2 * Copyright (c) 2016 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _HNS_ROCE_DEVICE_H
34 #define _HNS_ROCE_DEVICE_H
36 #include <rdma/ib_verbs.h>
37 #include <rdma/hns-abi.h>
39 #define DRV_NAME "hns_roce"
41 #define PCI_REVISION_ID_HIP08 0x21
42 #define PCI_REVISION_ID_HIP09 0x30
44 #define HNS_ROCE_HW_VER1 ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
46 #define HNS_ROCE_MAX_MSG_LEN 0x80000000
48 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6
52 /* Hardware specification only for v1 engine */
53 #define HNS_ROCE_MIN_CQE_NUM 0x40
54 #define HNS_ROCE_MIN_WQE_NUM 0x20
55 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1
57 /* Hardware specification only for v1 engine */
58 #define HNS_ROCE_MAX_INNER_MTPT_NUM 0x7
59 #define HNS_ROCE_MAX_MTPT_PBL_NUM 0x100000
61 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS 20
62 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT \
63 (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
64 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT 0x2
65 #define HNS_ROCE_MIN_CQE_CNT 16
67 #define HNS_ROCE_RESERVED_SGE 1
69 #define HNS_ROCE_MAX_IRQ_NUM 128
71 #define HNS_ROCE_SGE_IN_WQE 2
72 #define HNS_ROCE_SGE_SHIFT 4
77 #define HNS_ROCE_CEQ 0
78 #define HNS_ROCE_AEQ 1
80 #define HNS_ROCE_CEQE_SIZE 0x4
81 #define HNS_ROCE_AEQE_SIZE 0x10
83 #define HNS_ROCE_V3_EQE_SIZE 0x40
85 #define HNS_ROCE_V2_CQE_SIZE 32
86 #define HNS_ROCE_V3_CQE_SIZE 64
88 #define HNS_ROCE_V2_QPC_SZ 256
89 #define HNS_ROCE_V3_QPC_SZ 512
91 #define HNS_ROCE_MAX_PORTS 6
92 #define HNS_ROCE_GID_SIZE 16
93 #define HNS_ROCE_SGE_SIZE 16
94 #define HNS_ROCE_DWQE_SIZE 65536
96 #define HNS_ROCE_HOP_NUM_0 0xff
98 #define MR_TYPE_MR 0x00
99 #define MR_TYPE_FRMR 0x01
100 #define MR_TYPE_DMA 0x03
102 #define HNS_ROCE_FRMR_MAX_PA 512
104 #define PKEY_ID 0xffff
106 #define NODE_DESC_SIZE 64
107 #define DB_REG_OFFSET 0x1000
109 /* Configure to HW for PAGE_SIZE larger than 4KB */
110 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12)
112 #define PAGES_SHIFT_8 8
113 #define PAGES_SHIFT_16 16
114 #define PAGES_SHIFT_24 24
115 #define PAGES_SHIFT_32 32
117 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4
118 #define SRQ_DB_REG 0x230
120 #define HNS_ROCE_QP_BANK_NUM 8
121 #define HNS_ROCE_CQ_BANK_NUM 4
123 #define CQ_BANKID_SHIFT 2
125 /* The chip implementation of the consumer index is calculated
126 * according to twice the actual EQ depth
128 #define EQ_DEPTH_COEFF 2
138 enum hns_roce_qp_state {
139 HNS_ROCE_QP_STATE_RST,
140 HNS_ROCE_QP_STATE_INIT,
141 HNS_ROCE_QP_STATE_RTR,
142 HNS_ROCE_QP_STATE_RTS,
143 HNS_ROCE_QP_STATE_SQD,
144 HNS_ROCE_QP_STATE_ERR,
145 HNS_ROCE_QP_NUM_STATE,
148 enum hns_roce_event {
149 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01,
150 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02,
151 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03,
152 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04,
153 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
154 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06,
155 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07,
156 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08,
157 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09,
158 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a,
159 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b,
160 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c,
161 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d,
162 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f,
163 /* 0x10 and 0x11 is unused in currently application case */
164 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12,
165 HNS_ROCE_EVENT_TYPE_MB = 0x13,
166 HNS_ROCE_EVENT_TYPE_FLR = 0x15,
167 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16,
168 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17,
171 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12
174 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0),
175 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1),
176 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2),
177 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3),
178 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4),
179 HNS_ROCE_CAP_FLAG_SRQ = BIT(5),
180 HNS_ROCE_CAP_FLAG_XRC = BIT(6),
181 HNS_ROCE_CAP_FLAG_MW = BIT(7),
182 HNS_ROCE_CAP_FLAG_FRMR = BIT(8),
183 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9),
184 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10),
185 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14),
186 HNS_ROCE_CAP_FLAG_STASH = BIT(17),
189 #define HNS_ROCE_DB_TYPE_COUNT 2
190 #define HNS_ROCE_DB_UNIT_SIZE 4
193 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
196 enum hns_roce_reset_stage {
197 HNS_ROCE_STATE_NON_RST,
198 HNS_ROCE_STATE_RST_BEF_DOWN,
199 HNS_ROCE_STATE_RST_DOWN,
200 HNS_ROCE_STATE_RST_UNINIT,
201 HNS_ROCE_STATE_RST_INIT,
202 HNS_ROCE_STATE_RST_INITED,
205 enum hns_roce_instance_state {
206 HNS_ROCE_STATE_NON_INIT,
208 HNS_ROCE_STATE_INITED,
209 HNS_ROCE_STATE_UNINIT,
213 HNS_ROCE_RST_DIRECT_RETURN = 0,
216 #define HNS_ROCE_CMD_SUCCESS 1
218 /* The minimum page size is 4K for hardware */
219 #define HNS_HW_PAGE_SHIFT 12
220 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT)
222 struct hns_roce_uar {
225 unsigned long logic_idx;
228 struct hns_roce_ucontext {
229 struct ib_ucontext ibucontext;
230 struct hns_roce_uar uar;
231 struct list_head page_list;
232 struct mutex page_mutex;
240 struct hns_roce_xrcd {
241 struct ib_xrcd ibxrcd;
245 struct hns_roce_bitmap {
246 /* Bitmap Traversal last a bit which is 1 */
250 unsigned long reserved_top;
253 unsigned long *table;
256 struct hns_roce_ida {
258 u32 min; /* Lowest ID to allocate. */
259 u32 max; /* Highest ID to allocate. */
262 /* For Hardware Entry Memory */
263 struct hns_roce_hem_table {
264 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
266 /* HEM array elment num */
267 unsigned long num_hem;
268 /* Single obj size */
269 unsigned long obj_size;
270 unsigned long table_chunk_size;
273 struct hns_roce_hem **hem;
275 dma_addr_t *bt_l1_dma_addr;
277 dma_addr_t *bt_l0_dma_addr;
280 struct hns_roce_buf_region {
281 u32 offset; /* page offset */
282 u32 count; /* page count */
283 int hopnum; /* addressing hop num */
286 #define HNS_ROCE_MAX_BT_REGION 3
287 #define HNS_ROCE_MAX_BT_LEVEL 3
288 struct hns_roce_hem_list {
289 struct list_head root_bt;
290 /* link all bt dma mem by hop config */
291 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
292 struct list_head btm_bt; /* link all bottom bt in @mid_bt */
293 dma_addr_t root_ba; /* pointer to the root ba table */
296 struct hns_roce_buf_attr {
298 size_t size; /* region size */
299 int hopnum; /* multi-hop addressing hop num */
300 } region[HNS_ROCE_MAX_BT_REGION];
301 unsigned int region_count; /* valid region count */
302 unsigned int page_shift; /* buffer page shift */
303 unsigned int user_access; /* umem access flag */
304 bool mtt_only; /* only alloc buffer-required MTT memory */
307 struct hns_roce_hem_cfg {
308 dma_addr_t root_ba; /* root BA table's address */
309 bool is_direct; /* addressing without BA table */
310 unsigned int ba_pg_shift; /* BA table page shift */
311 unsigned int buf_pg_shift; /* buffer page shift */
312 unsigned int buf_pg_count; /* buffer page count */
313 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
314 unsigned int region_count;
317 /* memory translate region */
318 struct hns_roce_mtr {
319 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
320 struct ib_umem *umem; /* user space buffer */
321 struct hns_roce_buf *kmem; /* kernel space buffer */
322 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */
329 int enabled; /* MW's active status */
335 /* Only support 4K page size for mr register */
340 u64 iova; /* MR's virtual original addr */
341 u64 size; /* Address range of MR */
342 u32 key; /* Key of MR */
343 u32 pd; /* PD num of MR */
344 u32 access; /* Access permission of MR */
345 int enabled; /* MR's active status */
346 int type; /* MR's register type */
347 u32 pbl_hop_num; /* multi-hop number */
348 struct hns_roce_mtr pbl_mtr;
350 dma_addr_t *page_list;
353 struct hns_roce_mr_table {
354 struct hns_roce_ida mtpt_ida;
355 struct hns_roce_hem_table mtpt_table;
359 u64 *wrid; /* Work request ID */
361 u32 wqe_cnt; /* WQE num */
365 int wqe_shift; /* WQE size */
368 void __iomem *db_reg;
371 struct hns_roce_sge {
372 unsigned int sge_cnt; /* SGE num */
374 int sge_shift; /* SGE size */
377 struct hns_roce_buf_list {
383 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
386 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
388 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
389 * the allocated size is smaller than the required size.
392 HNS_ROCE_BUF_DIRECT = BIT(0),
393 HNS_ROCE_BUF_NOSLEEP = BIT(1),
394 HNS_ROCE_BUF_NOFAIL = BIT(2),
397 struct hns_roce_buf {
398 struct hns_roce_buf_list *trunk_list;
401 unsigned int trunk_shift;
402 unsigned int page_shift;
405 struct hns_roce_db_pgdir {
406 struct list_head list;
407 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
408 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
409 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT];
414 struct hns_roce_user_db_page {
415 struct list_head list;
416 struct ib_umem *umem;
417 unsigned long user_virt;
424 struct hns_roce_db_pgdir *pgdir;
425 struct hns_roce_user_db_page *user_page;
435 struct hns_roce_mtr mtr;
436 struct hns_roce_db db;
442 void __iomem *db_reg;
449 struct completion free;
450 struct list_head sq_list; /* all qps on this send cq */
451 struct list_head rq_list; /* all qps on this recv cq */
452 int is_armed; /* cq is armed */
453 struct list_head node; /* all armed cqs are on a list */
456 struct hns_roce_idx_que {
457 struct hns_roce_mtr mtr;
459 unsigned long *bitmap;
464 struct hns_roce_srq {
473 void __iomem *db_reg;
476 struct completion free;
478 struct hns_roce_mtr buf_mtr;
481 struct hns_roce_idx_que idx_que;
484 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
487 struct hns_roce_uar_table {
488 struct hns_roce_bitmap bitmap;
491 struct hns_roce_bank {
493 u32 inuse; /* Number of IDs allocated */
494 u32 min; /* Lowest ID to allocate. */
495 u32 max; /* Highest ID to allocate. */
496 u32 next; /* Next ID to allocate. */
499 struct hns_roce_qp_table {
500 struct hns_roce_hem_table qp_table;
501 struct hns_roce_hem_table irrl_table;
502 struct hns_roce_hem_table trrl_table;
503 struct hns_roce_hem_table sccc_table;
504 struct mutex scc_mutex;
505 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
506 struct mutex bank_mutex;
509 struct hns_roce_cq_table {
511 struct hns_roce_hem_table table;
512 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
513 struct mutex bank_mutex;
516 struct hns_roce_srq_table {
517 struct hns_roce_bitmap bitmap;
519 struct hns_roce_hem_table table;
522 struct hns_roce_raq_table {
523 struct hns_roce_buf_list *e_raq_buf;
535 u8 dgid[HNS_ROCE_GID_SIZE];
543 struct hns_roce_av av;
546 struct hns_roce_cmd_context {
547 struct completion done;
555 struct hns_roce_cmdq {
556 struct dma_pool *pool;
557 struct semaphore poll_sem;
559 * Event mode: cmd register mutex protection,
560 * ensure to not exceed max_cmds and user use limit region
562 struct semaphore event_sem;
564 spinlock_t context_lock;
566 struct hns_roce_cmd_context *context;
568 * Process whether use event mode, init default non-zero
569 * After the event queue of cmd event ready,
570 * can switch into event mode
571 * close device, switch into poll mode(non event mode)
576 struct hns_roce_cmd_mailbox {
583 struct hns_roce_rinl_sge {
588 struct hns_roce_rinl_wqe {
589 struct hns_roce_rinl_sge *sg_list;
593 struct hns_roce_rinl_buf {
594 struct hns_roce_rinl_wqe *wqe_list;
599 HNS_ROCE_FLUSH_FLAG = 0,
602 struct hns_roce_work {
603 struct hns_roce_dev *hr_dev;
604 struct work_struct work;
611 HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5),
616 struct hns_roce_wq rq;
617 struct hns_roce_db rdb;
618 struct hns_roce_db sdb;
619 unsigned long en_flags;
621 enum ib_sig_type sq_signal_bits;
622 struct hns_roce_wq sq;
624 struct hns_roce_mtr mtr;
637 void (*event)(struct hns_roce_qp *qp,
638 enum hns_roce_event event_type);
644 struct completion free;
646 struct hns_roce_sge sge;
648 enum ib_mtu path_mtu;
651 /* 0: flush needed, 1: unneeded */
652 unsigned long flush_flag;
653 struct hns_roce_work flush_work;
654 struct hns_roce_rinl_buf rq_inl_buf;
655 struct list_head node; /* all qps are on a list */
656 struct list_head rq_node; /* all recv qps are on a list */
657 struct list_head sq_node; /* all send qps are on a list */
660 struct hns_roce_ib_iboe {
662 struct net_device *netdevs[HNS_ROCE_MAX_PORTS];
663 struct notifier_block nb;
664 u8 phy_port[HNS_ROCE_MAX_PORTS];
668 HNS_ROCE_EQ_STAT_INVALID = 0,
669 HNS_ROCE_EQ_STAT_VALID = 2,
672 struct hns_roce_ceqe {
677 struct hns_roce_aeqe {
697 struct hns_roce_dev *hr_dev;
698 void __iomem *db_reg;
700 int type_flag; /* Aeq:1 ceq:0 */
708 struct hns_roce_buf_list *buf_list;
713 struct hns_roce_mtr mtr;
721 struct hns_roce_eq_table {
722 struct hns_roce_eq *eq;
723 void __iomem **eqc_base; /* only for hw v1 */
733 struct hns_roce_caps {
736 int gid_table_len[HNS_ROCE_MAX_PORTS];
737 int pkey_table_len[HNS_ROCE_MAX_PORTS];
738 int local_ca_ack_delay;
757 int max_qp_init_rdma;
758 int max_qp_dest_rdma;
766 int num_comp_vectors;
767 int num_other_vectors;
788 int qpc_timer_entry_sz;
789 int cqc_timer_entry_sz;
801 u32 qpc_timer_bt_num;
804 u32 cqc_timer_bt_num;
832 u32 qpc_timer_ba_pg_sz;
833 u32 qpc_timer_buf_pg_sz;
834 u32 qpc_timer_hop_num;
835 u32 cqc_timer_ba_pg_sz;
836 u32 cqc_timer_buf_pg_sz;
837 u32 cqc_timer_hop_num;
838 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */
842 u32 srqwqe_buf_pg_sz;
857 u32 chunk_sz; /* chunk size in non multihop mode */
859 u16 default_ceq_max_cnt;
860 u16 default_ceq_period;
861 u16 default_aeq_max_cnt;
862 u16 default_aeq_period;
863 u16 default_aeq_arm_st;
864 u16 default_ceq_arm_st;
865 enum cong_type cong_type;
868 struct hns_roce_dfx_hw {
869 int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
873 enum hns_roce_device_state {
874 HNS_ROCE_DEVICE_STATE_INITED,
875 HNS_ROCE_DEVICE_STATE_RST_DOWN,
876 HNS_ROCE_DEVICE_STATE_UNINIT,
880 int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
881 int (*cmq_init)(struct hns_roce_dev *hr_dev);
882 void (*cmq_exit)(struct hns_roce_dev *hr_dev);
883 int (*hw_profile)(struct hns_roce_dev *hr_dev);
884 int (*hw_init)(struct hns_roce_dev *hr_dev);
885 void (*hw_exit)(struct hns_roce_dev *hr_dev);
886 int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
887 u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
888 u16 token, int event);
889 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev,
890 unsigned int timeout);
891 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy);
892 int (*set_gid)(struct hns_roce_dev *hr_dev, u32 port, int gid_index,
893 const union ib_gid *gid, const struct ib_gid_attr *attr);
894 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
895 void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
897 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
898 struct hns_roce_mr *mr, unsigned long mtpt_idx);
899 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
900 struct hns_roce_mr *mr, int flags,
902 int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
903 struct hns_roce_mr *mr);
904 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
905 void (*write_cqc)(struct hns_roce_dev *hr_dev,
906 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
907 dma_addr_t dma_handle);
908 int (*set_hem)(struct hns_roce_dev *hr_dev,
909 struct hns_roce_hem_table *table, int obj, int step_idx);
910 int (*clear_hem)(struct hns_roce_dev *hr_dev,
911 struct hns_roce_hem_table *table, int obj,
913 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
914 int attr_mask, enum ib_qp_state cur_state,
915 enum ib_qp_state new_state);
916 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
917 struct hns_roce_qp *hr_qp);
918 int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
919 struct ib_udata *udata);
920 int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
921 int (*init_eq)(struct hns_roce_dev *hr_dev);
922 void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
923 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
924 const struct ib_device_ops *hns_roce_dev_ops;
925 const struct ib_device_ops *hns_roce_dev_srq_ops;
928 struct hns_roce_dev {
929 struct ib_device ib_dev;
930 struct platform_device *pdev;
931 struct pci_dev *pci_dev;
933 struct hns_roce_uar priv_uar;
934 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM];
936 spinlock_t bt_cmd_lock;
940 unsigned long reset_cnt;
941 struct hns_roce_ib_iboe iboe;
942 enum hns_roce_device_state state;
943 struct list_head qp_list; /* list of all qps on this dev */
944 spinlock_t qp_list_lock; /* protect qp_list */
945 struct list_head dip_list; /* list of all dest ips on this dev */
946 spinlock_t dip_list_lock; /* protect dip_list */
948 struct list_head pgdir_list;
949 struct mutex pgdir_mutex;
950 int irq[HNS_ROCE_MAX_IRQ_NUM];
951 u8 __iomem *reg_base;
952 void __iomem *mem_base;
953 struct hns_roce_caps caps;
954 struct xarray qp_table_xa;
956 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
961 void __iomem *priv_addr;
963 struct hns_roce_cmdq cmd;
964 struct hns_roce_ida pd_ida;
965 struct hns_roce_ida xrcd_ida;
966 struct hns_roce_uar_table uar_table;
967 struct hns_roce_mr_table mr_table;
968 struct hns_roce_cq_table cq_table;
969 struct hns_roce_srq_table srq_table;
970 struct hns_roce_qp_table qp_table;
971 struct hns_roce_eq_table eq_table;
972 struct hns_roce_hem_table qpc_timer_table;
973 struct hns_roce_hem_table cqc_timer_table;
974 /* GMV is the memory area that the driver allocates for the hardware
975 * to store SGID, SMAC and VLAN information.
977 struct hns_roce_hem_table gmv_table;
983 dma_addr_t tptr_dma_addr; /* only for hw v1 */
984 u32 tptr_size; /* only for hw v1 */
985 const struct hns_roce_hw *hw;
987 struct workqueue_struct *irq_workq;
988 const struct hns_roce_dfx_hw *dfx;
991 u32 cong_algo_tmpl_id;
994 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
996 return container_of(ib_dev, struct hns_roce_dev, ib_dev);
999 static inline struct hns_roce_ucontext
1000 *to_hr_ucontext(struct ib_ucontext *ibucontext)
1002 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1005 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1007 return container_of(ibpd, struct hns_roce_pd, ibpd);
1010 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd)
1012 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd);
1015 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1017 return container_of(ibah, struct hns_roce_ah, ibah);
1020 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1022 return container_of(ibmr, struct hns_roce_mr, ibmr);
1025 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1027 return container_of(ibmw, struct hns_roce_mw, ibmw);
1030 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1032 return container_of(ibqp, struct hns_roce_qp, ibqp);
1035 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1037 return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1040 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1042 return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1045 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1047 writeq(*(u64 *)val, dest);
1050 static inline struct hns_roce_qp
1051 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1053 return xa_load(&hr_dev->qp_table_xa, qpn);
1056 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
1057 unsigned int offset)
1059 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1060 (offset & ((1 << buf->trunk_shift) - 1));
1063 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf,
1064 unsigned int offset)
1066 return buf->trunk_list[offset >> buf->trunk_shift].map +
1067 (offset & ((1 << buf->trunk_shift) - 1));
1070 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
1072 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift);
1075 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1077 static inline u64 to_hr_hw_page_addr(u64 addr)
1079 return addr >> HNS_HW_PAGE_SHIFT;
1082 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1084 return page_shift - HNS_HW_PAGE_SHIFT;
1087 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1090 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1095 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1097 return hr_hw_page_align(count << buf_shift);
1100 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1102 return hr_hw_page_align(count << buf_shift) >> buf_shift;
1105 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1110 return ilog2(to_hr_hem_entries_count(count, buf_shift));
1113 #define DSCP_SHIFT 2
1115 static inline u8 get_tclass(const struct ib_global_route *grh)
1117 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
1118 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
1121 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
1122 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1123 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1124 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
1126 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1127 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1128 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1130 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1131 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1133 /* hns roce hw need current block and next block addr from mtt */
1134 #define MTT_MIN_COUNT 2
1135 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1136 int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1137 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1138 struct hns_roce_buf_attr *buf_attr,
1139 unsigned int page_shift, struct ib_udata *udata,
1140 unsigned long user_addr);
1141 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1142 struct hns_roce_mtr *mtr);
1143 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1144 dma_addr_t *pages, unsigned int page_cnt);
1146 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1147 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1148 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1149 void hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1150 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1151 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev);
1153 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1154 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1155 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1156 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev);
1158 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
1159 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj);
1160 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
1161 u32 reserved_bot, u32 resetrved_top);
1162 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
1163 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1165 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1166 struct ib_udata *udata);
1167 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1168 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1173 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1174 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1176 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1177 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1178 u64 virt_addr, int access_flags,
1179 struct ib_udata *udata);
1180 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
1181 u64 length, u64 virt_addr,
1182 int mr_access_flags, struct ib_pd *pd,
1183 struct ib_udata *udata);
1184 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1186 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1187 unsigned int *sg_offset);
1188 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1189 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
1190 struct hns_roce_cmd_mailbox *mailbox,
1191 unsigned long mpt_index);
1192 unsigned long key_to_hw_index(u32 key);
1194 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1195 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1197 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1198 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1199 u32 page_shift, u32 flags);
1201 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1202 int buf_cnt, struct hns_roce_buf *buf,
1203 unsigned int page_shift);
1204 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1205 int buf_cnt, struct ib_umem *umem,
1206 unsigned int page_shift);
1208 int hns_roce_create_srq(struct ib_srq *srq,
1209 struct ib_srq_init_attr *srq_init_attr,
1210 struct ib_udata *udata);
1211 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1212 enum ib_srq_attr_mask srq_attr_mask,
1213 struct ib_udata *udata);
1214 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1216 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1217 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata);
1219 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
1220 struct ib_qp_init_attr *init_attr,
1221 struct ib_udata *udata);
1222 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1223 int attr_mask, struct ib_udata *udata);
1224 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1225 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1226 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1227 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
1228 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1229 struct ib_cq *ib_cq);
1230 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1231 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1232 struct hns_roce_cq *recv_cq);
1233 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1234 struct hns_roce_cq *recv_cq);
1235 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1236 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1237 struct ib_udata *udata);
1238 __be32 send_ieth(const struct ib_send_wr *wr);
1239 int to_hr_qp_type(int qp_type);
1241 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1242 struct ib_udata *udata);
1244 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1245 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt,
1246 struct hns_roce_db *db);
1247 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1248 struct hns_roce_db *db);
1249 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1251 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1253 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1254 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1255 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp);
1256 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1257 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1258 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u32 port, int gid_index);
1259 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1260 int hns_roce_init(struct hns_roce_dev *hr_dev);
1261 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1262 int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
1263 struct ib_cq *ib_cq);
1264 #endif /* _HNS_ROCE_DEVICE_H */