drivers/infiniband/hw/hns/hns_roce_device.h

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _HNS_ROCE_DEVICE_H
  34 #define _HNS_ROCE_DEVICE_H
  35
  36 #include <rdma/ib_verbs.h>
  37 #include <rdma/hns-abi.h>
  38
  39 #define DRV_NAME "hns_roce"
  40
  41 #define PCI_REVISION_ID_HIP08                   0x21
  42 #define PCI_REVISION_ID_HIP09                   0x30
  43
  44 #define HNS_ROCE_HW_VER1        ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
  45
  46 #define HNS_ROCE_MAX_MSG_LEN                    0x80000000
  47
  48 #define HNS_ROCE_IB_MIN_SQ_STRIDE               6
  49
  50 #define HNS_ROCE_BA_SIZE                        (32 * 4096)
  51
  52 #define BA_BYTE_LEN                             8
  53
  54 /* Hardware specification only for v1 engine */
  55 #define HNS_ROCE_MIN_CQE_NUM                    0x40
  56 #define HNS_ROCE_MIN_WQE_NUM                    0x20
  57
  58 /* Hardware specification only for v1 engine */
  59 #define HNS_ROCE_MAX_INNER_MTPT_NUM             0x7
  60 #define HNS_ROCE_MAX_MTPT_PBL_NUM               0x100000
  61
  62 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS        20
  63 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT   \
  64         (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
  65 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT             0x2
  66 #define HNS_ROCE_MIN_CQE_CNT                    16
  67
  68 #define HNS_ROCE_RESERVED_SGE                   1
  69
  70 #define HNS_ROCE_MAX_IRQ_NUM                    128
  71
  72 #define HNS_ROCE_SGE_IN_WQE                     2
  73 #define HNS_ROCE_SGE_SHIFT                      4
  74
  75 #define EQ_ENABLE                               1
  76 #define EQ_DISABLE                              0
  77
  78 #define HNS_ROCE_CEQ                            0
  79 #define HNS_ROCE_AEQ                            1
  80
  81 #define HNS_ROCE_CEQE_SIZE 0x4
  82 #define HNS_ROCE_AEQE_SIZE 0x10
  83
  84 #define HNS_ROCE_V3_EQE_SIZE 0x40
  85
  86 #define HNS_ROCE_V2_CQE_SIZE 32
  87 #define HNS_ROCE_V3_CQE_SIZE 64
  88
  89 #define HNS_ROCE_V2_QPC_SZ 256
  90 #define HNS_ROCE_V3_QPC_SZ 512
  91
  92 #define HNS_ROCE_MAX_PORTS                      6
  93 #define HNS_ROCE_GID_SIZE                       16
  94 #define HNS_ROCE_SGE_SIZE                       16
  95
  96 #define HNS_ROCE_HOP_NUM_0                      0xff
  97
  98 #define BITMAP_NO_RR                            0
  99 #define BITMAP_RR                               1
 100
 101 #define MR_TYPE_MR                              0x00
 102 #define MR_TYPE_FRMR                            0x01
 103 #define MR_TYPE_DMA                             0x03
 104
 105 #define HNS_ROCE_FRMR_MAX_PA                    512
 106
 107 #define PKEY_ID                                 0xffff
 108 #define GUID_LEN                                8
 109 #define NODE_DESC_SIZE                          64
 110 #define DB_REG_OFFSET                           0x1000
 111
 112 /* Configure to HW for PAGE_SIZE larger than 4KB */
 113 #define PG_SHIFT_OFFSET                         (PAGE_SHIFT - 12)
 114
 115 #define PAGES_SHIFT_8                           8
 116 #define PAGES_SHIFT_16                          16
 117 #define PAGES_SHIFT_24                          24
 118 #define PAGES_SHIFT_32                          32
 119
 120 #define HNS_ROCE_IDX_QUE_ENTRY_SZ               4
 121 #define SRQ_DB_REG                              0x230
 122
 123 #define HNS_ROCE_QP_BANK_NUM 8
 124 #define HNS_ROCE_CQ_BANK_NUM 4
 125
 126 #define CQ_BANKID_SHIFT 2
 127
 128 /* The chip implementation of the consumer index is calculated
 129  * according to twice the actual EQ depth
 130  */
 131 #define EQ_DEPTH_COEFF                          2
 132
 133 enum {
 134         SERV_TYPE_RC,
 135         SERV_TYPE_UC,
 136         SERV_TYPE_RD,
 137         SERV_TYPE_UD,
 138 };
 139
 140 enum hns_roce_qp_state {
 141         HNS_ROCE_QP_STATE_RST,
 142         HNS_ROCE_QP_STATE_INIT,
 143         HNS_ROCE_QP_STATE_RTR,
 144         HNS_ROCE_QP_STATE_RTS,
 145         HNS_ROCE_QP_STATE_SQD,
 146         HNS_ROCE_QP_STATE_ERR,
 147         HNS_ROCE_QP_NUM_STATE,
 148 };
 149
 150 enum hns_roce_event {
 151         HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
 152         HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
 153         HNS_ROCE_EVENT_TYPE_COMM_EST                  = 0x03,
 154         HNS_ROCE_EVENT_TYPE_SQ_DRAINED                = 0x04,
 155         HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR            = 0x05,
 156         HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR    = 0x06,
 157         HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR     = 0x07,
 158         HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH           = 0x08,
 159         HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH        = 0x09,
 160         HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR           = 0x0a,
 161         HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR           = 0x0b,
 162         HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW               = 0x0c,
 163         HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID             = 0x0d,
 164         HNS_ROCE_EVENT_TYPE_PORT_CHANGE               = 0x0f,
 165         /* 0x10 and 0x11 is unused in currently application case */
 166         HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,
 167         HNS_ROCE_EVENT_TYPE_MB                        = 0x13,
 168         HNS_ROCE_EVENT_TYPE_FLR                       = 0x15,
 169 };
 170
 171 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
 172 enum {
 173         HNS_ROCE_LWQCE_QPC_ERROR                = 1,
 174         HNS_ROCE_LWQCE_MTU_ERROR                = 2,
 175         HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR        = 3,
 176         HNS_ROCE_LWQCE_WQE_ADDR_ERROR           = 4,
 177         HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR       = 5,
 178         HNS_ROCE_LWQCE_SL_ERROR                 = 6,
 179         HNS_ROCE_LWQCE_PORT_ERROR               = 7,
 180 };
 181
 182 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
 183 enum {
 184         HNS_ROCE_LAVWQE_R_KEY_VIOLATION         = 1,
 185         HNS_ROCE_LAVWQE_LENGTH_ERROR            = 2,
 186         HNS_ROCE_LAVWQE_VA_ERROR                = 3,
 187         HNS_ROCE_LAVWQE_PD_ERROR                = 4,
 188         HNS_ROCE_LAVWQE_RW_ACC_ERROR            = 5,
 189         HNS_ROCE_LAVWQE_KEY_STATE_ERROR         = 6,
 190         HNS_ROCE_LAVWQE_MR_OPERATION_ERROR      = 7,
 191 };
 192
 193 /* DOORBELL overflow subtype */
 194 enum {
 195         HNS_ROCE_DB_SUBTYPE_SDB_OVF             = 1,
 196         HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF         = 2,
 197         HNS_ROCE_DB_SUBTYPE_ODB_OVF             = 3,
 198         HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF         = 4,
 199         HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP         = 5,
 200         HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP         = 6,
 201 };
 202
 203 enum {
 204         /* RQ&SRQ related operations */
 205         HNS_ROCE_OPCODE_SEND_DATA_RECEIVE       = 0x06,
 206         HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE   = 0x07,
 207 };
 208
 209 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12
 210
 211 enum {
 212         HNS_ROCE_CAP_FLAG_REREG_MR              = BIT(0),
 213         HNS_ROCE_CAP_FLAG_ROCE_V1_V2            = BIT(1),
 214         HNS_ROCE_CAP_FLAG_RQ_INLINE             = BIT(2),
 215         HNS_ROCE_CAP_FLAG_RECORD_DB             = BIT(3),
 216         HNS_ROCE_CAP_FLAG_SQ_RECORD_DB          = BIT(4),
 217         HNS_ROCE_CAP_FLAG_SRQ                   = BIT(5),
 218         HNS_ROCE_CAP_FLAG_MW                    = BIT(7),
 219         HNS_ROCE_CAP_FLAG_FRMR                  = BIT(8),
 220         HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL          = BIT(9),
 221         HNS_ROCE_CAP_FLAG_ATOMIC                = BIT(10),
 222         HNS_ROCE_CAP_FLAG_SDI_MODE              = BIT(14),
 223         HNS_ROCE_CAP_FLAG_STASH                 = BIT(17),
 224 };
 225
 226 #define HNS_ROCE_DB_TYPE_COUNT                  2
 227 #define HNS_ROCE_DB_UNIT_SIZE                   4
 228
 229 enum {
 230         HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
 231 };
 232
 233 enum hns_roce_reset_stage {
 234         HNS_ROCE_STATE_NON_RST,
 235         HNS_ROCE_STATE_RST_BEF_DOWN,
 236         HNS_ROCE_STATE_RST_DOWN,
 237         HNS_ROCE_STATE_RST_UNINIT,
 238         HNS_ROCE_STATE_RST_INIT,
 239         HNS_ROCE_STATE_RST_INITED,
 240 };
 241
 242 enum hns_roce_instance_state {
 243         HNS_ROCE_STATE_NON_INIT,
 244         HNS_ROCE_STATE_INIT,
 245         HNS_ROCE_STATE_INITED,
 246         HNS_ROCE_STATE_UNINIT,
 247 };
 248
 249 enum {
 250         HNS_ROCE_RST_DIRECT_RETURN              = 0,
 251 };
 252
 253 enum {
 254         CMD_RST_PRC_OTHERS,
 255         CMD_RST_PRC_SUCCESS,
 256         CMD_RST_PRC_EBUSY,
 257 };
 258
 259 #define HNS_ROCE_CMD_SUCCESS                    1
 260
 261 #define HNS_ROCE_PORT_DOWN                      0
 262 #define HNS_ROCE_PORT_UP                        1
 263
 264 /* The minimum page size is 4K for hardware */
 265 #define HNS_HW_PAGE_SHIFT                       12
 266 #define HNS_HW_PAGE_SIZE                        (1 << HNS_HW_PAGE_SHIFT)
 267
 268 struct hns_roce_uar {
 269         u64             pfn;
 270         unsigned long   index;
 271         unsigned long   logic_idx;
 272 };
 273
 274 struct hns_roce_ucontext {
 275         struct ib_ucontext      ibucontext;
 276         struct hns_roce_uar     uar;
 277         struct list_head        page_list;
 278         struct mutex            page_mutex;
 279 };
 280
 281 struct hns_roce_pd {
 282         struct ib_pd            ibpd;
 283         unsigned long           pdn;
 284 };
 285
 286 struct hns_roce_bitmap {
 287         /* Bitmap Traversal last a bit which is 1 */
 288         unsigned long           last;
 289         unsigned long           top;
 290         unsigned long           max;
 291         unsigned long           reserved_top;
 292         unsigned long           mask;
 293         spinlock_t              lock;
 294         unsigned long           *table;
 295 };
 296
 297 /* For Hardware Entry Memory */
 298 struct hns_roce_hem_table {
 299         /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
 300         u32             type;
 301         /* HEM array elment num */
 302         unsigned long   num_hem;
 303         /* HEM entry record obj total num */
 304         unsigned long   num_obj;
 305         /* Single obj size */
 306         unsigned long   obj_size;
 307         unsigned long   table_chunk_size;
 308         int             lowmem;
 309         struct mutex    mutex;
 310         struct hns_roce_hem **hem;
 311         u64             **bt_l1;
 312         dma_addr_t      *bt_l1_dma_addr;
 313         u64             **bt_l0;
 314         dma_addr_t      *bt_l0_dma_addr;
 315 };
 316
 317 struct hns_roce_buf_region {
 318         u32 offset; /* page offset */
 319         u32 count; /* page count */
 320         int hopnum; /* addressing hop num */
 321 };
 322
 323 #define HNS_ROCE_MAX_BT_REGION  3
 324 #define HNS_ROCE_MAX_BT_LEVEL   3
 325 struct hns_roce_hem_list {
 326         struct list_head root_bt;
 327         /* link all bt dma mem by hop config */
 328         struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
 329         struct list_head btm_bt; /* link all bottom bt in @mid_bt */
 330         dma_addr_t root_ba; /* pointer to the root ba table */
 331 };
 332
 333 struct hns_roce_buf_attr {
 334         struct {
 335                 size_t  size;  /* region size */
 336                 int     hopnum; /* multi-hop addressing hop num */
 337         } region[HNS_ROCE_MAX_BT_REGION];
 338         unsigned int region_count; /* valid region count */
 339         unsigned int page_shift;  /* buffer page shift */
 340         unsigned int user_access; /* umem access flag */
 341         bool mtt_only; /* only alloc buffer-required MTT memory */
 342 };
 343
 344 struct hns_roce_hem_cfg {
 345         dma_addr_t      root_ba; /* root BA table's address */
 346         bool            is_direct; /* addressing without BA table */
 347         unsigned int    ba_pg_shift; /* BA table page shift */
 348         unsigned int    buf_pg_shift; /* buffer page shift */
 349         unsigned int    buf_pg_count;  /* buffer page count */
 350         struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
 351         unsigned int    region_count;
 352 };
 353
 354 /* memory translate region */
 355 struct hns_roce_mtr {
 356         struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
 357         struct ib_umem          *umem; /* user space buffer */
 358         struct hns_roce_buf     *kmem; /* kernel space buffer */
 359         struct hns_roce_hem_cfg  hem_cfg; /* config for hardware addressing */
 360 };
 361
 362 struct hns_roce_mw {
 363         struct ib_mw            ibmw;
 364         u32                     pdn;
 365         u32                     rkey;
 366         int                     enabled; /* MW's active status */
 367         u32                     pbl_hop_num;
 368         u32                     pbl_ba_pg_sz;
 369         u32                     pbl_buf_pg_sz;
 370 };
 371
 372 /* Only support 4K page size for mr register */
 373 #define MR_SIZE_4K 0
 374
 375 struct hns_roce_mr {
 376         struct ib_mr            ibmr;
 377         u64                     iova; /* MR's virtual orignal addr */
 378         u64                     size; /* Address range of MR */
 379         u32                     key; /* Key of MR */
 380         u32                     pd;   /* PD num of MR */
 381         u32                     access; /* Access permission of MR */
 382         int                     enabled; /* MR's active status */
 383         int                     type;   /* MR's register type */
 384         u32                     pbl_hop_num;    /* multi-hop number */
 385         struct hns_roce_mtr     pbl_mtr;
 386         u32                     npages;
 387         dma_addr_t              *page_list;
 388 };
 389
 390 struct hns_roce_mr_table {
 391         struct hns_roce_bitmap          mtpt_bitmap;
 392         struct hns_roce_hem_table       mtpt_table;
 393 };
 394
 395 struct hns_roce_wq {
 396         u64             *wrid;     /* Work request ID */
 397         spinlock_t      lock;
 398         u32             wqe_cnt;  /* WQE num */
 399         u32             max_gs;
 400         u32             rsv_sge;
 401         int             offset;
 402         int             wqe_shift;      /* WQE size */
 403         u32             head;
 404         u32             tail;
 405         void __iomem    *db_reg_l;
 406 };
 407
 408 struct hns_roce_sge {
 409         unsigned int    sge_cnt;        /* SGE num */
 410         int             offset;
 411         int             sge_shift;      /* SGE size */
 412 };
 413
 414 struct hns_roce_buf_list {
 415         void            *buf;
 416         dma_addr_t      map;
 417 };
 418
 419 /*
 420  * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
 421  * dma address range.
 422  *
 423  * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
 424  *
 425  * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
 426  * the allocated size is smaller than the required size.
 427  */
 428 enum {
 429         HNS_ROCE_BUF_DIRECT = BIT(0),
 430         HNS_ROCE_BUF_NOSLEEP = BIT(1),
 431         HNS_ROCE_BUF_NOFAIL = BIT(2),
 432 };
 433
 434 struct hns_roce_buf {
 435         struct hns_roce_buf_list        *trunk_list;
 436         u32                             ntrunks;
 437         u32                             npages;
 438         unsigned int                    trunk_shift;
 439         unsigned int                    page_shift;
 440 };
 441
 442 struct hns_roce_db_pgdir {
 443         struct list_head        list;
 444         DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
 445         DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
 446         unsigned long           *bits[HNS_ROCE_DB_TYPE_COUNT];
 447         u32                     *page;
 448         dma_addr_t              db_dma;
 449 };
 450
 451 struct hns_roce_user_db_page {
 452         struct list_head        list;
 453         struct ib_umem          *umem;
 454         unsigned long           user_virt;
 455         refcount_t              refcount;
 456 };
 457
 458 struct hns_roce_db {
 459         u32             *db_record;
 460         union {
 461                 struct hns_roce_db_pgdir *pgdir;
 462                 struct hns_roce_user_db_page *user_page;
 463         } u;
 464         dma_addr_t      dma;
 465         void            *virt_addr;
 466         unsigned long   index;
 467         unsigned long   order;
 468 };
 469
 470 struct hns_roce_cq {
 471         struct ib_cq                    ib_cq;
 472         struct hns_roce_mtr             mtr;
 473         struct hns_roce_db              db;
 474         u32                             flags;
 475         spinlock_t                      lock;
 476         u32                             cq_depth;
 477         u32                             cons_index;
 478         u32                             *set_ci_db;
 479         void __iomem                    *cq_db_l;
 480         u16                             *tptr_addr;
 481         int                             arm_sn;
 482         int                             cqe_size;
 483         unsigned long                   cqn;
 484         u32                             vector;
 485         atomic_t                        refcount;
 486         struct completion               free;
 487         struct list_head                sq_list; /* all qps on this send cq */
 488         struct list_head                rq_list; /* all qps on this recv cq */
 489         int                             is_armed; /* cq is armed */
 490         struct list_head                node; /* all armed cqs are on a list */
 491 };
 492
 493 struct hns_roce_idx_que {
 494         struct hns_roce_mtr             mtr;
 495         int                             entry_shift;
 496         unsigned long                   *bitmap;
 497         u32                             head;
 498         u32                             tail;
 499 };
 500
 501 struct hns_roce_srq {
 502         struct ib_srq           ibsrq;
 503         unsigned long           srqn;
 504         u32                     wqe_cnt;
 505         int                     max_gs;
 506         u32                     rsv_sge;
 507         int                     wqe_shift;
 508         void __iomem            *db_reg_l;
 509
 510         atomic_t                refcount;
 511         struct completion       free;
 512
 513         struct hns_roce_mtr     buf_mtr;
 514
 515         u64                    *wrid;
 516         struct hns_roce_idx_que idx_que;
 517         spinlock_t              lock;
 518         struct mutex            mutex;
 519         void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
 520 };
 521
 522 struct hns_roce_uar_table {
 523         struct hns_roce_bitmap bitmap;
 524 };
 525
 526 struct hns_roce_bank {
 527         struct ida ida;
 528         u32 inuse; /* Number of IDs allocated */
 529         u32 min; /* Lowest ID to allocate.  */
 530         u32 max; /* Highest ID to allocate. */
 531         u32 next; /* Next ID to allocate. */
 532 };
 533
 534 struct hns_roce_qp_table {
 535         struct hns_roce_hem_table       qp_table;
 536         struct hns_roce_hem_table       irrl_table;
 537         struct hns_roce_hem_table       trrl_table;
 538         struct hns_roce_hem_table       sccc_table;
 539         struct mutex                    scc_mutex;
 540         struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
 541         spinlock_t bank_lock;
 542 };
 543
 544 struct hns_roce_cq_table {
 545         struct xarray                   array;
 546         struct hns_roce_hem_table       table;
 547         struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
 548         struct mutex                    bank_mutex;
 549 };
 550
 551 struct hns_roce_srq_table {
 552         struct hns_roce_bitmap          bitmap;
 553         struct xarray                   xa;
 554         struct hns_roce_hem_table       table;
 555 };
 556
 557 struct hns_roce_raq_table {
 558         struct hns_roce_buf_list        *e_raq_buf;
 559 };
 560
 561 struct hns_roce_av {
 562         u8 port;
 563         u8 gid_index;
 564         u8 stat_rate;
 565         u8 hop_limit;
 566         u32 flowlabel;
 567         u16 udp_sport;
 568         u8 sl;
 569         u8 tclass;
 570         u8 dgid[HNS_ROCE_GID_SIZE];
 571         u8 mac[ETH_ALEN];
 572         u16 vlan_id;
 573         u8 vlan_en;
 574 };
 575
 576 struct hns_roce_ah {
 577         struct ib_ah            ibah;
 578         struct hns_roce_av      av;
 579 };
 580
 581 struct hns_roce_cmd_context {
 582         struct completion       done;
 583         int                     result;
 584         int                     next;
 585         u64                     out_param;
 586         u16                     token;
 587 };
 588
 589 struct hns_roce_cmdq {
 590         struct dma_pool         *pool;
 591         struct mutex            hcr_mutex;
 592         struct semaphore        poll_sem;
 593         /*
 594          * Event mode: cmd register mutex protection,
 595          * ensure to not exceed max_cmds and user use limit region
 596          */
 597         struct semaphore        event_sem;
 598         int                     max_cmds;
 599         spinlock_t              context_lock;
 600         int                     free_head;
 601         struct hns_roce_cmd_context *context;
 602         /*
 603          * Result of get integer part
 604          * which max_comds compute according a power of 2
 605          */
 606         u16                     token_mask;
 607         /*
 608          * Process whether use event mode, init default non-zero
 609          * After the event queue of cmd event ready,
 610          * can switch into event mode
 611          * close device, switch into poll mode(non event mode)
 612          */
 613         u8                      use_events;
 614 };
 615
 616 struct hns_roce_cmd_mailbox {
 617         void                   *buf;
 618         dma_addr_t              dma;
 619 };
 620
 621 struct hns_roce_dev;
 622
 623 struct hns_roce_rinl_sge {
 624         void                    *addr;
 625         u32                     len;
 626 };
 627
 628 struct hns_roce_rinl_wqe {
 629         struct hns_roce_rinl_sge *sg_list;
 630         u32                      sge_cnt;
 631 };
 632
 633 struct hns_roce_rinl_buf {
 634         struct hns_roce_rinl_wqe *wqe_list;
 635         u32                      wqe_cnt;
 636 };
 637
 638 enum {
 639         HNS_ROCE_FLUSH_FLAG = 0,
 640 };
 641
 642 struct hns_roce_work {
 643         struct hns_roce_dev *hr_dev;
 644         struct work_struct work;
 645         int event_type;
 646         int sub_type;
 647         u32 queue_num;
 648 };
 649
 650 struct hns_roce_qp {
 651         struct ib_qp            ibqp;
 652         struct hns_roce_wq      rq;
 653         struct hns_roce_db      rdb;
 654         struct hns_roce_db      sdb;
 655         unsigned long           en_flags;
 656         u32                     doorbell_qpn;
 657         u32                     sq_signal_bits;
 658         struct hns_roce_wq      sq;
 659
 660         struct hns_roce_mtr     mtr;
 661
 662         u32                     buff_size;
 663         struct mutex            mutex;
 664         u8                      port;
 665         u8                      phy_port;
 666         u8                      sl;
 667         u8                      resp_depth;
 668         u8                      state;
 669         u32                     access_flags;
 670         u32                     atomic_rd_en;
 671         u32                     pkey_index;
 672         u32                     qkey;
 673         void                    (*event)(struct hns_roce_qp *qp,
 674                                          enum hns_roce_event event_type);
 675         unsigned long           qpn;
 676
 677         atomic_t                refcount;
 678         struct completion       free;
 679
 680         struct hns_roce_sge     sge;
 681         u32                     next_sge;
 682         enum ib_mtu             path_mtu;
 683         u32                     max_inline_data;
 684
 685         /* 0: flush needed, 1: unneeded */
 686         unsigned long           flush_flag;
 687         struct hns_roce_work    flush_work;
 688         struct hns_roce_rinl_buf rq_inl_buf;
 689         struct list_head        node;           /* all qps are on a list */
 690         struct list_head        rq_node;        /* all recv qps are on a list */
 691         struct list_head        sq_node;        /* all send qps are on a list */
 692 };
 693
 694 struct hns_roce_ib_iboe {
 695         spinlock_t              lock;
 696         struct net_device      *netdevs[HNS_ROCE_MAX_PORTS];
 697         struct notifier_block   nb;
 698         u8                      phy_port[HNS_ROCE_MAX_PORTS];
 699 };
 700
 701 enum {
 702         HNS_ROCE_EQ_STAT_INVALID  = 0,
 703         HNS_ROCE_EQ_STAT_VALID    = 2,
 704 };
 705
 706 struct hns_roce_ceqe {
 707         __le32  comp;
 708         __le32  rsv[15];
 709 };
 710
 711 struct hns_roce_aeqe {
 712         __le32 asyn;
 713         union {
 714                 struct {
 715                         __le32 num;
 716                         u32 rsv0;
 717                         u32 rsv1;
 718                 } queue_event;
 719
 720                 struct {
 721                         __le64  out_param;
 722                         __le16  token;
 723                         u8      status;
 724                         u8      rsv0;
 725                 } __packed cmd;
 726          } event;
 727         __le32 rsv[12];
 728 };
 729
 730 struct hns_roce_eq {
 731         struct hns_roce_dev             *hr_dev;
 732         void __iomem                    *doorbell;
 733
 734         int                             type_flag; /* Aeq:1 ceq:0 */
 735         int                             eqn;
 736         u32                             entries;
 737         u32                             log_entries;
 738         int                             eqe_size;
 739         int                             irq;
 740         int                             log_page_size;
 741         u32                             cons_index;
 742         struct hns_roce_buf_list        *buf_list;
 743         int                             over_ignore;
 744         int                             coalesce;
 745         int                             arm_st;
 746         int                             hop_num;
 747         struct hns_roce_mtr             mtr;
 748         u16                             eq_max_cnt;
 749         u32                             eq_period;
 750         int                             shift;
 751         int                             event_type;
 752         int                             sub_type;
 753 };
 754
 755 struct hns_roce_eq_table {
 756         struct hns_roce_eq      *eq;
 757         void __iomem            **eqc_base; /* only for hw v1 */
 758 };
 759
 760 struct hns_roce_caps {
 761         u64             fw_ver;
 762         u8              num_ports;
 763         int             gid_table_len[HNS_ROCE_MAX_PORTS];
 764         int             pkey_table_len[HNS_ROCE_MAX_PORTS];
 765         int             local_ca_ack_delay;
 766         int             num_uars;
 767         u32             phy_num_uars;
 768         u32             max_sq_sg;
 769         u32             max_sq_inline;
 770         u32             max_rq_sg;
 771         u32             max_extend_sg;
 772         u32             num_qps;
 773         u32             reserved_qps;
 774         int             num_qpc_timer;
 775         int             num_cqc_timer;
 776         int             num_srqs;
 777         u32             max_wqes;
 778         u32             max_srq_wrs;
 779         u32             max_srq_sges;
 780         u32             max_sq_desc_sz;
 781         u32             max_rq_desc_sz;
 782         u32             max_srq_desc_sz;
 783         int             max_qp_init_rdma;
 784         int             max_qp_dest_rdma;
 785         u32             num_cqs;
 786         u32             max_cqes;
 787         u32             min_cqes;
 788         u32             min_wqes;
 789         u32             reserved_cqs;
 790         int             reserved_srqs;
 791         int             num_aeq_vectors;
 792         int             num_comp_vectors;
 793         int             num_other_vectors;
 794         u32             num_mtpts;
 795         u32             num_mtt_segs;
 796         u32             num_cqe_segs;
 797         u32             num_srqwqe_segs;
 798         u32             num_idx_segs;
 799         int             reserved_mrws;
 800         int             reserved_uars;
 801         int             num_pds;
 802         int             reserved_pds;
 803         u32             mtt_entry_sz;
 804         u32             cqe_sz;
 805         u32             page_size_cap;
 806         u32             reserved_lkey;
 807         int             mtpt_entry_sz;
 808         int             qpc_sz;
 809         int             irrl_entry_sz;
 810         int             trrl_entry_sz;
 811         int             cqc_entry_sz;
 812         int             sccc_sz;
 813         int             qpc_timer_entry_sz;
 814         int             cqc_timer_entry_sz;
 815         int             srqc_entry_sz;
 816         int             idx_entry_sz;
 817         u32             pbl_ba_pg_sz;
 818         u32             pbl_buf_pg_sz;
 819         u32             pbl_hop_num;
 820         int             aeqe_depth;
 821         int             ceqe_depth;
 822         u32             aeqe_size;
 823         u32             ceqe_size;
 824         enum ib_mtu     max_mtu;
 825         u32             qpc_bt_num;
 826         u32             qpc_timer_bt_num;
 827         u32             srqc_bt_num;
 828         u32             cqc_bt_num;
 829         u32             cqc_timer_bt_num;
 830         u32             mpt_bt_num;
 831         u32             sccc_bt_num;
 832         u32             gmv_bt_num;
 833         u32             qpc_ba_pg_sz;
 834         u32             qpc_buf_pg_sz;
 835         u32             qpc_hop_num;
 836         u32             srqc_ba_pg_sz;
 837         u32             srqc_buf_pg_sz;
 838         u32             srqc_hop_num;
 839         u32             cqc_ba_pg_sz;
 840         u32             cqc_buf_pg_sz;
 841         u32             cqc_hop_num;
 842         u32             mpt_ba_pg_sz;
 843         u32             mpt_buf_pg_sz;
 844         u32             mpt_hop_num;
 845         u32             mtt_ba_pg_sz;
 846         u32             mtt_buf_pg_sz;
 847         u32             mtt_hop_num;
 848         u32             wqe_sq_hop_num;
 849         u32             wqe_sge_hop_num;
 850         u32             wqe_rq_hop_num;
 851         u32             sccc_ba_pg_sz;
 852         u32             sccc_buf_pg_sz;
 853         u32             sccc_hop_num;
 854         u32             qpc_timer_ba_pg_sz;
 855         u32             qpc_timer_buf_pg_sz;
 856         u32             qpc_timer_hop_num;
 857         u32             cqc_timer_ba_pg_sz;
 858         u32             cqc_timer_buf_pg_sz;
 859         u32             cqc_timer_hop_num;
 860         u32             cqe_ba_pg_sz;   /* page_size = 4K*(2^cqe_ba_pg_sz) */
 861         u32             cqe_buf_pg_sz;
 862         u32             cqe_hop_num;
 863         u32             srqwqe_ba_pg_sz;
 864         u32             srqwqe_buf_pg_sz;
 865         u32             srqwqe_hop_num;
 866         u32             idx_ba_pg_sz;
 867         u32             idx_buf_pg_sz;
 868         u32             idx_hop_num;
 869         u32             eqe_ba_pg_sz;
 870         u32             eqe_buf_pg_sz;
 871         u32             eqe_hop_num;
 872         u32             gmv_entry_num;
 873         u32             gmv_entry_sz;
 874         u32             gmv_ba_pg_sz;
 875         u32             gmv_buf_pg_sz;
 876         u32             gmv_hop_num;
 877         u32             sl_num;
 878         u32             tsq_buf_pg_sz;
 879         u32             tpq_buf_pg_sz;
 880         u32             chunk_sz;       /* chunk size in non multihop mode */
 881         u64             flags;
 882         u16             default_ceq_max_cnt;
 883         u16             default_ceq_period;
 884         u16             default_aeq_max_cnt;
 885         u16             default_aeq_period;
 886         u16             default_aeq_arm_st;
 887         u16             default_ceq_arm_st;
 888 };
 889
 890 struct hns_roce_dfx_hw {
 891         int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
 892                               int *buffer);
 893 };
 894
 895 enum hns_roce_device_state {
 896         HNS_ROCE_DEVICE_STATE_INITED,
 897         HNS_ROCE_DEVICE_STATE_RST_DOWN,
 898         HNS_ROCE_DEVICE_STATE_UNINIT,
 899 };
 900
 901 struct hns_roce_hw {
 902         int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
 903         int (*cmq_init)(struct hns_roce_dev *hr_dev);
 904         void (*cmq_exit)(struct hns_roce_dev *hr_dev);
 905         int (*hw_profile)(struct hns_roce_dev *hr_dev);
 906         int (*hw_init)(struct hns_roce_dev *hr_dev);
 907         void (*hw_exit)(struct hns_roce_dev *hr_dev);
 908         int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
 909                          u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
 910                          u16 token, int event);
 911         int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned int timeout);
 912         int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev);
 913         int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
 914                        const union ib_gid *gid, const struct ib_gid_attr *attr);
 915         int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
 916         void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
 917                         enum ib_mtu mtu);
 918         int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
 919                           struct hns_roce_mr *mr, unsigned long mtpt_idx);
 920         int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
 921                                 struct hns_roce_mr *mr, int flags,
 922                                 void *mb_buf);
 923         int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
 924                                struct hns_roce_mr *mr);
 925         int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
 926         void (*write_cqc)(struct hns_roce_dev *hr_dev,
 927                           struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
 928                           dma_addr_t dma_handle);
 929         int (*set_hem)(struct hns_roce_dev *hr_dev,
 930                        struct hns_roce_hem_table *table, int obj, int step_idx);
 931         int (*clear_hem)(struct hns_roce_dev *hr_dev,
 932                          struct hns_roce_hem_table *table, int obj,
 933                          int step_idx);
 934         int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
 935                         int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
 936         int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
 937                          int attr_mask, enum ib_qp_state cur_state,
 938                          enum ib_qp_state new_state);
 939         int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata);
 940         int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
 941                          struct hns_roce_qp *hr_qp);
 942         int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 943                          const struct ib_send_wr **bad_wr);
 944         int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr,
 945                          const struct ib_recv_wr **bad_recv_wr);
 946         int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 947         int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 948         int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
 949                         struct ib_udata *udata);
 950         int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
 951         int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
 952         int (*init_eq)(struct hns_roce_dev *hr_dev);
 953         void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
 954         void (*write_srqc)(struct hns_roce_dev *hr_dev,
 955                            struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn,
 956                            void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx,
 957                            dma_addr_t dma_handle_wqe,
 958                            dma_addr_t dma_handle_idx);
 959         int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
 960                        enum ib_srq_attr_mask srq_attr_mask,
 961                        struct ib_udata *udata);
 962         int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr);
 963         int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
 964                              const struct ib_recv_wr **bad_wr);
 965         const struct ib_device_ops *hns_roce_dev_ops;
 966         const struct ib_device_ops *hns_roce_dev_srq_ops;
 967 };
 968
 969 struct hns_roce_dev {
 970         struct ib_device        ib_dev;
 971         struct platform_device  *pdev;
 972         struct pci_dev          *pci_dev;
 973         struct device           *dev;
 974         struct hns_roce_uar     priv_uar;
 975         const char              *irq_names[HNS_ROCE_MAX_IRQ_NUM];
 976         spinlock_t              sm_lock;
 977         spinlock_t              bt_cmd_lock;
 978         bool                    active;
 979         bool                    is_reset;
 980         bool                    dis_db;
 981         unsigned long           reset_cnt;
 982         struct hns_roce_ib_iboe iboe;
 983         enum hns_roce_device_state state;
 984         struct list_head        qp_list; /* list of all qps on this dev */
 985         spinlock_t              qp_list_lock; /* protect qp_list */
 986
 987         struct list_head        pgdir_list;
 988         struct mutex            pgdir_mutex;
 989         int                     irq[HNS_ROCE_MAX_IRQ_NUM];
 990         u8 __iomem              *reg_base;
 991         struct hns_roce_caps    caps;
 992         struct xarray           qp_table_xa;
 993
 994         unsigned char   dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
 995         u64                     sys_image_guid;
 996         u32                     vendor_id;
 997         u32                     vendor_part_id;
 998         u32                     hw_rev;
 999         void __iomem            *priv_addr;
1000
1001         struct hns_roce_cmdq    cmd;
1002         struct hns_roce_bitmap    pd_bitmap;
1003         struct hns_roce_uar_table uar_table;
1004         struct hns_roce_mr_table  mr_table;
1005         struct hns_roce_cq_table  cq_table;
1006         struct hns_roce_srq_table srq_table;
1007         struct hns_roce_qp_table  qp_table;
1008         struct hns_roce_eq_table  eq_table;
1009         struct hns_roce_hem_table  qpc_timer_table;
1010         struct hns_roce_hem_table  cqc_timer_table;
1011         /* GMV is the memory area that the driver allocates for the hardware
1012          * to store SGID, SMAC and VLAN information.
1013          */
1014         struct hns_roce_hem_table  gmv_table;
1015
1016         int                     cmd_mod;
1017         int                     loop_idc;
1018         u32                     sdb_offset;
1019         u32                     odb_offset;
1020         dma_addr_t              tptr_dma_addr;  /* only for hw v1 */
1021         u32                     tptr_size;      /* only for hw v1 */
1022         const struct hns_roce_hw *hw;
1023         void                    *priv;
1024         struct workqueue_struct *irq_workq;
1025         const struct hns_roce_dfx_hw *dfx;
1026 };
1027
1028 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
1029 {
1030         return container_of(ib_dev, struct hns_roce_dev, ib_dev);
1031 }
1032
1033 static inline struct hns_roce_ucontext
1034                         *to_hr_ucontext(struct ib_ucontext *ibucontext)
1035 {
1036         return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1037 }
1038
1039 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1040 {
1041         return container_of(ibpd, struct hns_roce_pd, ibpd);
1042 }
1043
1044 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1045 {
1046         return container_of(ibah, struct hns_roce_ah, ibah);
1047 }
1048
1049 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1050 {
1051         return container_of(ibmr, struct hns_roce_mr, ibmr);
1052 }
1053
1054 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1055 {
1056         return container_of(ibmw, struct hns_roce_mw, ibmw);
1057 }
1058
1059 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1060 {
1061         return container_of(ibqp, struct hns_roce_qp, ibqp);
1062 }
1063
1064 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1065 {
1066         return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1067 }
1068
1069 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1070 {
1071         return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1072 }
1073
1074 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1075 {
1076         __raw_writeq(*(u64 *) val, dest);
1077 }
1078
1079 static inline struct hns_roce_qp
1080         *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1081 {
1082         return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1));
1083 }
1084
1085 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
1086                                         unsigned int offset)
1087 {
1088         return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1089                         (offset & ((1 << buf->trunk_shift) - 1));
1090 }
1091
1092 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
1093 {
1094         unsigned int offset = idx << buf->page_shift;
1095
1096         return buf->trunk_list[offset >> buf->trunk_shift].map +
1097                         (offset & ((1 << buf->trunk_shift) - 1));
1098 }
1099
1100 #define hr_hw_page_align(x)             ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1101
1102 static inline u64 to_hr_hw_page_addr(u64 addr)
1103 {
1104         return addr >> HNS_HW_PAGE_SHIFT;
1105 }
1106
1107 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1108 {
1109         return page_shift - HNS_HW_PAGE_SHIFT;
1110 }
1111
1112 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1113 {
1114         if (count > 0)
1115                 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1116
1117         return 0;
1118 }
1119
1120 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1121 {
1122         return hr_hw_page_align(count << buf_shift);
1123 }
1124
1125 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1126 {
1127         return hr_hw_page_align(count << buf_shift) >> buf_shift;
1128 }
1129
1130 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1131 {
1132         if (!count)
1133                 return 0;
1134
1135         return ilog2(to_hr_hem_entries_count(count, buf_shift));
1136 }
1137
1138 #define DSCP_SHIFT 2
1139
1140 static inline u8 get_tclass(const struct ib_global_route *grh)
1141 {
1142         return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
1143                grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
1144 }
1145
1146 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
1147 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1148 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1149 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
1150
1151 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1152 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1153 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1154                         u64 out_param);
1155 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1156 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1157
1158 /* hns roce hw need current block and next block addr from mtt */
1159 #define MTT_MIN_COUNT    2
1160 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1161                       int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1162 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1163                         struct hns_roce_buf_attr *buf_attr,
1164                         unsigned int page_shift, struct ib_udata *udata,
1165                         unsigned long user_addr);
1166 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1167                           struct hns_roce_mtr *mtr);
1168 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1169                      dma_addr_t *pages, unsigned int page_cnt);
1170
1171 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1172 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1173 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1174 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1175 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1176
1177 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
1178 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
1179 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1180 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1181 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1182 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev);
1183
1184 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
1185 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
1186                          int rr);
1187 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
1188                          u32 reserved_bot, u32 resetrved_top);
1189 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
1190 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1191 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
1192                                 int align, unsigned long *obj);
1193 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
1194                                 unsigned long obj, int cnt,
1195                                 int rr);
1196
1197 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1198                        struct ib_udata *udata);
1199 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1200 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1201 {
1202         return 0;
1203 }
1204
1205 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1206 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1207
1208 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1209 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1210                                    u64 virt_addr, int access_flags,
1211                                    struct ib_udata *udata);
1212 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
1213                                      u64 length, u64 virt_addr,
1214                                      int mr_access_flags, struct ib_pd *pd,
1215                                      struct ib_udata *udata);
1216 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1217                                 u32 max_num_sg);
1218 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1219                        unsigned int *sg_offset);
1220 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1221 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
1222                             struct hns_roce_cmd_mailbox *mailbox,
1223                             unsigned long mpt_index);
1224 unsigned long key_to_hw_index(u32 key);
1225
1226 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1227 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1228
1229 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1230 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1231                                         u32 page_shift, u32 flags);
1232
1233 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1234                            int buf_cnt, int start, struct hns_roce_buf *buf);
1235 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1236                            int buf_cnt, int start, struct ib_umem *umem,
1237                            unsigned int page_shift);
1238
1239 int hns_roce_create_srq(struct ib_srq *srq,
1240                         struct ib_srq_init_attr *srq_init_attr,
1241                         struct ib_udata *udata);
1242 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1243                         enum ib_srq_attr_mask srq_attr_mask,
1244                         struct ib_udata *udata);
1245 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1246
1247 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
1248                                  struct ib_qp_init_attr *init_attr,
1249                                  struct ib_udata *udata);
1250 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1251                        int attr_mask, struct ib_udata *udata);
1252 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1253 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1254 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1255 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
1256 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1257                           struct ib_cq *ib_cq);
1258 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1259 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1260                        struct hns_roce_cq *recv_cq);
1261 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1262                          struct hns_roce_cq *recv_cq);
1263 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1264 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1265                          struct ib_udata *udata);
1266 __be32 send_ieth(const struct ib_send_wr *wr);
1267 int to_hr_qp_type(int qp_type);
1268
1269 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1270                        struct ib_udata *udata);
1271
1272 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1273 int hns_roce_db_map_user(struct hns_roce_ucontext *context,
1274                          struct ib_udata *udata, unsigned long virt,
1275                          struct hns_roce_db *db);
1276 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1277                             struct hns_roce_db *db);
1278 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1279                       int order);
1280 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1281
1282 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1283 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1284 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1285 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1286 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
1287 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1288 int hns_roce_init(struct hns_roce_dev *hr_dev);
1289 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1290 int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
1291                                struct ib_cq *ib_cq);
1292 #endif /* _HNS_ROCE_DEVICE_H */