drivers/infiniband/hw/hns/hns_roce_device.h

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _HNS_ROCE_DEVICE_H
  34 #define _HNS_ROCE_DEVICE_H
  35
  36 #include <rdma/ib_verbs.h>
  37
  38 #define DRV_NAME "hns_roce"
  39
  40 #define HNS_ROCE_HW_VER1        ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
  41
  42 #define MAC_ADDR_OCTET_NUM                      6
  43 #define HNS_ROCE_MAX_MSG_LEN                    0x80000000
  44
  45 #define HNS_ROCE_ALOGN_UP(a, b) ((((a) + (b) - 1) / (b)) * (b))
  46
  47 #define HNS_ROCE_IB_MIN_SQ_STRIDE               6
  48
  49 #define HNS_ROCE_BA_SIZE                        (32 * 4096)
  50
  51 /* Hardware specification only for v1 engine */
  52 #define HNS_ROCE_MIN_CQE_NUM                    0x40
  53 #define HNS_ROCE_MIN_WQE_NUM                    0x20
  54
  55 /* Hardware specification only for v1 engine */
  56 #define HNS_ROCE_MAX_INNER_MTPT_NUM             0x7
  57 #define HNS_ROCE_MAX_MTPT_PBL_NUM               0x100000
  58
  59 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS        20
  60 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT   \
  61         (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
  62 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT             0x2
  63 #define HNS_ROCE_MIN_CQE_CNT                    16
  64
  65 #define HNS_ROCE_MAX_IRQ_NUM                    128
  66
  67 #define EQ_ENABLE                               1
  68 #define EQ_DISABLE                              0
  69
  70 #define HNS_ROCE_CEQ                            0
  71 #define HNS_ROCE_AEQ                            1
  72
  73 #define HNS_ROCE_CEQ_ENTRY_SIZE                 0x4
  74 #define HNS_ROCE_AEQ_ENTRY_SIZE                 0x10
  75
  76 /* 4G/4K = 1M */
  77 #define HNS_ROCE_SL_SHIFT                       28
  78 #define HNS_ROCE_TCLASS_SHIFT                   20
  79 #define HNS_ROCE_FLOW_LABEL_MASK                0xfffff
  80
  81 #define HNS_ROCE_MAX_PORTS                      6
  82 #define HNS_ROCE_MAX_GID_NUM                    16
  83 #define HNS_ROCE_GID_SIZE                       16
  84
  85 #define HNS_ROCE_HOP_NUM_0                      0xff
  86
  87 #define BITMAP_NO_RR                            0
  88 #define BITMAP_RR                               1
  89
  90 #define MR_TYPE_MR                              0x00
  91 #define MR_TYPE_FRMR                            0x01
  92 #define MR_TYPE_DMA                             0x03
  93
  94 #define HNS_ROCE_FRMR_MAX_PA                    512
  95
  96 #define PKEY_ID                                 0xffff
  97 #define GUID_LEN                                8
  98 #define NODE_DESC_SIZE                          64
  99 #define DB_REG_OFFSET                           0x1000
 100
 101 #define SERV_TYPE_RC                            0
 102 #define SERV_TYPE_RD                            1
 103 #define SERV_TYPE_UC                            2
 104 #define SERV_TYPE_UD                            3
 105
 106 /* Configure to HW for PAGE_SIZE larger than 4KB */
 107 #define PG_SHIFT_OFFSET                         (PAGE_SHIFT - 12)
 108
 109 #define PAGES_SHIFT_8                           8
 110 #define PAGES_SHIFT_16                          16
 111 #define PAGES_SHIFT_24                          24
 112 #define PAGES_SHIFT_32                          32
 113
 114 #define HNS_ROCE_IDX_QUE_ENTRY_SZ               4
 115 #define SRQ_DB_REG                              0x230
 116
 117 enum {
 118         HNS_ROCE_SUPPORT_RQ_RECORD_DB = 1 << 0,
 119         HNS_ROCE_SUPPORT_SQ_RECORD_DB = 1 << 1,
 120 };
 121
 122 enum {
 123         HNS_ROCE_SUPPORT_CQ_RECORD_DB = 1 << 0,
 124 };
 125
 126 enum hns_roce_qp_state {
 127         HNS_ROCE_QP_STATE_RST,
 128         HNS_ROCE_QP_STATE_INIT,
 129         HNS_ROCE_QP_STATE_RTR,
 130         HNS_ROCE_QP_STATE_RTS,
 131         HNS_ROCE_QP_STATE_SQD,
 132         HNS_ROCE_QP_STATE_ERR,
 133         HNS_ROCE_QP_NUM_STATE,
 134 };
 135
 136 enum hns_roce_event {
 137         HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
 138         HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
 139         HNS_ROCE_EVENT_TYPE_COMM_EST                  = 0x03,
 140         HNS_ROCE_EVENT_TYPE_SQ_DRAINED                = 0x04,
 141         HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR            = 0x05,
 142         HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR    = 0x06,
 143         HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR     = 0x07,
 144         HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH           = 0x08,
 145         HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH        = 0x09,
 146         HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR           = 0x0a,
 147         HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR           = 0x0b,
 148         HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW               = 0x0c,
 149         HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID             = 0x0d,
 150         HNS_ROCE_EVENT_TYPE_PORT_CHANGE               = 0x0f,
 151         /* 0x10 and 0x11 is unused in currently application case */
 152         HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,
 153         HNS_ROCE_EVENT_TYPE_MB                        = 0x13,
 154         HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW              = 0x14,
 155         HNS_ROCE_EVENT_TYPE_FLR                       = 0x15,
 156 };
 157
 158 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
 159 enum {
 160         HNS_ROCE_LWQCE_QPC_ERROR                = 1,
 161         HNS_ROCE_LWQCE_MTU_ERROR                = 2,
 162         HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR        = 3,
 163         HNS_ROCE_LWQCE_WQE_ADDR_ERROR           = 4,
 164         HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR       = 5,
 165         HNS_ROCE_LWQCE_SL_ERROR                 = 6,
 166         HNS_ROCE_LWQCE_PORT_ERROR               = 7,
 167 };
 168
 169 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
 170 enum {
 171         HNS_ROCE_LAVWQE_R_KEY_VIOLATION         = 1,
 172         HNS_ROCE_LAVWQE_LENGTH_ERROR            = 2,
 173         HNS_ROCE_LAVWQE_VA_ERROR                = 3,
 174         HNS_ROCE_LAVWQE_PD_ERROR                = 4,
 175         HNS_ROCE_LAVWQE_RW_ACC_ERROR            = 5,
 176         HNS_ROCE_LAVWQE_KEY_STATE_ERROR         = 6,
 177         HNS_ROCE_LAVWQE_MR_OPERATION_ERROR      = 7,
 178 };
 179
 180 /* DOORBELL overflow subtype */
 181 enum {
 182         HNS_ROCE_DB_SUBTYPE_SDB_OVF             = 1,
 183         HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF         = 2,
 184         HNS_ROCE_DB_SUBTYPE_ODB_OVF             = 3,
 185         HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF         = 4,
 186         HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP         = 5,
 187         HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP         = 6,
 188 };
 189
 190 enum {
 191         /* RQ&SRQ related operations */
 192         HNS_ROCE_OPCODE_SEND_DATA_RECEIVE       = 0x06,
 193         HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE   = 0x07,
 194 };
 195
 196 enum {
 197         HNS_ROCE_CAP_FLAG_REREG_MR              = BIT(0),
 198         HNS_ROCE_CAP_FLAG_ROCE_V1_V2            = BIT(1),
 199         HNS_ROCE_CAP_FLAG_RQ_INLINE             = BIT(2),
 200         HNS_ROCE_CAP_FLAG_RECORD_DB             = BIT(3),
 201         HNS_ROCE_CAP_FLAG_SQ_RECORD_DB          = BIT(4),
 202         HNS_ROCE_CAP_FLAG_SRQ                   = BIT(5),
 203         HNS_ROCE_CAP_FLAG_MW                    = BIT(7),
 204         HNS_ROCE_CAP_FLAG_FRMR                  = BIT(8),
 205         HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL          = BIT(9),
 206         HNS_ROCE_CAP_FLAG_ATOMIC                = BIT(10),
 207 };
 208
 209 enum hns_roce_mtt_type {
 210         MTT_TYPE_WQE,
 211         MTT_TYPE_CQE,
 212         MTT_TYPE_SRQWQE,
 213         MTT_TYPE_IDX
 214 };
 215
 216 enum {
 217         HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
 218 };
 219
 220 enum hns_roce_reset_stage {
 221         HNS_ROCE_STATE_NON_RST,
 222         HNS_ROCE_STATE_RST_BEF_DOWN,
 223         HNS_ROCE_STATE_RST_DOWN,
 224         HNS_ROCE_STATE_RST_UNINIT,
 225         HNS_ROCE_STATE_RST_INIT,
 226         HNS_ROCE_STATE_RST_INITED,
 227 };
 228
 229 enum hns_roce_instance_state {
 230         HNS_ROCE_STATE_NON_INIT,
 231         HNS_ROCE_STATE_INIT,
 232         HNS_ROCE_STATE_INITED,
 233         HNS_ROCE_STATE_UNINIT,
 234 };
 235
 236 enum {
 237         HNS_ROCE_RST_DIRECT_RETURN              = 0,
 238 };
 239
 240 enum {
 241         CMD_RST_PRC_OTHERS,
 242         CMD_RST_PRC_SUCCESS,
 243         CMD_RST_PRC_EBUSY,
 244 };
 245
 246 #define HNS_ROCE_CMD_SUCCESS                    1
 247
 248 #define HNS_ROCE_PORT_DOWN                      0
 249 #define HNS_ROCE_PORT_UP                        1
 250
 251 #define HNS_ROCE_MTT_ENTRY_PER_SEG              8
 252
 253 #define PAGE_ADDR_SHIFT                         12
 254
 255 struct hns_roce_uar {
 256         u64             pfn;
 257         unsigned long   index;
 258         unsigned long   logic_idx;
 259 };
 260
 261 struct hns_roce_ucontext {
 262         struct ib_ucontext      ibucontext;
 263         struct hns_roce_uar     uar;
 264         struct list_head        page_list;
 265         struct mutex            page_mutex;
 266 };
 267
 268 struct hns_roce_pd {
 269         struct ib_pd            ibpd;
 270         unsigned long           pdn;
 271 };
 272
 273 struct hns_roce_bitmap {
 274         /* Bitmap Traversal last a bit which is 1 */
 275         unsigned long           last;
 276         unsigned long           top;
 277         unsigned long           max;
 278         unsigned long           reserved_top;
 279         unsigned long           mask;
 280         spinlock_t              lock;
 281         unsigned long           *table;
 282 };
 283
 284 /* Order bitmap length -- bit num compute formula: 1 << (max_order - order) */
 285 /* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */
 286 /* Every bit repesent to a partner free/used status in bitmap */
 287 /*
 288  * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1
 289  * Bit = 1 represent to idle and available; bit = 0: not available
 290  */
 291 struct hns_roce_buddy {
 292         /* Members point to every order level bitmap */
 293         unsigned long **bits;
 294         /* Represent to avail bits of the order level bitmap */
 295         u32            *num_free;
 296         int             max_order;
 297         spinlock_t      lock;
 298 };
 299
 300 /* For Hardware Entry Memory */
 301 struct hns_roce_hem_table {
 302         /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
 303         u32             type;
 304         /* HEM array elment num */
 305         unsigned long   num_hem;
 306         /* HEM entry record obj total num */
 307         unsigned long   num_obj;
 308         /*Single obj size */
 309         unsigned long   obj_size;
 310         unsigned long   table_chunk_size;
 311         int             lowmem;
 312         struct mutex    mutex;
 313         struct hns_roce_hem **hem;
 314         u64             **bt_l1;
 315         dma_addr_t      *bt_l1_dma_addr;
 316         u64             **bt_l0;
 317         dma_addr_t      *bt_l0_dma_addr;
 318 };
 319
 320 struct hns_roce_mtt {
 321         unsigned long           first_seg;
 322         int                     order;
 323         int                     page_shift;
 324         enum hns_roce_mtt_type  mtt_type;
 325 };
 326
 327 struct hns_roce_mw {
 328         struct ib_mw            ibmw;
 329         u32                     pdn;
 330         u32                     rkey;
 331         int                     enabled; /* MW's active status */
 332         u32                     pbl_hop_num;
 333         u32                     pbl_ba_pg_sz;
 334         u32                     pbl_buf_pg_sz;
 335 };
 336
 337 /* Only support 4K page size for mr register */
 338 #define MR_SIZE_4K 0
 339
 340 struct hns_roce_mr {
 341         struct ib_mr            ibmr;
 342         struct ib_umem          *umem;
 343         u64                     iova; /* MR's virtual orignal addr */
 344         u64                     size; /* Address range of MR */
 345         u32                     key; /* Key of MR */
 346         u32                     pd;   /* PD num of MR */
 347         u32                     access;/* Access permission of MR */
 348         u32                     npages;
 349         int                     enabled; /* MR's active status */
 350         int                     type;   /* MR's register type */
 351         u64                     *pbl_buf;/* MR's PBL space */
 352         dma_addr_t              pbl_dma_addr;   /* MR's PBL space PA */
 353         u32                     pbl_size;/* PA number in the PBL */
 354         u64                     pbl_ba;/* page table address */
 355         u32                     l0_chunk_last_num;/* L0 last number */
 356         u32                     l1_chunk_last_num;/* L1 last number */
 357         u64                     **pbl_bt_l2;/* PBL BT L2 */
 358         u64                     **pbl_bt_l1;/* PBL BT L1 */
 359         u64                     *pbl_bt_l0;/* PBL BT L0 */
 360         dma_addr_t              *pbl_l2_dma_addr;/* PBL BT L2 dma addr */
 361         dma_addr_t              *pbl_l1_dma_addr;/* PBL BT L1 dma addr */
 362         dma_addr_t              pbl_l0_dma_addr;/* PBL BT L0 dma addr */
 363         u32                     pbl_ba_pg_sz;/* BT chunk page size */
 364         u32                     pbl_buf_pg_sz;/* buf chunk page size */
 365         u32                     pbl_hop_num;/* multi-hop number */
 366 };
 367
 368 struct hns_roce_mr_table {
 369         struct hns_roce_bitmap          mtpt_bitmap;
 370         struct hns_roce_buddy           mtt_buddy;
 371         struct hns_roce_hem_table       mtt_table;
 372         struct hns_roce_hem_table       mtpt_table;
 373         struct hns_roce_buddy           mtt_cqe_buddy;
 374         struct hns_roce_hem_table       mtt_cqe_table;
 375         struct hns_roce_buddy           mtt_srqwqe_buddy;
 376         struct hns_roce_hem_table       mtt_srqwqe_table;
 377         struct hns_roce_buddy           mtt_idx_buddy;
 378         struct hns_roce_hem_table       mtt_idx_table;
 379 };
 380
 381 struct hns_roce_wq {
 382         u64             *wrid;     /* Work request ID */
 383         spinlock_t      lock;
 384         int             wqe_cnt;  /* WQE num */
 385         u32             max_post;
 386         int             max_gs;
 387         int             offset;
 388         int             wqe_shift;/* WQE size */
 389         u32             head;
 390         u32             tail;
 391         void __iomem    *db_reg_l;
 392 };
 393
 394 struct hns_roce_sge {
 395         int             sge_cnt;  /* SGE num */
 396         int             offset;
 397         int             sge_shift;/* SGE size */
 398 };
 399
 400 struct hns_roce_buf_list {
 401         void            *buf;
 402         dma_addr_t      map;
 403 };
 404
 405 struct hns_roce_buf {
 406         struct hns_roce_buf_list        direct;
 407         struct hns_roce_buf_list        *page_list;
 408         int                             nbufs;
 409         u32                             npages;
 410         int                             page_shift;
 411 };
 412
 413 struct hns_roce_db_pgdir {
 414         struct list_head        list;
 415         DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
 416         DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / 2);
 417         unsigned long           *bits[2];
 418         u32                     *page;
 419         dma_addr_t              db_dma;
 420 };
 421
 422 struct hns_roce_user_db_page {
 423         struct list_head        list;
 424         struct ib_umem          *umem;
 425         unsigned long           user_virt;
 426         refcount_t              refcount;
 427 };
 428
 429 struct hns_roce_db {
 430         u32             *db_record;
 431         union {
 432                 struct hns_roce_db_pgdir *pgdir;
 433                 struct hns_roce_user_db_page *user_page;
 434         } u;
 435         dma_addr_t      dma;
 436         void            *virt_addr;
 437         int             index;
 438         int             order;
 439 };
 440
 441 struct hns_roce_cq_buf {
 442         struct hns_roce_buf hr_buf;
 443         struct hns_roce_mtt hr_mtt;
 444 };
 445
 446 struct hns_roce_cq {
 447         struct ib_cq                    ib_cq;
 448         struct hns_roce_cq_buf          hr_buf;
 449         struct hns_roce_db              db;
 450         u8                              db_en;
 451         spinlock_t                      lock;
 452         struct ib_umem                  *umem;
 453         void (*comp)(struct hns_roce_cq *cq);
 454         void (*event)(struct hns_roce_cq *cq, enum hns_roce_event event_type);
 455
 456         struct hns_roce_uar             *uar;
 457         u32                             cq_depth;
 458         u32                             cons_index;
 459         u32                             *set_ci_db;
 460         void __iomem                    *cq_db_l;
 461         u16                             *tptr_addr;
 462         int                             arm_sn;
 463         unsigned long                   cqn;
 464         u32                             vector;
 465         atomic_t                        refcount;
 466         struct completion               free;
 467 };
 468
 469 struct hns_roce_idx_que {
 470         struct hns_roce_buf             idx_buf;
 471         int                             entry_sz;
 472         u32                             buf_size;
 473         struct ib_umem                  *umem;
 474         struct hns_roce_mtt             mtt;
 475         u64                             *bitmap;
 476 };
 477
 478 struct hns_roce_srq {
 479         struct ib_srq           ibsrq;
 480         void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
 481         unsigned long           srqn;
 482         int                     max;
 483         int                     max_gs;
 484         int                     wqe_shift;
 485         void __iomem            *db_reg_l;
 486
 487         atomic_t                refcount;
 488         struct completion       free;
 489
 490         struct hns_roce_buf     buf;
 491         u64                    *wrid;
 492         struct ib_umem         *umem;
 493         struct hns_roce_mtt     mtt;
 494         struct hns_roce_idx_que idx_que;
 495         spinlock_t              lock;
 496         int                     head;
 497         int                     tail;
 498         u16                     wqe_ctr;
 499         struct mutex            mutex;
 500 };
 501
 502 struct hns_roce_uar_table {
 503         struct hns_roce_bitmap bitmap;
 504 };
 505
 506 struct hns_roce_qp_table {
 507         struct hns_roce_bitmap          bitmap;
 508         struct hns_roce_hem_table       qp_table;
 509         struct hns_roce_hem_table       irrl_table;
 510         struct hns_roce_hem_table       trrl_table;
 511         struct hns_roce_hem_table       sccc_table;
 512         struct mutex                    scc_mutex;
 513 };
 514
 515 struct hns_roce_cq_table {
 516         struct hns_roce_bitmap          bitmap;
 517         struct xarray                   array;
 518         struct hns_roce_hem_table       table;
 519 };
 520
 521 struct hns_roce_srq_table {
 522         struct hns_roce_bitmap          bitmap;
 523         struct xarray                   xa;
 524         struct hns_roce_hem_table       table;
 525 };
 526
 527 struct hns_roce_raq_table {
 528         struct hns_roce_buf_list        *e_raq_buf;
 529 };
 530
 531 struct hns_roce_av {
 532         __le32      port_pd;
 533         u8          gid_index;
 534         u8          stat_rate;
 535         u8          hop_limit;
 536         __le32      sl_tclass_flowlabel;
 537         u8          dgid[HNS_ROCE_GID_SIZE];
 538         u8          mac[6];
 539         __le16      vlan;
 540         bool        vlan_en;
 541 };
 542
 543 struct hns_roce_ah {
 544         struct ib_ah            ibah;
 545         struct hns_roce_av      av;
 546 };
 547
 548 struct hns_roce_cmd_context {
 549         struct completion       done;
 550         int                     result;
 551         int                     next;
 552         u64                     out_param;
 553         u16                     token;
 554 };
 555
 556 struct hns_roce_cmdq {
 557         struct dma_pool         *pool;
 558         struct mutex            hcr_mutex;
 559         struct semaphore        poll_sem;
 560         /*
 561          * Event mode: cmd register mutex protection,
 562          * ensure to not exceed max_cmds and user use limit region
 563          */
 564         struct semaphore        event_sem;
 565         int                     max_cmds;
 566         spinlock_t              context_lock;
 567         int                     free_head;
 568         struct hns_roce_cmd_context *context;
 569         /*
 570          * Result of get integer part
 571          * which max_comds compute according a power of 2
 572          */
 573         u16                     token_mask;
 574         /*
 575          * Process whether use event mode, init default non-zero
 576          * After the event queue of cmd event ready,
 577          * can switch into event mode
 578          * close device, switch into poll mode(non event mode)
 579          */
 580         u8                      use_events;
 581         u8                      toggle;
 582 };
 583
 584 struct hns_roce_cmd_mailbox {
 585         void                   *buf;
 586         dma_addr_t              dma;
 587 };
 588
 589 struct hns_roce_dev;
 590
 591 struct hns_roce_rinl_sge {
 592         void                    *addr;
 593         u32                     len;
 594 };
 595
 596 struct hns_roce_rinl_wqe {
 597         struct hns_roce_rinl_sge *sg_list;
 598         u32                      sge_cnt;
 599 };
 600
 601 struct hns_roce_rinl_buf {
 602         struct hns_roce_rinl_wqe *wqe_list;
 603         u32                      wqe_cnt;
 604 };
 605
 606 struct hns_roce_qp {
 607         struct ib_qp            ibqp;
 608         struct hns_roce_buf     hr_buf;
 609         struct hns_roce_wq      rq;
 610         struct hns_roce_db      rdb;
 611         struct hns_roce_db      sdb;
 612         u8                      rdb_en;
 613         u8                      sdb_en;
 614         u32                     doorbell_qpn;
 615         __le32                  sq_signal_bits;
 616         u32                     sq_next_wqe;
 617         int                     sq_max_wqes_per_wr;
 618         int                     sq_spare_wqes;
 619         struct hns_roce_wq      sq;
 620
 621         struct ib_umem          *umem;
 622         struct hns_roce_mtt     mtt;
 623         u32                     buff_size;
 624         struct mutex            mutex;
 625         u8                      port;
 626         u8                      phy_port;
 627         u8                      sl;
 628         u8                      resp_depth;
 629         u8                      state;
 630         u32                     access_flags;
 631         u32                     atomic_rd_en;
 632         u32                     pkey_index;
 633         u32                     qkey;
 634         void                    (*event)(struct hns_roce_qp *qp,
 635                                          enum hns_roce_event event_type);
 636         unsigned long           qpn;
 637
 638         atomic_t                refcount;
 639         struct completion       free;
 640
 641         struct hns_roce_sge     sge;
 642         u32                     next_sge;
 643
 644         struct hns_roce_rinl_buf rq_inl_buf;
 645 };
 646
 647 struct hns_roce_sqp {
 648         struct hns_roce_qp      hr_qp;
 649 };
 650
 651 struct hns_roce_ib_iboe {
 652         spinlock_t              lock;
 653         struct net_device      *netdevs[HNS_ROCE_MAX_PORTS];
 654         struct notifier_block   nb;
 655         u8                      phy_port[HNS_ROCE_MAX_PORTS];
 656 };
 657
 658 enum {
 659         HNS_ROCE_EQ_STAT_INVALID  = 0,
 660         HNS_ROCE_EQ_STAT_VALID    = 2,
 661 };
 662
 663 struct hns_roce_ceqe {
 664         u32                     comp;
 665 };
 666
 667 struct hns_roce_aeqe {
 668         __le32 asyn;
 669         union {
 670                 struct {
 671                         __le32 qp;
 672                         u32 rsv0;
 673                         u32 rsv1;
 674                 } qp_event;
 675
 676                 struct {
 677                         __le32 srq;
 678                         u32 rsv0;
 679                         u32 rsv1;
 680                 } srq_event;
 681
 682                 struct {
 683                         __le32 cq;
 684                         u32 rsv0;
 685                         u32 rsv1;
 686                 } cq_event;
 687
 688                 struct {
 689                         __le32 ceqe;
 690                         u32 rsv0;
 691                         u32 rsv1;
 692                 } ce_event;
 693
 694                 struct {
 695                         __le64  out_param;
 696                         __le16  token;
 697                         u8      status;
 698                         u8      rsv0;
 699                 } __packed cmd;
 700          } event;
 701 };
 702
 703 struct hns_roce_eq {
 704         struct hns_roce_dev             *hr_dev;
 705         void __iomem                    *doorbell;
 706
 707         int                             type_flag;/* Aeq:1 ceq:0 */
 708         int                             eqn;
 709         u32                             entries;
 710         int                             log_entries;
 711         int                             eqe_size;
 712         int                             irq;
 713         int                             log_page_size;
 714         int                             cons_index;
 715         struct hns_roce_buf_list        *buf_list;
 716         int                             over_ignore;
 717         int                             coalesce;
 718         int                             arm_st;
 719         u64                             eqe_ba;
 720         int                             eqe_ba_pg_sz;
 721         int                             eqe_buf_pg_sz;
 722         int                             hop_num;
 723         u64                             *bt_l0; /* Base address table for L0 */
 724         u64                             **bt_l1; /* Base address table for L1 */
 725         u64                             **buf;
 726         dma_addr_t                      l0_dma;
 727         dma_addr_t                      *l1_dma;
 728         dma_addr_t                      *buf_dma;
 729         u32                             l0_last_num; /* L0 last chunk num */
 730         u32                             l1_last_num; /* L1 last chunk num */
 731         int                             eq_max_cnt;
 732         int                             eq_period;
 733         int                             shift;
 734         dma_addr_t                      cur_eqe_ba;
 735         dma_addr_t                      nxt_eqe_ba;
 736         int                             event_type;
 737         int                             sub_type;
 738 };
 739
 740 struct hns_roce_eq_table {
 741         struct hns_roce_eq      *eq;
 742         void __iomem            **eqc_base; /* only for hw v1 */
 743 };
 744
 745 struct hns_roce_caps {
 746         u64             fw_ver;
 747         u8              num_ports;
 748         int             gid_table_len[HNS_ROCE_MAX_PORTS];
 749         int             pkey_table_len[HNS_ROCE_MAX_PORTS];
 750         int             local_ca_ack_delay;
 751         int             num_uars;
 752         u32             phy_num_uars;
 753         u32             max_sq_sg;      /* 2 */
 754         u32             max_sq_inline;  /* 32 */
 755         u32             max_rq_sg;      /* 2 */
 756         u32             max_extend_sg;
 757         int             num_qps;        /* 256k */
 758         int             reserved_qps;
 759         int             num_qpc_timer;
 760         int             num_cqc_timer;
 761         u32             max_srq_sg;
 762         int             num_srqs;
 763         u32             max_wqes;       /* 16k */
 764         u32             max_srqs;
 765         u32             max_srq_wrs;
 766         u32             max_srq_sges;
 767         u32             max_sq_desc_sz; /* 64 */
 768         u32             max_rq_desc_sz; /* 64 */
 769         u32             max_srq_desc_sz;
 770         int             max_qp_init_rdma;
 771         int             max_qp_dest_rdma;
 772         int             num_cqs;
 773         int             max_cqes;
 774         int             min_cqes;
 775         u32             min_wqes;
 776         int             reserved_cqs;
 777         int             reserved_srqs;
 778         u32             max_srqwqes;
 779         int             num_aeq_vectors;        /* 1 */
 780         int             num_comp_vectors;
 781         int             num_other_vectors;
 782         int             num_mtpts;
 783         u32             num_mtt_segs;
 784         u32             num_cqe_segs;
 785         u32             num_srqwqe_segs;
 786         u32             num_idx_segs;
 787         int             reserved_mrws;
 788         int             reserved_uars;
 789         int             num_pds;
 790         int             reserved_pds;
 791         u32             mtt_entry_sz;
 792         u32             cq_entry_sz;
 793         u32             page_size_cap;
 794         u32             reserved_lkey;
 795         int             mtpt_entry_sz;
 796         int             qpc_entry_sz;
 797         int             irrl_entry_sz;
 798         int             trrl_entry_sz;
 799         int             cqc_entry_sz;
 800         int             sccc_entry_sz;
 801         int             qpc_timer_entry_sz;
 802         int             cqc_timer_entry_sz;
 803         int             srqc_entry_sz;
 804         int             idx_entry_sz;
 805         u32             pbl_ba_pg_sz;
 806         u32             pbl_buf_pg_sz;
 807         u32             pbl_hop_num;
 808         int             aeqe_depth;
 809         int             ceqe_depth;
 810         enum ib_mtu     max_mtu;
 811         u32             qpc_bt_num;
 812         u32             qpc_timer_bt_num;
 813         u32             srqc_bt_num;
 814         u32             cqc_bt_num;
 815         u32             cqc_timer_bt_num;
 816         u32             mpt_bt_num;
 817         u32             sccc_bt_num;
 818         u32             qpc_ba_pg_sz;
 819         u32             qpc_buf_pg_sz;
 820         u32             qpc_hop_num;
 821         u32             srqc_ba_pg_sz;
 822         u32             srqc_buf_pg_sz;
 823         u32             srqc_hop_num;
 824         u32             cqc_ba_pg_sz;
 825         u32             cqc_buf_pg_sz;
 826         u32             cqc_hop_num;
 827         u32             mpt_ba_pg_sz;
 828         u32             mpt_buf_pg_sz;
 829         u32             mpt_hop_num;
 830         u32             mtt_ba_pg_sz;
 831         u32             mtt_buf_pg_sz;
 832         u32             mtt_hop_num;
 833         u32             sccc_ba_pg_sz;
 834         u32             sccc_buf_pg_sz;
 835         u32             sccc_hop_num;
 836         u32             qpc_timer_ba_pg_sz;
 837         u32             qpc_timer_buf_pg_sz;
 838         u32             qpc_timer_hop_num;
 839         u32             cqc_timer_ba_pg_sz;
 840         u32             cqc_timer_buf_pg_sz;
 841         u32             cqc_timer_hop_num;
 842         u32             cqe_ba_pg_sz;
 843         u32             cqe_buf_pg_sz;
 844         u32             cqe_hop_num;
 845         u32             srqwqe_ba_pg_sz;
 846         u32             srqwqe_buf_pg_sz;
 847         u32             srqwqe_hop_num;
 848         u32             idx_ba_pg_sz;
 849         u32             idx_buf_pg_sz;
 850         u32             idx_hop_num;
 851         u32             eqe_ba_pg_sz;
 852         u32             eqe_buf_pg_sz;
 853         u32             eqe_hop_num;
 854         u32             sl_num;
 855         u32             tsq_buf_pg_sz;
 856         u32             tpq_buf_pg_sz;
 857         u32             chunk_sz;       /* chunk size in non multihop mode*/
 858         u64             flags;
 859 };
 860
 861 struct hns_roce_work {
 862         struct hns_roce_dev *hr_dev;
 863         struct work_struct work;
 864         u32 qpn;
 865         u32 cqn;
 866         int event_type;
 867         int sub_type;
 868 };
 869
 870 struct hns_roce_dfx_hw {
 871         int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
 872                               int *buffer);
 873 };
 874
 875 struct hns_roce_hw {
 876         int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
 877         int (*cmq_init)(struct hns_roce_dev *hr_dev);
 878         void (*cmq_exit)(struct hns_roce_dev *hr_dev);
 879         int (*hw_profile)(struct hns_roce_dev *hr_dev);
 880         int (*hw_init)(struct hns_roce_dev *hr_dev);
 881         void (*hw_exit)(struct hns_roce_dev *hr_dev);
 882         int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
 883                          u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
 884                          u16 token, int event);
 885         int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
 886         int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev);
 887         int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
 888                        const union ib_gid *gid, const struct ib_gid_attr *attr);
 889         int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
 890         void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
 891                         enum ib_mtu mtu);
 892         int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr,
 893                           unsigned long mtpt_idx);
 894         int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
 895                                 struct hns_roce_mr *mr, int flags, u32 pdn,
 896                                 int mr_access_flags, u64 iova, u64 size,
 897                                 void *mb_buf);
 898         int (*frmr_write_mtpt)(void *mb_buf, struct hns_roce_mr *mr);
 899         int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
 900         void (*write_cqc)(struct hns_roce_dev *hr_dev,
 901                           struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
 902                           dma_addr_t dma_handle, int nent, u32 vector);
 903         int (*set_hem)(struct hns_roce_dev *hr_dev,
 904                        struct hns_roce_hem_table *table, int obj, int step_idx);
 905         int (*clear_hem)(struct hns_roce_dev *hr_dev,
 906                          struct hns_roce_hem_table *table, int obj,
 907                          int step_idx);
 908         int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
 909                         int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
 910         int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
 911                          int attr_mask, enum ib_qp_state cur_state,
 912                          enum ib_qp_state new_state);
 913         int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata);
 914         int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
 915                          struct hns_roce_qp *hr_qp);
 916         int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 917                          const struct ib_send_wr **bad_wr);
 918         int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr,
 919                          const struct ib_recv_wr **bad_recv_wr);
 920         int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 921         int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 922         int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
 923                         struct ib_udata *udata);
 924         int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
 925         int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
 926         int (*init_eq)(struct hns_roce_dev *hr_dev);
 927         void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
 928         void (*write_srqc)(struct hns_roce_dev *hr_dev,
 929                            struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn,
 930                            void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx,
 931                            dma_addr_t dma_handle_wqe,
 932                            dma_addr_t dma_handle_idx);
 933         int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
 934                        enum ib_srq_attr_mask srq_attr_mask,
 935                        struct ib_udata *udata);
 936         int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr);
 937         int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
 938                              const struct ib_recv_wr **bad_wr);
 939         const struct ib_device_ops *hns_roce_dev_ops;
 940         const struct ib_device_ops *hns_roce_dev_srq_ops;
 941 };
 942
 943 struct hns_roce_dev {
 944         struct ib_device        ib_dev;
 945         struct platform_device  *pdev;
 946         struct pci_dev          *pci_dev;
 947         struct device           *dev;
 948         struct hns_roce_uar     priv_uar;
 949         const char              *irq_names[HNS_ROCE_MAX_IRQ_NUM];
 950         spinlock_t              sm_lock;
 951         spinlock_t              bt_cmd_lock;
 952         bool                    active;
 953         bool                    is_reset;
 954         bool                    dis_db;
 955         unsigned long           reset_cnt;
 956         struct hns_roce_ib_iboe iboe;
 957
 958         struct list_head        pgdir_list;
 959         struct mutex            pgdir_mutex;
 960         int                     irq[HNS_ROCE_MAX_IRQ_NUM];
 961         u8 __iomem              *reg_base;
 962         struct hns_roce_caps    caps;
 963         struct xarray           qp_table_xa;
 964
 965         unsigned char   dev_addr[HNS_ROCE_MAX_PORTS][MAC_ADDR_OCTET_NUM];
 966         u64                     sys_image_guid;
 967         u32                     vendor_id;
 968         u32                     vendor_part_id;
 969         u32                     hw_rev;
 970         void __iomem            *priv_addr;
 971
 972         struct hns_roce_cmdq    cmd;
 973         struct hns_roce_bitmap    pd_bitmap;
 974         struct hns_roce_uar_table uar_table;
 975         struct hns_roce_mr_table  mr_table;
 976         struct hns_roce_cq_table  cq_table;
 977         struct hns_roce_srq_table srq_table;
 978         struct hns_roce_qp_table  qp_table;
 979         struct hns_roce_eq_table  eq_table;
 980         struct hns_roce_hem_table  qpc_timer_table;
 981         struct hns_roce_hem_table  cqc_timer_table;
 982
 983         int                     cmd_mod;
 984         int                     loop_idc;
 985         u32                     sdb_offset;
 986         u32                     odb_offset;
 987         dma_addr_t              tptr_dma_addr; /*only for hw v1*/
 988         u32                     tptr_size; /*only for hw v1*/
 989         const struct hns_roce_hw *hw;
 990         void                    *priv;
 991         struct workqueue_struct *irq_workq;
 992         const struct hns_roce_dfx_hw *dfx;
 993 };
 994
 995 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
 996 {
 997         return container_of(ib_dev, struct hns_roce_dev, ib_dev);
 998 }
 999
1000 static inline struct hns_roce_ucontext
1001                         *to_hr_ucontext(struct ib_ucontext *ibucontext)
1002 {
1003         return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1004 }
1005
1006 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1007 {
1008         return container_of(ibpd, struct hns_roce_pd, ibpd);
1009 }
1010
1011 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1012 {
1013         return container_of(ibah, struct hns_roce_ah, ibah);
1014 }
1015
1016 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1017 {
1018         return container_of(ibmr, struct hns_roce_mr, ibmr);
1019 }
1020
1021 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1022 {
1023         return container_of(ibmw, struct hns_roce_mw, ibmw);
1024 }
1025
1026 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1027 {
1028         return container_of(ibqp, struct hns_roce_qp, ibqp);
1029 }
1030
1031 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1032 {
1033         return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1034 }
1035
1036 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1037 {
1038         return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1039 }
1040
1041 static inline struct hns_roce_sqp *hr_to_hr_sqp(struct hns_roce_qp *hr_qp)
1042 {
1043         return container_of(hr_qp, struct hns_roce_sqp, hr_qp);
1044 }
1045
1046 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1047 {
1048         __raw_writeq(*(u64 *) val, dest);
1049 }
1050
1051 static inline struct hns_roce_qp
1052         *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1053 {
1054         return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1));
1055 }
1056
1057 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
1058 {
1059         u32 page_size = 1 << buf->page_shift;
1060
1061         if (buf->nbufs == 1)
1062                 return (char *)(buf->direct.buf) + offset;
1063         else
1064                 return (char *)(buf->page_list[offset >> buf->page_shift].buf) +
1065                        (offset & (page_size - 1));
1066 }
1067
1068 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
1069 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1070 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1071 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
1072
1073 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1074 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1075 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1076                         u64 out_param);
1077 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1078 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1079
1080 int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift,
1081                       struct hns_roce_mtt *mtt);
1082 void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev,
1083                           struct hns_roce_mtt *mtt);
1084 int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev,
1085                            struct hns_roce_mtt *mtt, struct hns_roce_buf *buf);
1086
1087 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1088 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1089 int hns_roce_init_eq_table(struct hns_roce_dev *hr_dev);
1090 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1091 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1092 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1093
1094 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
1095 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
1096 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1097 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1098 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1099 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev);
1100
1101 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
1102 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
1103                          int rr);
1104 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
1105                          u32 reserved_bot, u32 resetrved_top);
1106 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
1107 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1108 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
1109                                 int align, unsigned long *obj);
1110 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
1111                                 unsigned long obj, int cnt,
1112                                 int rr);
1113
1114 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr,
1115                        u32 flags, struct ib_udata *udata);
1116 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1117 void hns_roce_destroy_ah(struct ib_ah *ah, u32 flags);
1118
1119 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1120 void hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1121
1122 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1123 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1124                                    u64 virt_addr, int access_flags,
1125                                    struct ib_udata *udata);
1126 int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length,
1127                            u64 virt_addr, int mr_access_flags, struct ib_pd *pd,
1128                            struct ib_udata *udata);
1129 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1130                                 u32 max_num_sg, struct ib_udata *udata);
1131 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1132                        unsigned int *sg_offset);
1133 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1134 int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev,
1135                        struct hns_roce_cmd_mailbox *mailbox,
1136                        unsigned long mpt_index);
1137 unsigned long key_to_hw_index(u32 key);
1138
1139 struct ib_mw *hns_roce_alloc_mw(struct ib_pd *pd, enum ib_mw_type,
1140                                 struct ib_udata *udata);
1141 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1142
1143 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, u32 size,
1144                        struct hns_roce_buf *buf);
1145 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
1146                        struct hns_roce_buf *buf, u32 page_shift);
1147
1148 int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev,
1149                                struct hns_roce_mtt *mtt, struct ib_umem *umem);
1150
1151 int hns_roce_create_srq(struct ib_srq *srq,
1152                         struct ib_srq_init_attr *srq_init_attr,
1153                         struct ib_udata *udata);
1154 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1155                         enum ib_srq_attr_mask srq_attr_mask,
1156                         struct ib_udata *udata);
1157 void hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1158
1159 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
1160                                  struct ib_qp_init_attr *init_attr,
1161                                  struct ib_udata *udata);
1162 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1163                        int attr_mask, struct ib_udata *udata);
1164 void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
1165 void *get_send_wqe(struct hns_roce_qp *hr_qp, int n);
1166 void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n);
1167 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
1168                           struct ib_cq *ib_cq);
1169 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1170 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1171                        struct hns_roce_cq *recv_cq);
1172 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1173                          struct hns_roce_cq *recv_cq);
1174 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1175 void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1176 void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
1177                                int cnt);
1178 __be32 send_ieth(const struct ib_send_wr *wr);
1179 int to_hr_qp_type(int qp_type);
1180
1181 struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
1182                                     const struct ib_cq_init_attr *attr,
1183                                     struct ib_udata *udata);
1184
1185 int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1186 void hns_roce_free_cq(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq);
1187
1188 int hns_roce_db_map_user(struct hns_roce_ucontext *context,
1189                          struct ib_udata *udata, unsigned long virt,
1190                          struct hns_roce_db *db);
1191 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1192                             struct hns_roce_db *db);
1193 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1194                       int order);
1195 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1196
1197 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1198 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1199 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1200 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1201 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
1202 int hns_roce_init(struct hns_roce_dev *hr_dev);
1203 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1204
1205 int hns_roce_fill_res_entry(struct sk_buff *msg,
1206                             struct rdma_restrack_entry *res);
1207 #endif /* _HNS_ROCE_DEVICE_H */