drivers/infiniband/hw/hns/hns_roce_device.h

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _HNS_ROCE_DEVICE_H
  34 #define _HNS_ROCE_DEVICE_H
  35
  36 #include <rdma/ib_verbs.h>
  37 #include <rdma/hns-abi.h>
  38
  39 #define DRV_NAME "hns_roce"
  40
  41 #define PCI_REVISION_ID_HIP08                   0x21
  42 #define PCI_REVISION_ID_HIP09                   0x30
  43
  44 #define HNS_ROCE_HW_VER1        ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
  45
  46 #define HNS_ROCE_MAX_MSG_LEN                    0x80000000
  47
  48 #define HNS_ROCE_IB_MIN_SQ_STRIDE               6
  49
  50 #define HNS_ROCE_BA_SIZE                        (32 * 4096)
  51
  52 #define BA_BYTE_LEN                             8
  53
  54 /* Hardware specification only for v1 engine */
  55 #define HNS_ROCE_MIN_CQE_NUM                    0x40
  56 #define HNS_ROCE_MIN_WQE_NUM                    0x20
  57 #define HNS_ROCE_MIN_SRQ_WQE_NUM                1
  58
  59 /* Hardware specification only for v1 engine */
  60 #define HNS_ROCE_MAX_INNER_MTPT_NUM             0x7
  61 #define HNS_ROCE_MAX_MTPT_PBL_NUM               0x100000
  62
  63 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS        20
  64 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT   \
  65         (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
  66 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT             0x2
  67 #define HNS_ROCE_MIN_CQE_CNT                    16
  68
  69 #define HNS_ROCE_RESERVED_SGE                   1
  70
  71 #define HNS_ROCE_MAX_IRQ_NUM                    128
  72
  73 #define HNS_ROCE_SGE_IN_WQE                     2
  74 #define HNS_ROCE_SGE_SHIFT                      4
  75
  76 #define EQ_ENABLE                               1
  77 #define EQ_DISABLE                              0
  78
  79 #define HNS_ROCE_CEQ                            0
  80 #define HNS_ROCE_AEQ                            1
  81
  82 #define HNS_ROCE_CEQE_SIZE 0x4
  83 #define HNS_ROCE_AEQE_SIZE 0x10
  84
  85 #define HNS_ROCE_V3_EQE_SIZE 0x40
  86
  87 #define HNS_ROCE_V2_CQE_SIZE 32
  88 #define HNS_ROCE_V3_CQE_SIZE 64
  89
  90 #define HNS_ROCE_V2_QPC_SZ 256
  91 #define HNS_ROCE_V3_QPC_SZ 512
  92
  93 #define HNS_ROCE_MAX_PORTS                      6
  94 #define HNS_ROCE_GID_SIZE                       16
  95 #define HNS_ROCE_SGE_SIZE                       16
  96 #define HNS_ROCE_DWQE_SIZE                      65536
  97
  98 #define HNS_ROCE_HOP_NUM_0                      0xff
  99
 100 #define BITMAP_NO_RR                            0
 101 #define BITMAP_RR                               1
 102
 103 #define MR_TYPE_MR                              0x00
 104 #define MR_TYPE_FRMR                            0x01
 105 #define MR_TYPE_DMA                             0x03
 106
 107 #define HNS_ROCE_FRMR_MAX_PA                    512
 108
 109 #define PKEY_ID                                 0xffff
 110 #define GUID_LEN                                8
 111 #define NODE_DESC_SIZE                          64
 112 #define DB_REG_OFFSET                           0x1000
 113
 114 /* Configure to HW for PAGE_SIZE larger than 4KB */
 115 #define PG_SHIFT_OFFSET                         (PAGE_SHIFT - 12)
 116
 117 #define PAGES_SHIFT_8                           8
 118 #define PAGES_SHIFT_16                          16
 119 #define PAGES_SHIFT_24                          24
 120 #define PAGES_SHIFT_32                          32
 121
 122 #define HNS_ROCE_IDX_QUE_ENTRY_SZ               4
 123 #define SRQ_DB_REG                              0x230
 124
 125 #define HNS_ROCE_QP_BANK_NUM 8
 126 #define HNS_ROCE_CQ_BANK_NUM 4
 127
 128 #define CQ_BANKID_SHIFT 2
 129
 130 /* The chip implementation of the consumer index is calculated
 131  * according to twice the actual EQ depth
 132  */
 133 #define EQ_DEPTH_COEFF                          2
 134
 135 enum {
 136         SERV_TYPE_RC,
 137         SERV_TYPE_UC,
 138         SERV_TYPE_RD,
 139         SERV_TYPE_UD,
 140 };
 141
 142 enum hns_roce_qp_state {
 143         HNS_ROCE_QP_STATE_RST,
 144         HNS_ROCE_QP_STATE_INIT,
 145         HNS_ROCE_QP_STATE_RTR,
 146         HNS_ROCE_QP_STATE_RTS,
 147         HNS_ROCE_QP_STATE_SQD,
 148         HNS_ROCE_QP_STATE_ERR,
 149         HNS_ROCE_QP_NUM_STATE,
 150 };
 151
 152 enum hns_roce_event {
 153         HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
 154         HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
 155         HNS_ROCE_EVENT_TYPE_COMM_EST                  = 0x03,
 156         HNS_ROCE_EVENT_TYPE_SQ_DRAINED                = 0x04,
 157         HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR            = 0x05,
 158         HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR    = 0x06,
 159         HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR     = 0x07,
 160         HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH           = 0x08,
 161         HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH        = 0x09,
 162         HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR           = 0x0a,
 163         HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR           = 0x0b,
 164         HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW               = 0x0c,
 165         HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID             = 0x0d,
 166         HNS_ROCE_EVENT_TYPE_PORT_CHANGE               = 0x0f,
 167         /* 0x10 and 0x11 is unused in currently application case */
 168         HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,
 169         HNS_ROCE_EVENT_TYPE_MB                        = 0x13,
 170         HNS_ROCE_EVENT_TYPE_FLR                       = 0x15,
 171 };
 172
 173 #define HNS_ROCE_CAP_FLAGS_EX_SHIFT 12
 174
 175 enum {
 176         HNS_ROCE_CAP_FLAG_REREG_MR              = BIT(0),
 177         HNS_ROCE_CAP_FLAG_ROCE_V1_V2            = BIT(1),
 178         HNS_ROCE_CAP_FLAG_RQ_INLINE             = BIT(2),
 179         HNS_ROCE_CAP_FLAG_RECORD_DB             = BIT(3),
 180         HNS_ROCE_CAP_FLAG_SQ_RECORD_DB          = BIT(4),
 181         HNS_ROCE_CAP_FLAG_SRQ                   = BIT(5),
 182         HNS_ROCE_CAP_FLAG_MW                    = BIT(7),
 183         HNS_ROCE_CAP_FLAG_FRMR                  = BIT(8),
 184         HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL          = BIT(9),
 185         HNS_ROCE_CAP_FLAG_ATOMIC                = BIT(10),
 186         HNS_ROCE_CAP_FLAG_SDI_MODE              = BIT(14),
 187         HNS_ROCE_CAP_FLAG_STASH                 = BIT(17),
 188 };
 189
 190 #define HNS_ROCE_DB_TYPE_COUNT                  2
 191 #define HNS_ROCE_DB_UNIT_SIZE                   4
 192
 193 enum {
 194         HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
 195 };
 196
 197 enum hns_roce_reset_stage {
 198         HNS_ROCE_STATE_NON_RST,
 199         HNS_ROCE_STATE_RST_BEF_DOWN,
 200         HNS_ROCE_STATE_RST_DOWN,
 201         HNS_ROCE_STATE_RST_UNINIT,
 202         HNS_ROCE_STATE_RST_INIT,
 203         HNS_ROCE_STATE_RST_INITED,
 204 };
 205
 206 enum hns_roce_instance_state {
 207         HNS_ROCE_STATE_NON_INIT,
 208         HNS_ROCE_STATE_INIT,
 209         HNS_ROCE_STATE_INITED,
 210         HNS_ROCE_STATE_UNINIT,
 211 };
 212
 213 enum {
 214         HNS_ROCE_RST_DIRECT_RETURN              = 0,
 215 };
 216
 217 enum {
 218         CMD_RST_PRC_OTHERS,
 219         CMD_RST_PRC_SUCCESS,
 220         CMD_RST_PRC_EBUSY,
 221 };
 222
 223 #define HNS_ROCE_CMD_SUCCESS                    1
 224
 225 /* The minimum page size is 4K for hardware */
 226 #define HNS_HW_PAGE_SHIFT                       12
 227 #define HNS_HW_PAGE_SIZE                        (1 << HNS_HW_PAGE_SHIFT)
 228
 229 struct hns_roce_uar {
 230         u64             pfn;
 231         unsigned long   index;
 232         unsigned long   logic_idx;
 233 };
 234
 235 struct hns_roce_ucontext {
 236         struct ib_ucontext      ibucontext;
 237         struct hns_roce_uar     uar;
 238         struct list_head        page_list;
 239         struct mutex            page_mutex;
 240 };
 241
 242 struct hns_roce_pd {
 243         struct ib_pd            ibpd;
 244         unsigned long           pdn;
 245 };
 246
 247 struct hns_roce_bitmap {
 248         /* Bitmap Traversal last a bit which is 1 */
 249         unsigned long           last;
 250         unsigned long           top;
 251         unsigned long           max;
 252         unsigned long           reserved_top;
 253         unsigned long           mask;
 254         spinlock_t              lock;
 255         unsigned long           *table;
 256 };
 257
 258 /* For Hardware Entry Memory */
 259 struct hns_roce_hem_table {
 260         /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
 261         u32             type;
 262         /* HEM array elment num */
 263         unsigned long   num_hem;
 264         /* HEM entry record obj total num */
 265         unsigned long   num_obj;
 266         /* Single obj size */
 267         unsigned long   obj_size;
 268         unsigned long   table_chunk_size;
 269         int             lowmem;
 270         struct mutex    mutex;
 271         struct hns_roce_hem **hem;
 272         u64             **bt_l1;
 273         dma_addr_t      *bt_l1_dma_addr;
 274         u64             **bt_l0;
 275         dma_addr_t      *bt_l0_dma_addr;
 276 };
 277
 278 struct hns_roce_buf_region {
 279         u32 offset; /* page offset */
 280         u32 count; /* page count */
 281         int hopnum; /* addressing hop num */
 282 };
 283
 284 #define HNS_ROCE_MAX_BT_REGION  3
 285 #define HNS_ROCE_MAX_BT_LEVEL   3
 286 struct hns_roce_hem_list {
 287         struct list_head root_bt;
 288         /* link all bt dma mem by hop config */
 289         struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
 290         struct list_head btm_bt; /* link all bottom bt in @mid_bt */
 291         dma_addr_t root_ba; /* pointer to the root ba table */
 292 };
 293
 294 struct hns_roce_buf_attr {
 295         struct {
 296                 size_t  size;  /* region size */
 297                 int     hopnum; /* multi-hop addressing hop num */
 298         } region[HNS_ROCE_MAX_BT_REGION];
 299         unsigned int region_count; /* valid region count */
 300         unsigned int page_shift;  /* buffer page shift */
 301         unsigned int user_access; /* umem access flag */
 302         bool mtt_only; /* only alloc buffer-required MTT memory */
 303 };
 304
 305 struct hns_roce_hem_cfg {
 306         dma_addr_t      root_ba; /* root BA table's address */
 307         bool            is_direct; /* addressing without BA table */
 308         unsigned int    ba_pg_shift; /* BA table page shift */
 309         unsigned int    buf_pg_shift; /* buffer page shift */
 310         unsigned int    buf_pg_count;  /* buffer page count */
 311         struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION];
 312         unsigned int    region_count;
 313 };
 314
 315 /* memory translate region */
 316 struct hns_roce_mtr {
 317         struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
 318         struct ib_umem          *umem; /* user space buffer */
 319         struct hns_roce_buf     *kmem; /* kernel space buffer */
 320         struct hns_roce_hem_cfg  hem_cfg; /* config for hardware addressing */
 321 };
 322
 323 struct hns_roce_mw {
 324         struct ib_mw            ibmw;
 325         u32                     pdn;
 326         u32                     rkey;
 327         int                     enabled; /* MW's active status */
 328         u32                     pbl_hop_num;
 329         u32                     pbl_ba_pg_sz;
 330         u32                     pbl_buf_pg_sz;
 331 };
 332
 333 /* Only support 4K page size for mr register */
 334 #define MR_SIZE_4K 0
 335
 336 struct hns_roce_mr {
 337         struct ib_mr            ibmr;
 338         u64                     iova; /* MR's virtual orignal addr */
 339         u64                     size; /* Address range of MR */
 340         u32                     key; /* Key of MR */
 341         u32                     pd;   /* PD num of MR */
 342         u32                     access; /* Access permission of MR */
 343         int                     enabled; /* MR's active status */
 344         int                     type;   /* MR's register type */
 345         u32                     pbl_hop_num;    /* multi-hop number */
 346         struct hns_roce_mtr     pbl_mtr;
 347         u32                     npages;
 348         dma_addr_t              *page_list;
 349 };
 350
 351 struct hns_roce_mr_table {
 352         struct hns_roce_bitmap          mtpt_bitmap;
 353         struct hns_roce_hem_table       mtpt_table;
 354 };
 355
 356 struct hns_roce_wq {
 357         u64             *wrid;     /* Work request ID */
 358         spinlock_t      lock;
 359         u32             wqe_cnt;  /* WQE num */
 360         u32             max_gs;
 361         u32             rsv_sge;
 362         int             offset;
 363         int             wqe_shift;      /* WQE size */
 364         u32             head;
 365         u32             tail;
 366         void __iomem    *db_reg_l;
 367 };
 368
 369 struct hns_roce_sge {
 370         unsigned int    sge_cnt;        /* SGE num */
 371         int             offset;
 372         int             sge_shift;      /* SGE size */
 373 };
 374
 375 struct hns_roce_buf_list {
 376         void            *buf;
 377         dma_addr_t      map;
 378 };
 379
 380 /*
 381  * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous
 382  * dma address range.
 383  *
 384  * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep.
 385  *
 386  * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even
 387  * the allocated size is smaller than the required size.
 388  */
 389 enum {
 390         HNS_ROCE_BUF_DIRECT = BIT(0),
 391         HNS_ROCE_BUF_NOSLEEP = BIT(1),
 392         HNS_ROCE_BUF_NOFAIL = BIT(2),
 393 };
 394
 395 struct hns_roce_buf {
 396         struct hns_roce_buf_list        *trunk_list;
 397         u32                             ntrunks;
 398         u32                             npages;
 399         unsigned int                    trunk_shift;
 400         unsigned int                    page_shift;
 401 };
 402
 403 struct hns_roce_db_pgdir {
 404         struct list_head        list;
 405         DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
 406         DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
 407         unsigned long           *bits[HNS_ROCE_DB_TYPE_COUNT];
 408         u32                     *page;
 409         dma_addr_t              db_dma;
 410 };
 411
 412 struct hns_roce_user_db_page {
 413         struct list_head        list;
 414         struct ib_umem          *umem;
 415         unsigned long           user_virt;
 416         refcount_t              refcount;
 417 };
 418
 419 struct hns_roce_db {
 420         u32             *db_record;
 421         union {
 422                 struct hns_roce_db_pgdir *pgdir;
 423                 struct hns_roce_user_db_page *user_page;
 424         } u;
 425         dma_addr_t      dma;
 426         void            *virt_addr;
 427         unsigned long   index;
 428         unsigned long   order;
 429 };
 430
 431 struct hns_roce_cq {
 432         struct ib_cq                    ib_cq;
 433         struct hns_roce_mtr             mtr;
 434         struct hns_roce_db              db;
 435         u32                             flags;
 436         spinlock_t                      lock;
 437         u32                             cq_depth;
 438         u32                             cons_index;
 439         u32                             *set_ci_db;
 440         void __iomem                    *cq_db_l;
 441         u16                             *tptr_addr;
 442         int                             arm_sn;
 443         int                             cqe_size;
 444         unsigned long                   cqn;
 445         u32                             vector;
 446         atomic_t                        refcount;
 447         struct completion               free;
 448         struct list_head                sq_list; /* all qps on this send cq */
 449         struct list_head                rq_list; /* all qps on this recv cq */
 450         int                             is_armed; /* cq is armed */
 451         struct list_head                node; /* all armed cqs are on a list */
 452 };
 453
 454 struct hns_roce_idx_que {
 455         struct hns_roce_mtr             mtr;
 456         int                             entry_shift;
 457         unsigned long                   *bitmap;
 458         u32                             head;
 459         u32                             tail;
 460 };
 461
 462 struct hns_roce_srq {
 463         struct ib_srq           ibsrq;
 464         unsigned long           srqn;
 465         u32                     wqe_cnt;
 466         int                     max_gs;
 467         u32                     rsv_sge;
 468         int                     wqe_shift;
 469         u32                     cqn;
 470         void __iomem            *db_reg_l;
 471
 472         atomic_t                refcount;
 473         struct completion       free;
 474
 475         struct hns_roce_mtr     buf_mtr;
 476
 477         u64                    *wrid;
 478         struct hns_roce_idx_que idx_que;
 479         spinlock_t              lock;
 480         struct mutex            mutex;
 481         void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
 482 };
 483
 484 struct hns_roce_uar_table {
 485         struct hns_roce_bitmap bitmap;
 486 };
 487
 488 struct hns_roce_bank {
 489         struct ida ida;
 490         u32 inuse; /* Number of IDs allocated */
 491         u32 min; /* Lowest ID to allocate.  */
 492         u32 max; /* Highest ID to allocate. */
 493         u32 next; /* Next ID to allocate. */
 494 };
 495
 496 struct hns_roce_qp_table {
 497         struct hns_roce_hem_table       qp_table;
 498         struct hns_roce_hem_table       irrl_table;
 499         struct hns_roce_hem_table       trrl_table;
 500         struct hns_roce_hem_table       sccc_table;
 501         struct mutex                    scc_mutex;
 502         struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
 503         struct mutex bank_mutex;
 504 };
 505
 506 struct hns_roce_cq_table {
 507         struct xarray                   array;
 508         struct hns_roce_hem_table       table;
 509         struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM];
 510         struct mutex                    bank_mutex;
 511 };
 512
 513 struct hns_roce_srq_table {
 514         struct hns_roce_bitmap          bitmap;
 515         struct xarray                   xa;
 516         struct hns_roce_hem_table       table;
 517 };
 518
 519 struct hns_roce_raq_table {
 520         struct hns_roce_buf_list        *e_raq_buf;
 521 };
 522
 523 struct hns_roce_av {
 524         u8 port;
 525         u8 gid_index;
 526         u8 stat_rate;
 527         u8 hop_limit;
 528         u32 flowlabel;
 529         u16 udp_sport;
 530         u8 sl;
 531         u8 tclass;
 532         u8 dgid[HNS_ROCE_GID_SIZE];
 533         u8 mac[ETH_ALEN];
 534         u16 vlan_id;
 535         u8 vlan_en;
 536 };
 537
 538 struct hns_roce_ah {
 539         struct ib_ah            ibah;
 540         struct hns_roce_av      av;
 541 };
 542
 543 struct hns_roce_cmd_context {
 544         struct completion       done;
 545         int                     result;
 546         int                     next;
 547         u64                     out_param;
 548         u16                     token;
 549 };
 550
 551 struct hns_roce_cmdq {
 552         struct dma_pool         *pool;
 553         struct mutex            hcr_mutex;
 554         struct semaphore        poll_sem;
 555         /*
 556          * Event mode: cmd register mutex protection,
 557          * ensure to not exceed max_cmds and user use limit region
 558          */
 559         struct semaphore        event_sem;
 560         int                     max_cmds;
 561         spinlock_t              context_lock;
 562         int                     free_head;
 563         struct hns_roce_cmd_context *context;
 564         /*
 565          * Result of get integer part
 566          * which max_comds compute according a power of 2
 567          */
 568         u16                     token_mask;
 569         /*
 570          * Process whether use event mode, init default non-zero
 571          * After the event queue of cmd event ready,
 572          * can switch into event mode
 573          * close device, switch into poll mode(non event mode)
 574          */
 575         u8                      use_events;
 576 };
 577
 578 struct hns_roce_cmd_mailbox {
 579         void                   *buf;
 580         dma_addr_t              dma;
 581 };
 582
 583 struct hns_roce_dev;
 584
 585 struct hns_roce_rinl_sge {
 586         void                    *addr;
 587         u32                     len;
 588 };
 589
 590 struct hns_roce_rinl_wqe {
 591         struct hns_roce_rinl_sge *sg_list;
 592         u32                      sge_cnt;
 593 };
 594
 595 struct hns_roce_rinl_buf {
 596         struct hns_roce_rinl_wqe *wqe_list;
 597         u32                      wqe_cnt;
 598 };
 599
 600 enum {
 601         HNS_ROCE_FLUSH_FLAG = 0,
 602 };
 603
 604 struct hns_roce_work {
 605         struct hns_roce_dev *hr_dev;
 606         struct work_struct work;
 607         int event_type;
 608         int sub_type;
 609         u32 queue_num;
 610 };
 611
 612 enum {
 613         HNS_ROCE_QP_CAP_DIRECT_WQE = BIT(5),
 614 };
 615
 616 struct hns_roce_qp {
 617         struct ib_qp            ibqp;
 618         struct hns_roce_wq      rq;
 619         struct hns_roce_db      rdb;
 620         struct hns_roce_db      sdb;
 621         unsigned long           en_flags;
 622         u32                     doorbell_qpn;
 623         enum ib_sig_type        sq_signal_bits;
 624         struct hns_roce_wq      sq;
 625
 626         struct hns_roce_mtr     mtr;
 627
 628         u32                     buff_size;
 629         struct mutex            mutex;
 630         u8                      port;
 631         u8                      phy_port;
 632         u8                      sl;
 633         u8                      resp_depth;
 634         u8                      state;
 635         u32                     access_flags;
 636         u32                     atomic_rd_en;
 637         u32                     pkey_index;
 638         u32                     qkey;
 639         void                    (*event)(struct hns_roce_qp *qp,
 640                                          enum hns_roce_event event_type);
 641         unsigned long           qpn;
 642
 643         atomic_t                refcount;
 644         struct completion       free;
 645
 646         struct hns_roce_sge     sge;
 647         u32                     next_sge;
 648         enum ib_mtu             path_mtu;
 649         u32                     max_inline_data;
 650
 651         /* 0: flush needed, 1: unneeded */
 652         unsigned long           flush_flag;
 653         struct hns_roce_work    flush_work;
 654         struct hns_roce_rinl_buf rq_inl_buf;
 655         struct list_head        node;           /* all qps are on a list */
 656         struct list_head        rq_node;        /* all recv qps are on a list */
 657         struct list_head        sq_node;        /* all send qps are on a list */
 658 };
 659
 660 struct hns_roce_ib_iboe {
 661         spinlock_t              lock;
 662         struct net_device      *netdevs[HNS_ROCE_MAX_PORTS];
 663         struct notifier_block   nb;
 664         u8                      phy_port[HNS_ROCE_MAX_PORTS];
 665 };
 666
 667 enum {
 668         HNS_ROCE_EQ_STAT_INVALID  = 0,
 669         HNS_ROCE_EQ_STAT_VALID    = 2,
 670 };
 671
 672 struct hns_roce_ceqe {
 673         __le32  comp;
 674         __le32  rsv[15];
 675 };
 676
 677 struct hns_roce_aeqe {
 678         __le32 asyn;
 679         union {
 680                 struct {
 681                         __le32 num;
 682                         u32 rsv0;
 683                         u32 rsv1;
 684                 } queue_event;
 685
 686                 struct {
 687                         __le64  out_param;
 688                         __le16  token;
 689                         u8      status;
 690                         u8      rsv0;
 691                 } __packed cmd;
 692          } event;
 693         __le32 rsv[12];
 694 };
 695
 696 struct hns_roce_eq {
 697         struct hns_roce_dev             *hr_dev;
 698         void __iomem                    *doorbell;
 699
 700         int                             type_flag; /* Aeq:1 ceq:0 */
 701         int                             eqn;
 702         u32                             entries;
 703         u32                             log_entries;
 704         int                             eqe_size;
 705         int                             irq;
 706         int                             log_page_size;
 707         u32                             cons_index;
 708         struct hns_roce_buf_list        *buf_list;
 709         int                             over_ignore;
 710         int                             coalesce;
 711         int                             arm_st;
 712         int                             hop_num;
 713         struct hns_roce_mtr             mtr;
 714         u16                             eq_max_cnt;
 715         u32                             eq_period;
 716         int                             shift;
 717         int                             event_type;
 718         int                             sub_type;
 719 };
 720
 721 struct hns_roce_eq_table {
 722         struct hns_roce_eq      *eq;
 723         void __iomem            **eqc_base; /* only for hw v1 */
 724 };
 725
 726 struct hns_roce_caps {
 727         u64             fw_ver;
 728         u8              num_ports;
 729         int             gid_table_len[HNS_ROCE_MAX_PORTS];
 730         int             pkey_table_len[HNS_ROCE_MAX_PORTS];
 731         int             local_ca_ack_delay;
 732         int             num_uars;
 733         u32             phy_num_uars;
 734         u32             max_sq_sg;
 735         u32             max_sq_inline;
 736         u32             max_rq_sg;
 737         u32             max_extend_sg;
 738         u32             num_qps;
 739         u32             reserved_qps;
 740         int             num_qpc_timer;
 741         int             num_cqc_timer;
 742         int             num_srqs;
 743         u32             max_wqes;
 744         u32             max_srq_wrs;
 745         u32             max_srq_sges;
 746         u32             max_sq_desc_sz;
 747         u32             max_rq_desc_sz;
 748         u32             max_srq_desc_sz;
 749         int             max_qp_init_rdma;
 750         int             max_qp_dest_rdma;
 751         u32             num_cqs;
 752         u32             max_cqes;
 753         u32             min_cqes;
 754         u32             min_wqes;
 755         u32             reserved_cqs;
 756         int             reserved_srqs;
 757         int             num_aeq_vectors;
 758         int             num_comp_vectors;
 759         int             num_other_vectors;
 760         u32             num_mtpts;
 761         u32             num_mtt_segs;
 762         u32             num_cqe_segs;
 763         u32             num_srqwqe_segs;
 764         u32             num_idx_segs;
 765         int             reserved_mrws;
 766         int             reserved_uars;
 767         int             num_pds;
 768         int             reserved_pds;
 769         u32             mtt_entry_sz;
 770         u32             cqe_sz;
 771         u32             page_size_cap;
 772         u32             reserved_lkey;
 773         int             mtpt_entry_sz;
 774         int             qpc_sz;
 775         int             irrl_entry_sz;
 776         int             trrl_entry_sz;
 777         int             cqc_entry_sz;
 778         int             sccc_sz;
 779         int             qpc_timer_entry_sz;
 780         int             cqc_timer_entry_sz;
 781         int             srqc_entry_sz;
 782         int             idx_entry_sz;
 783         u32             pbl_ba_pg_sz;
 784         u32             pbl_buf_pg_sz;
 785         u32             pbl_hop_num;
 786         int             aeqe_depth;
 787         int             ceqe_depth;
 788         u32             aeqe_size;
 789         u32             ceqe_size;
 790         enum ib_mtu     max_mtu;
 791         u32             qpc_bt_num;
 792         u32             qpc_timer_bt_num;
 793         u32             srqc_bt_num;
 794         u32             cqc_bt_num;
 795         u32             cqc_timer_bt_num;
 796         u32             mpt_bt_num;
 797         u32             sccc_bt_num;
 798         u32             gmv_bt_num;
 799         u32             qpc_ba_pg_sz;
 800         u32             qpc_buf_pg_sz;
 801         u32             qpc_hop_num;
 802         u32             srqc_ba_pg_sz;
 803         u32             srqc_buf_pg_sz;
 804         u32             srqc_hop_num;
 805         u32             cqc_ba_pg_sz;
 806         u32             cqc_buf_pg_sz;
 807         u32             cqc_hop_num;
 808         u32             mpt_ba_pg_sz;
 809         u32             mpt_buf_pg_sz;
 810         u32             mpt_hop_num;
 811         u32             mtt_ba_pg_sz;
 812         u32             mtt_buf_pg_sz;
 813         u32             mtt_hop_num;
 814         u32             wqe_sq_hop_num;
 815         u32             wqe_sge_hop_num;
 816         u32             wqe_rq_hop_num;
 817         u32             sccc_ba_pg_sz;
 818         u32             sccc_buf_pg_sz;
 819         u32             sccc_hop_num;
 820         u32             qpc_timer_ba_pg_sz;
 821         u32             qpc_timer_buf_pg_sz;
 822         u32             qpc_timer_hop_num;
 823         u32             cqc_timer_ba_pg_sz;
 824         u32             cqc_timer_buf_pg_sz;
 825         u32             cqc_timer_hop_num;
 826         u32             cqe_ba_pg_sz;   /* page_size = 4K*(2^cqe_ba_pg_sz) */
 827         u32             cqe_buf_pg_sz;
 828         u32             cqe_hop_num;
 829         u32             srqwqe_ba_pg_sz;
 830         u32             srqwqe_buf_pg_sz;
 831         u32             srqwqe_hop_num;
 832         u32             idx_ba_pg_sz;
 833         u32             idx_buf_pg_sz;
 834         u32             idx_hop_num;
 835         u32             eqe_ba_pg_sz;
 836         u32             eqe_buf_pg_sz;
 837         u32             eqe_hop_num;
 838         u32             gmv_entry_num;
 839         u32             gmv_entry_sz;
 840         u32             gmv_ba_pg_sz;
 841         u32             gmv_buf_pg_sz;
 842         u32             gmv_hop_num;
 843         u32             sl_num;
 844         u32             tsq_buf_pg_sz;
 845         u32             tpq_buf_pg_sz;
 846         u32             chunk_sz;       /* chunk size in non multihop mode */
 847         u64             flags;
 848         u16             default_ceq_max_cnt;
 849         u16             default_ceq_period;
 850         u16             default_aeq_max_cnt;
 851         u16             default_aeq_period;
 852         u16             default_aeq_arm_st;
 853         u16             default_ceq_arm_st;
 854 };
 855
 856 struct hns_roce_dfx_hw {
 857         int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
 858                               int *buffer);
 859 };
 860
 861 enum hns_roce_device_state {
 862         HNS_ROCE_DEVICE_STATE_INITED,
 863         HNS_ROCE_DEVICE_STATE_RST_DOWN,
 864         HNS_ROCE_DEVICE_STATE_UNINIT,
 865 };
 866
 867 struct hns_roce_hw {
 868         int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
 869         int (*cmq_init)(struct hns_roce_dev *hr_dev);
 870         void (*cmq_exit)(struct hns_roce_dev *hr_dev);
 871         int (*hw_profile)(struct hns_roce_dev *hr_dev);
 872         int (*hw_init)(struct hns_roce_dev *hr_dev);
 873         void (*hw_exit)(struct hns_roce_dev *hr_dev);
 874         int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
 875                          u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
 876                          u16 token, int event);
 877         int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned int timeout);
 878         int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev);
 879         int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
 880                        const union ib_gid *gid, const struct ib_gid_attr *attr);
 881         int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
 882         void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
 883                         enum ib_mtu mtu);
 884         int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
 885                           struct hns_roce_mr *mr, unsigned long mtpt_idx);
 886         int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
 887                                 struct hns_roce_mr *mr, int flags,
 888                                 void *mb_buf);
 889         int (*frmr_write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf,
 890                                struct hns_roce_mr *mr);
 891         int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
 892         void (*write_cqc)(struct hns_roce_dev *hr_dev,
 893                           struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
 894                           dma_addr_t dma_handle);
 895         int (*set_hem)(struct hns_roce_dev *hr_dev,
 896                        struct hns_roce_hem_table *table, int obj, int step_idx);
 897         int (*clear_hem)(struct hns_roce_dev *hr_dev,
 898                          struct hns_roce_hem_table *table, int obj,
 899                          int step_idx);
 900         int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
 901                         int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
 902         int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
 903                          int attr_mask, enum ib_qp_state cur_state,
 904                          enum ib_qp_state new_state);
 905         int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata);
 906         int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
 907                          struct hns_roce_qp *hr_qp);
 908         int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 909                          const struct ib_send_wr **bad_wr);
 910         int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr,
 911                          const struct ib_recv_wr **bad_recv_wr);
 912         int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 913         int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 914         int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
 915                         struct ib_udata *udata);
 916         int (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
 917         int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
 918         int (*init_eq)(struct hns_roce_dev *hr_dev);
 919         void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
 920         int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf);
 921         int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
 922                        enum ib_srq_attr_mask srq_attr_mask,
 923                        struct ib_udata *udata);
 924         int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr);
 925         int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
 926                              const struct ib_recv_wr **bad_wr);
 927         const struct ib_device_ops *hns_roce_dev_ops;
 928         const struct ib_device_ops *hns_roce_dev_srq_ops;
 929 };
 930
 931 struct hns_roce_dev {
 932         struct ib_device        ib_dev;
 933         struct platform_device  *pdev;
 934         struct pci_dev          *pci_dev;
 935         struct device           *dev;
 936         struct hns_roce_uar     priv_uar;
 937         const char              *irq_names[HNS_ROCE_MAX_IRQ_NUM];
 938         spinlock_t              sm_lock;
 939         spinlock_t              bt_cmd_lock;
 940         bool                    active;
 941         bool                    is_reset;
 942         bool                    dis_db;
 943         unsigned long           reset_cnt;
 944         struct hns_roce_ib_iboe iboe;
 945         enum hns_roce_device_state state;
 946         struct list_head        qp_list; /* list of all qps on this dev */
 947         spinlock_t              qp_list_lock; /* protect qp_list */
 948
 949         struct list_head        pgdir_list;
 950         struct mutex            pgdir_mutex;
 951         int                     irq[HNS_ROCE_MAX_IRQ_NUM];
 952         u8 __iomem              *reg_base;
 953         void __iomem            *mem_base;
 954         struct hns_roce_caps    caps;
 955         struct xarray           qp_table_xa;
 956
 957         unsigned char   dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
 958         u64                     sys_image_guid;
 959         u32                     vendor_id;
 960         u32                     vendor_part_id;
 961         u32                     hw_rev;
 962         void __iomem            *priv_addr;
 963
 964         struct hns_roce_cmdq    cmd;
 965         struct hns_roce_bitmap    pd_bitmap;
 966         struct hns_roce_uar_table uar_table;
 967         struct hns_roce_mr_table  mr_table;
 968         struct hns_roce_cq_table  cq_table;
 969         struct hns_roce_srq_table srq_table;
 970         struct hns_roce_qp_table  qp_table;
 971         struct hns_roce_eq_table  eq_table;
 972         struct hns_roce_hem_table  qpc_timer_table;
 973         struct hns_roce_hem_table  cqc_timer_table;
 974         /* GMV is the memory area that the driver allocates for the hardware
 975          * to store SGID, SMAC and VLAN information.
 976          */
 977         struct hns_roce_hem_table  gmv_table;
 978
 979         int                     cmd_mod;
 980         int                     loop_idc;
 981         u32                     sdb_offset;
 982         u32                     odb_offset;
 983         dma_addr_t              tptr_dma_addr;  /* only for hw v1 */
 984         u32                     tptr_size;      /* only for hw v1 */
 985         const struct hns_roce_hw *hw;
 986         void                    *priv;
 987         struct workqueue_struct *irq_workq;
 988         const struct hns_roce_dfx_hw *dfx;
 989 };
 990
 991 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
 992 {
 993         return container_of(ib_dev, struct hns_roce_dev, ib_dev);
 994 }
 995
 996 static inline struct hns_roce_ucontext
 997                         *to_hr_ucontext(struct ib_ucontext *ibucontext)
 998 {
 999         return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1000 }
1001
1002 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1003 {
1004         return container_of(ibpd, struct hns_roce_pd, ibpd);
1005 }
1006
1007 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1008 {
1009         return container_of(ibah, struct hns_roce_ah, ibah);
1010 }
1011
1012 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1013 {
1014         return container_of(ibmr, struct hns_roce_mr, ibmr);
1015 }
1016
1017 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1018 {
1019         return container_of(ibmw, struct hns_roce_mw, ibmw);
1020 }
1021
1022 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1023 {
1024         return container_of(ibqp, struct hns_roce_qp, ibqp);
1025 }
1026
1027 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1028 {
1029         return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1030 }
1031
1032 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1033 {
1034         return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1035 }
1036
1037 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1038 {
1039         writeq(*(u64 *)val, dest);
1040 }
1041
1042 static inline struct hns_roce_qp
1043         *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1044 {
1045         return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1));
1046 }
1047
1048 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf,
1049                                         unsigned int offset)
1050 {
1051         return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) +
1052                         (offset & ((1 << buf->trunk_shift) - 1));
1053 }
1054
1055 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx)
1056 {
1057         unsigned int offset = idx << buf->page_shift;
1058
1059         return buf->trunk_list[offset >> buf->trunk_shift].map +
1060                         (offset & ((1 << buf->trunk_shift) - 1));
1061 }
1062
1063 #define hr_hw_page_align(x)             ALIGN(x, 1 << HNS_HW_PAGE_SHIFT)
1064
1065 static inline u64 to_hr_hw_page_addr(u64 addr)
1066 {
1067         return addr >> HNS_HW_PAGE_SHIFT;
1068 }
1069
1070 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1071 {
1072         return page_shift - HNS_HW_PAGE_SHIFT;
1073 }
1074
1075 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count)
1076 {
1077         if (count > 0)
1078                 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum;
1079
1080         return 0;
1081 }
1082
1083 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift)
1084 {
1085         return hr_hw_page_align(count << buf_shift);
1086 }
1087
1088 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift)
1089 {
1090         return hr_hw_page_align(count << buf_shift) >> buf_shift;
1091 }
1092
1093 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift)
1094 {
1095         if (!count)
1096                 return 0;
1097
1098         return ilog2(to_hr_hem_entries_count(count, buf_shift));
1099 }
1100
1101 #define DSCP_SHIFT 2
1102
1103 static inline u8 get_tclass(const struct ib_global_route *grh)
1104 {
1105         return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ?
1106                grh->traffic_class >> DSCP_SHIFT : grh->traffic_class;
1107 }
1108
1109 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
1110 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1111 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1112 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
1113
1114 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1115 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1116 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1117                         u64 out_param);
1118 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1119 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1120
1121 /* hns roce hw need current block and next block addr from mtt */
1122 #define MTT_MIN_COUNT    2
1123 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1124                       int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1125 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1126                         struct hns_roce_buf_attr *buf_attr,
1127                         unsigned int page_shift, struct ib_udata *udata,
1128                         unsigned long user_addr);
1129 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1130                           struct hns_roce_mtr *mtr);
1131 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1132                      dma_addr_t *pages, unsigned int page_cnt);
1133
1134 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1135 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1136 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1137 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1138 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1139
1140 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
1141 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
1142 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1143 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1144 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1145 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev);
1146
1147 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
1148 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
1149                          int rr);
1150 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
1151                          u32 reserved_bot, u32 resetrved_top);
1152 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
1153 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1154 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
1155                                 int align, unsigned long *obj);
1156 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
1157                                 unsigned long obj, int cnt,
1158                                 int rr);
1159
1160 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1161                        struct ib_udata *udata);
1162 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1163 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags)
1164 {
1165         return 0;
1166 }
1167
1168 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1169 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1170
1171 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1172 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1173                                    u64 virt_addr, int access_flags,
1174                                    struct ib_udata *udata);
1175 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start,
1176                                      u64 length, u64 virt_addr,
1177                                      int mr_access_flags, struct ib_pd *pd,
1178                                      struct ib_udata *udata);
1179 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1180                                 u32 max_num_sg);
1181 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1182                        unsigned int *sg_offset);
1183 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1184 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
1185                             struct hns_roce_cmd_mailbox *mailbox,
1186                             unsigned long mpt_index);
1187 unsigned long key_to_hw_index(u32 key);
1188
1189 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1190 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1191
1192 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1193 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size,
1194                                         u32 page_shift, u32 flags);
1195
1196 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1197                            int buf_cnt, int start, struct hns_roce_buf *buf);
1198 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1199                            int buf_cnt, int start, struct ib_umem *umem,
1200                            unsigned int page_shift);
1201
1202 int hns_roce_create_srq(struct ib_srq *srq,
1203                         struct ib_srq_init_attr *srq_init_attr,
1204                         struct ib_udata *udata);
1205 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1206                         enum ib_srq_attr_mask srq_attr_mask,
1207                         struct ib_udata *udata);
1208 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1209
1210 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
1211                                  struct ib_qp_init_attr *init_attr,
1212                                  struct ib_udata *udata);
1213 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1214                        int attr_mask, struct ib_udata *udata);
1215 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1216 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1217 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n);
1218 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n);
1219 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq,
1220                           struct ib_cq *ib_cq);
1221 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1222 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1223                        struct hns_roce_cq *recv_cq);
1224 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1225                          struct hns_roce_cq *recv_cq);
1226 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1227 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1228                          struct ib_udata *udata);
1229 __be32 send_ieth(const struct ib_send_wr *wr);
1230 int to_hr_qp_type(int qp_type);
1231
1232 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1233                        struct ib_udata *udata);
1234
1235 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1236 int hns_roce_db_map_user(struct hns_roce_ucontext *context,
1237                          struct ib_udata *udata, unsigned long virt,
1238                          struct hns_roce_db *db);
1239 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1240                             struct hns_roce_db *db);
1241 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1242                       int order);
1243 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1244
1245 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1246 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1247 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1248 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1249 u8 hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
1250 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1251 int hns_roce_init(struct hns_roce_dev *hr_dev);
1252 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1253 int hns_roce_fill_res_cq_entry(struct sk_buff *msg,
1254                                struct ib_cq *ib_cq);
1255 #endif /* _HNS_ROCE_DEVICE_H */