drivers/infiniband/hw/hns/hns_roce_device.h

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef _HNS_ROCE_DEVICE_H
  34 #define _HNS_ROCE_DEVICE_H
  35
  36 #include <rdma/ib_verbs.h>
  37
  38 #define DRV_NAME "hns_roce"
  39
  40 /* hip08 is a pci device, it includes two version according pci version id */
  41 #define PCI_REVISION_ID_HIP08_A                 0x20
  42 #define PCI_REVISION_ID_HIP08_B                 0x21
  43
  44 #define HNS_ROCE_HW_VER1        ('h' << 24 | 'i' << 16 | '0' << 8 | '6')
  45
  46 #define HNS_ROCE_MAX_MSG_LEN                    0x80000000
  47
  48 #define HNS_ROCE_IB_MIN_SQ_STRIDE               6
  49
  50 #define HNS_ROCE_BA_SIZE                        (32 * 4096)
  51
  52 #define BA_BYTE_LEN                             8
  53
  54 /* Hardware specification only for v1 engine */
  55 #define HNS_ROCE_MIN_CQE_NUM                    0x40
  56 #define HNS_ROCE_MIN_WQE_NUM                    0x20
  57
  58 /* Hardware specification only for v1 engine */
  59 #define HNS_ROCE_MAX_INNER_MTPT_NUM             0x7
  60 #define HNS_ROCE_MAX_MTPT_PBL_NUM               0x100000
  61 #define HNS_ROCE_MAX_SGE_NUM                    2
  62
  63 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS        20
  64 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT   \
  65         (5000 / HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS)
  66 #define HNS_ROCE_CQE_WCMD_EMPTY_BIT             0x2
  67 #define HNS_ROCE_MIN_CQE_CNT                    16
  68
  69 #define HNS_ROCE_MAX_IRQ_NUM                    128
  70
  71 #define HNS_ROCE_SGE_IN_WQE                     2
  72 #define HNS_ROCE_SGE_SHIFT                      4
  73
  74 #define EQ_ENABLE                               1
  75 #define EQ_DISABLE                              0
  76
  77 #define HNS_ROCE_CEQ                            0
  78 #define HNS_ROCE_AEQ                            1
  79
  80 #define HNS_ROCE_CEQ_ENTRY_SIZE                 0x4
  81 #define HNS_ROCE_AEQ_ENTRY_SIZE                 0x10
  82
  83 #define HNS_ROCE_SL_SHIFT                       28
  84 #define HNS_ROCE_TCLASS_SHIFT                   20
  85 #define HNS_ROCE_FLOW_LABEL_MASK                0xfffff
  86
  87 #define HNS_ROCE_MAX_PORTS                      6
  88 #define HNS_ROCE_MAX_GID_NUM                    16
  89 #define HNS_ROCE_GID_SIZE                       16
  90 #define HNS_ROCE_SGE_SIZE                       16
  91
  92 #define HNS_ROCE_HOP_NUM_0                      0xff
  93
  94 #define BITMAP_NO_RR                            0
  95 #define BITMAP_RR                               1
  96
  97 #define MR_TYPE_MR                              0x00
  98 #define MR_TYPE_FRMR                            0x01
  99 #define MR_TYPE_DMA                             0x03
 100
 101 #define HNS_ROCE_FRMR_MAX_PA                    512
 102
 103 #define PKEY_ID                                 0xffff
 104 #define GUID_LEN                                8
 105 #define NODE_DESC_SIZE                          64
 106 #define DB_REG_OFFSET                           0x1000
 107
 108 /* Configure to HW for PAGE_SIZE larger than 4KB */
 109 #define PG_SHIFT_OFFSET                         (PAGE_SHIFT - 12)
 110
 111 #define PAGES_SHIFT_8                           8
 112 #define PAGES_SHIFT_16                          16
 113 #define PAGES_SHIFT_24                          24
 114 #define PAGES_SHIFT_32                          32
 115
 116 #define HNS_ROCE_PCI_BAR_NUM                    2
 117
 118 #define HNS_ROCE_IDX_QUE_ENTRY_SZ               4
 119 #define SRQ_DB_REG                              0x230
 120
 121 /* The chip implementation of the consumer index is calculated
 122  * according to twice the actual EQ depth
 123  */
 124 #define EQ_DEPTH_COEFF                          2
 125
 126 enum {
 127         SERV_TYPE_RC,
 128         SERV_TYPE_UC,
 129         SERV_TYPE_RD,
 130         SERV_TYPE_UD,
 131 };
 132
 133 enum {
 134         HNS_ROCE_SUPPORT_RQ_RECORD_DB = 1 << 0,
 135         HNS_ROCE_SUPPORT_SQ_RECORD_DB = 1 << 1,
 136 };
 137
 138 enum {
 139         HNS_ROCE_SUPPORT_CQ_RECORD_DB = 1 << 0,
 140 };
 141
 142 enum hns_roce_qp_state {
 143         HNS_ROCE_QP_STATE_RST,
 144         HNS_ROCE_QP_STATE_INIT,
 145         HNS_ROCE_QP_STATE_RTR,
 146         HNS_ROCE_QP_STATE_RTS,
 147         HNS_ROCE_QP_STATE_SQD,
 148         HNS_ROCE_QP_STATE_ERR,
 149         HNS_ROCE_QP_NUM_STATE,
 150 };
 151
 152 enum hns_roce_event {
 153         HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
 154         HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
 155         HNS_ROCE_EVENT_TYPE_COMM_EST                  = 0x03,
 156         HNS_ROCE_EVENT_TYPE_SQ_DRAINED                = 0x04,
 157         HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR            = 0x05,
 158         HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR    = 0x06,
 159         HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR     = 0x07,
 160         HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH           = 0x08,
 161         HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH        = 0x09,
 162         HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR           = 0x0a,
 163         HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR           = 0x0b,
 164         HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW               = 0x0c,
 165         HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID             = 0x0d,
 166         HNS_ROCE_EVENT_TYPE_PORT_CHANGE               = 0x0f,
 167         /* 0x10 and 0x11 is unused in currently application case */
 168         HNS_ROCE_EVENT_TYPE_DB_OVERFLOW               = 0x12,
 169         HNS_ROCE_EVENT_TYPE_MB                        = 0x13,
 170         HNS_ROCE_EVENT_TYPE_CEQ_OVERFLOW              = 0x14,
 171         HNS_ROCE_EVENT_TYPE_FLR                       = 0x15,
 172 };
 173
 174 /* Local Work Queue Catastrophic Error,SUBTYPE 0x5 */
 175 enum {
 176         HNS_ROCE_LWQCE_QPC_ERROR                = 1,
 177         HNS_ROCE_LWQCE_MTU_ERROR                = 2,
 178         HNS_ROCE_LWQCE_WQE_BA_ADDR_ERROR        = 3,
 179         HNS_ROCE_LWQCE_WQE_ADDR_ERROR           = 4,
 180         HNS_ROCE_LWQCE_SQ_WQE_SHIFT_ERROR       = 5,
 181         HNS_ROCE_LWQCE_SL_ERROR                 = 6,
 182         HNS_ROCE_LWQCE_PORT_ERROR               = 7,
 183 };
 184
 185 /* Local Access Violation Work Queue Error,SUBTYPE 0x7 */
 186 enum {
 187         HNS_ROCE_LAVWQE_R_KEY_VIOLATION         = 1,
 188         HNS_ROCE_LAVWQE_LENGTH_ERROR            = 2,
 189         HNS_ROCE_LAVWQE_VA_ERROR                = 3,
 190         HNS_ROCE_LAVWQE_PD_ERROR                = 4,
 191         HNS_ROCE_LAVWQE_RW_ACC_ERROR            = 5,
 192         HNS_ROCE_LAVWQE_KEY_STATE_ERROR         = 6,
 193         HNS_ROCE_LAVWQE_MR_OPERATION_ERROR      = 7,
 194 };
 195
 196 /* DOORBELL overflow subtype */
 197 enum {
 198         HNS_ROCE_DB_SUBTYPE_SDB_OVF             = 1,
 199         HNS_ROCE_DB_SUBTYPE_SDB_ALM_OVF         = 2,
 200         HNS_ROCE_DB_SUBTYPE_ODB_OVF             = 3,
 201         HNS_ROCE_DB_SUBTYPE_ODB_ALM_OVF         = 4,
 202         HNS_ROCE_DB_SUBTYPE_SDB_ALM_EMP         = 5,
 203         HNS_ROCE_DB_SUBTYPE_ODB_ALM_EMP         = 6,
 204 };
 205
 206 enum {
 207         /* RQ&SRQ related operations */
 208         HNS_ROCE_OPCODE_SEND_DATA_RECEIVE       = 0x06,
 209         HNS_ROCE_OPCODE_RDMA_WITH_IMM_RECEIVE   = 0x07,
 210 };
 211
 212 enum {
 213         HNS_ROCE_CAP_FLAG_REREG_MR              = BIT(0),
 214         HNS_ROCE_CAP_FLAG_ROCE_V1_V2            = BIT(1),
 215         HNS_ROCE_CAP_FLAG_RQ_INLINE             = BIT(2),
 216         HNS_ROCE_CAP_FLAG_RECORD_DB             = BIT(3),
 217         HNS_ROCE_CAP_FLAG_SQ_RECORD_DB          = BIT(4),
 218         HNS_ROCE_CAP_FLAG_SRQ                   = BIT(5),
 219         HNS_ROCE_CAP_FLAG_MW                    = BIT(7),
 220         HNS_ROCE_CAP_FLAG_FRMR                  = BIT(8),
 221         HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL          = BIT(9),
 222         HNS_ROCE_CAP_FLAG_ATOMIC                = BIT(10),
 223 };
 224
 225 enum hns_roce_mtt_type {
 226         MTT_TYPE_WQE,
 227         MTT_TYPE_CQE,
 228         MTT_TYPE_SRQWQE,
 229         MTT_TYPE_IDX
 230 };
 231
 232 #define HNS_ROCE_DB_TYPE_COUNT                  2
 233 #define HNS_ROCE_DB_UNIT_SIZE                   4
 234
 235 enum {
 236         HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
 237 };
 238
 239 enum hns_roce_reset_stage {
 240         HNS_ROCE_STATE_NON_RST,
 241         HNS_ROCE_STATE_RST_BEF_DOWN,
 242         HNS_ROCE_STATE_RST_DOWN,
 243         HNS_ROCE_STATE_RST_UNINIT,
 244         HNS_ROCE_STATE_RST_INIT,
 245         HNS_ROCE_STATE_RST_INITED,
 246 };
 247
 248 enum hns_roce_instance_state {
 249         HNS_ROCE_STATE_NON_INIT,
 250         HNS_ROCE_STATE_INIT,
 251         HNS_ROCE_STATE_INITED,
 252         HNS_ROCE_STATE_UNINIT,
 253 };
 254
 255 enum {
 256         HNS_ROCE_RST_DIRECT_RETURN              = 0,
 257 };
 258
 259 enum {
 260         CMD_RST_PRC_OTHERS,
 261         CMD_RST_PRC_SUCCESS,
 262         CMD_RST_PRC_EBUSY,
 263 };
 264
 265 #define HNS_ROCE_CMD_SUCCESS                    1
 266
 267 #define HNS_ROCE_PORT_DOWN                      0
 268 #define HNS_ROCE_PORT_UP                        1
 269
 270 #define HNS_ROCE_MTT_ENTRY_PER_SEG              8
 271
 272 #define PAGE_ADDR_SHIFT                         12
 273
 274 /* The minimum page count for hardware access page directly. */
 275 #define HNS_HW_DIRECT_PAGE_COUNT 2
 276
 277 struct hns_roce_uar {
 278         u64             pfn;
 279         unsigned long   index;
 280         unsigned long   logic_idx;
 281 };
 282
 283 struct hns_roce_ucontext {
 284         struct ib_ucontext      ibucontext;
 285         struct hns_roce_uar     uar;
 286         struct list_head        page_list;
 287         struct mutex            page_mutex;
 288 };
 289
 290 struct hns_roce_pd {
 291         struct ib_pd            ibpd;
 292         unsigned long           pdn;
 293 };
 294
 295 struct hns_roce_bitmap {
 296         /* Bitmap Traversal last a bit which is 1 */
 297         unsigned long           last;
 298         unsigned long           top;
 299         unsigned long           max;
 300         unsigned long           reserved_top;
 301         unsigned long           mask;
 302         spinlock_t              lock;
 303         unsigned long           *table;
 304 };
 305
 306 /* Order bitmap length -- bit num compute formula: 1 << (max_order - order) */
 307 /* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */
 308 /* Every bit repesent to a partner free/used status in bitmap */
 309 /*
 310  * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1
 311  * Bit = 1 represent to idle and available; bit = 0: not available
 312  */
 313 struct hns_roce_buddy {
 314         /* Members point to every order level bitmap */
 315         unsigned long **bits;
 316         /* Represent to avail bits of the order level bitmap */
 317         u32            *num_free;
 318         int             max_order;
 319         spinlock_t      lock;
 320 };
 321
 322 /* For Hardware Entry Memory */
 323 struct hns_roce_hem_table {
 324         /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */
 325         u32             type;
 326         /* HEM array elment num */
 327         unsigned long   num_hem;
 328         /* HEM entry record obj total num */
 329         unsigned long   num_obj;
 330         /* Single obj size */
 331         unsigned long   obj_size;
 332         unsigned long   table_chunk_size;
 333         int             lowmem;
 334         struct mutex    mutex;
 335         struct hns_roce_hem **hem;
 336         u64             **bt_l1;
 337         dma_addr_t      *bt_l1_dma_addr;
 338         u64             **bt_l0;
 339         dma_addr_t      *bt_l0_dma_addr;
 340 };
 341
 342 struct hns_roce_mtt {
 343         unsigned long           first_seg;
 344         int                     order;
 345         int                     page_shift;
 346         enum hns_roce_mtt_type  mtt_type;
 347 };
 348
 349 struct hns_roce_buf_region {
 350         int offset; /* page offset */
 351         u32 count; /* page count */
 352         int hopnum; /* addressing hop num */
 353 };
 354
 355 #define HNS_ROCE_MAX_BT_REGION  3
 356 #define HNS_ROCE_MAX_BT_LEVEL   3
 357 struct hns_roce_hem_list {
 358         struct list_head root_bt;
 359         /* link all bt dma mem by hop config */
 360         struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL];
 361         struct list_head btm_bt; /* link all bottom bt in @mid_bt */
 362         dma_addr_t root_ba; /* pointer to the root ba table */
 363 };
 364
 365 struct hns_roce_buf_attr {
 366         struct {
 367                 size_t  size;  /* region size */
 368                 int     hopnum; /* multi-hop addressing hop num */
 369         } region[HNS_ROCE_MAX_BT_REGION];
 370         int region_count; /* valid region count */
 371         int page_shift;  /* buffer page shift */
 372         bool fixed_page; /* decide page shift is fixed-size or maximum size */
 373         int user_access; /* umem access flag */
 374         bool mtt_only; /* only alloc buffer-required MTT memory */
 375 };
 376
 377 /* memory translate region */
 378 struct hns_roce_mtr {
 379         struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */
 380         struct ib_umem           *umem; /* user space buffer */
 381         struct hns_roce_buf      *kmem; /* kernel space buffer */
 382         struct {
 383                 dma_addr_t       root_ba; /* root BA table's address */
 384                 bool             is_direct; /* addressing without BA table */
 385                 int              ba_pg_shift; /* BA table page shift */
 386                 int              buf_pg_shift; /* buffer page shift */
 387                 int              buf_pg_count;  /* buffer page count */
 388         } hem_cfg; /* config for hardware addressing */
 389 };
 390
 391 struct hns_roce_mw {
 392         struct ib_mw            ibmw;
 393         u32                     pdn;
 394         u32                     rkey;
 395         int                     enabled; /* MW's active status */
 396         u32                     pbl_hop_num;
 397         u32                     pbl_ba_pg_sz;
 398         u32                     pbl_buf_pg_sz;
 399 };
 400
 401 /* Only support 4K page size for mr register */
 402 #define MR_SIZE_4K 0
 403
 404 struct hns_roce_mr {
 405         struct ib_mr            ibmr;
 406         struct ib_umem          *umem;
 407         u64                     iova; /* MR's virtual orignal addr */
 408         u64                     size; /* Address range of MR */
 409         u32                     key; /* Key of MR */
 410         u32                     pd;   /* PD num of MR */
 411         u32                     access; /* Access permission of MR */
 412         u32                     npages;
 413         int                     enabled; /* MR's active status */
 414         int                     type;   /* MR's register type */
 415         u64                     *pbl_buf;       /* MR's PBL space */
 416         dma_addr_t              pbl_dma_addr;   /* MR's PBL space PA */
 417         u32                     pbl_size;       /* PA number in the PBL */
 418         u64                     pbl_ba;         /* page table address */
 419         u32                     l0_chunk_last_num;      /* L0 last number */
 420         u32                     l1_chunk_last_num;      /* L1 last number */
 421         u64                     **pbl_bt_l2;    /* PBL BT L2 */
 422         u64                     **pbl_bt_l1;    /* PBL BT L1 */
 423         u64                     *pbl_bt_l0;     /* PBL BT L0 */
 424         dma_addr_t              *pbl_l2_dma_addr;       /* PBL BT L2 dma addr */
 425         dma_addr_t              *pbl_l1_dma_addr;       /* PBL BT L1 dma addr */
 426         dma_addr_t              pbl_l0_dma_addr;        /* PBL BT L0 dma addr */
 427         u32                     pbl_ba_pg_sz;   /* BT chunk page size */
 428         u32                     pbl_buf_pg_sz;  /* buf chunk page size */
 429         u32                     pbl_hop_num;    /* multi-hop number */
 430 };
 431
 432 struct hns_roce_mr_table {
 433         struct hns_roce_bitmap          mtpt_bitmap;
 434         struct hns_roce_buddy           mtt_buddy;
 435         struct hns_roce_hem_table       mtt_table;
 436         struct hns_roce_hem_table       mtpt_table;
 437         struct hns_roce_buddy           mtt_cqe_buddy;
 438         struct hns_roce_hem_table       mtt_cqe_table;
 439         struct hns_roce_buddy           mtt_srqwqe_buddy;
 440         struct hns_roce_hem_table       mtt_srqwqe_table;
 441         struct hns_roce_buddy           mtt_idx_buddy;
 442         struct hns_roce_hem_table       mtt_idx_table;
 443 };
 444
 445 struct hns_roce_wq {
 446         u64             *wrid;     /* Work request ID */
 447         spinlock_t      lock;
 448         u32             wqe_cnt;  /* WQE num */
 449         int             max_gs;
 450         int             offset;
 451         int             wqe_shift;      /* WQE size */
 452         u32             head;
 453         u32             tail;
 454         void __iomem    *db_reg_l;
 455 };
 456
 457 struct hns_roce_sge {
 458         int             sge_cnt;        /* SGE num */
 459         int             offset;
 460         int             sge_shift;      /* SGE size */
 461 };
 462
 463 struct hns_roce_buf_list {
 464         void            *buf;
 465         dma_addr_t      map;
 466 };
 467
 468 struct hns_roce_buf {
 469         struct hns_roce_buf_list        direct;
 470         struct hns_roce_buf_list        *page_list;
 471         u32                             npages;
 472         u32                             size;
 473         int                             page_shift;
 474 };
 475
 476 struct hns_roce_db_pgdir {
 477         struct list_head        list;
 478         DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
 479         DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
 480         unsigned long           *bits[HNS_ROCE_DB_TYPE_COUNT];
 481         u32                     *page;
 482         dma_addr_t              db_dma;
 483 };
 484
 485 struct hns_roce_user_db_page {
 486         struct list_head        list;
 487         struct ib_umem          *umem;
 488         unsigned long           user_virt;
 489         refcount_t              refcount;
 490 };
 491
 492 struct hns_roce_db {
 493         u32             *db_record;
 494         union {
 495                 struct hns_roce_db_pgdir *pgdir;
 496                 struct hns_roce_user_db_page *user_page;
 497         } u;
 498         dma_addr_t      dma;
 499         void            *virt_addr;
 500         int             index;
 501         int             order;
 502 };
 503
 504 struct hns_roce_cq {
 505         struct ib_cq                    ib_cq;
 506         struct hns_roce_buf             buf;
 507         struct hns_roce_mtt             mtt;
 508         struct hns_roce_db              db;
 509         u8                              db_en;
 510         spinlock_t                      lock;
 511         struct ib_umem                  *umem;
 512         u32                             buf_size;
 513         int                             page_shift;
 514         u32                             cq_depth;
 515         u32                             cons_index;
 516         u32                             *set_ci_db;
 517         void __iomem                    *cq_db_l;
 518         u16                             *tptr_addr;
 519         int                             arm_sn;
 520         unsigned long                   cqn;
 521         u32                             vector;
 522         atomic_t                        refcount;
 523         struct completion               free;
 524         struct list_head                sq_list; /* all qps on this send cq */
 525         struct list_head                rq_list; /* all qps on this recv cq */
 526         int                             is_armed; /* cq is armed */
 527         struct list_head                node; /* all armed cqs are on a list */
 528 };
 529
 530 struct hns_roce_idx_que {
 531         struct hns_roce_mtr             mtr;
 532         int                             entry_sz;
 533         unsigned long                   *bitmap;
 534 };
 535
 536 struct hns_roce_srq {
 537         struct ib_srq           ibsrq;
 538         unsigned long           srqn;
 539         u32                     wqe_cnt;
 540         int                     max_gs;
 541         int                     wqe_shift;
 542         void __iomem            *db_reg_l;
 543
 544         atomic_t                refcount;
 545         struct completion       free;
 546
 547         struct hns_roce_mtr     buf_mtr;
 548
 549         u64                    *wrid;
 550         struct hns_roce_idx_que idx_que;
 551         spinlock_t              lock;
 552         int                     head;
 553         int                     tail;
 554         struct mutex            mutex;
 555         void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event);
 556 };
 557
 558 struct hns_roce_uar_table {
 559         struct hns_roce_bitmap bitmap;
 560 };
 561
 562 struct hns_roce_qp_table {
 563         struct hns_roce_bitmap          bitmap;
 564         struct hns_roce_hem_table       qp_table;
 565         struct hns_roce_hem_table       irrl_table;
 566         struct hns_roce_hem_table       trrl_table;
 567         struct hns_roce_hem_table       sccc_table;
 568         struct mutex                    scc_mutex;
 569 };
 570
 571 struct hns_roce_cq_table {
 572         struct hns_roce_bitmap          bitmap;
 573         struct xarray                   array;
 574         struct hns_roce_hem_table       table;
 575 };
 576
 577 struct hns_roce_srq_table {
 578         struct hns_roce_bitmap          bitmap;
 579         struct xarray                   xa;
 580         struct hns_roce_hem_table       table;
 581 };
 582
 583 struct hns_roce_raq_table {
 584         struct hns_roce_buf_list        *e_raq_buf;
 585 };
 586
 587 struct hns_roce_av {
 588         u8          port;
 589         u8          gid_index;
 590         u8          stat_rate;
 591         u8          hop_limit;
 592         u32         flowlabel;
 593         u8          sl;
 594         u8          tclass;
 595         u8          dgid[HNS_ROCE_GID_SIZE];
 596         u8          mac[ETH_ALEN];
 597         u16         vlan_id;
 598         bool        vlan_en;
 599 };
 600
 601 struct hns_roce_ah {
 602         struct ib_ah            ibah;
 603         struct hns_roce_av      av;
 604 };
 605
 606 struct hns_roce_cmd_context {
 607         struct completion       done;
 608         int                     result;
 609         int                     next;
 610         u64                     out_param;
 611         u16                     token;
 612 };
 613
 614 struct hns_roce_cmdq {
 615         struct dma_pool         *pool;
 616         struct mutex            hcr_mutex;
 617         struct semaphore        poll_sem;
 618         /*
 619          * Event mode: cmd register mutex protection,
 620          * ensure to not exceed max_cmds and user use limit region
 621          */
 622         struct semaphore        event_sem;
 623         int                     max_cmds;
 624         spinlock_t              context_lock;
 625         int                     free_head;
 626         struct hns_roce_cmd_context *context;
 627         /*
 628          * Result of get integer part
 629          * which max_comds compute according a power of 2
 630          */
 631         u16                     token_mask;
 632         /*
 633          * Process whether use event mode, init default non-zero
 634          * After the event queue of cmd event ready,
 635          * can switch into event mode
 636          * close device, switch into poll mode(non event mode)
 637          */
 638         u8                      use_events;
 639 };
 640
 641 struct hns_roce_cmd_mailbox {
 642         void                   *buf;
 643         dma_addr_t              dma;
 644 };
 645
 646 struct hns_roce_dev;
 647
 648 struct hns_roce_rinl_sge {
 649         void                    *addr;
 650         u32                     len;
 651 };
 652
 653 struct hns_roce_rinl_wqe {
 654         struct hns_roce_rinl_sge *sg_list;
 655         u32                      sge_cnt;
 656 };
 657
 658 struct hns_roce_rinl_buf {
 659         struct hns_roce_rinl_wqe *wqe_list;
 660         u32                      wqe_cnt;
 661 };
 662
 663 enum {
 664         HNS_ROCE_FLUSH_FLAG = 0,
 665 };
 666
 667 struct hns_roce_work {
 668         struct hns_roce_dev *hr_dev;
 669         struct work_struct work;
 670         u32 qpn;
 671         u32 cqn;
 672         int event_type;
 673         int sub_type;
 674 };
 675
 676 struct hns_roce_qp {
 677         struct ib_qp            ibqp;
 678         struct hns_roce_wq      rq;
 679         struct hns_roce_db      rdb;
 680         struct hns_roce_db      sdb;
 681         u8                      rdb_en;
 682         u8                      sdb_en;
 683         u32                     doorbell_qpn;
 684         u32                     sq_signal_bits;
 685         struct hns_roce_wq      sq;
 686
 687         struct hns_roce_mtr     mtr;
 688
 689         u32                     buff_size;
 690         struct mutex            mutex;
 691         u8                      port;
 692         u8                      phy_port;
 693         u8                      sl;
 694         u8                      resp_depth;
 695         u8                      state;
 696         u32                     access_flags;
 697         u32                     atomic_rd_en;
 698         u32                     pkey_index;
 699         u32                     qkey;
 700         void                    (*event)(struct hns_roce_qp *qp,
 701                                          enum hns_roce_event event_type);
 702         unsigned long           qpn;
 703
 704         atomic_t                refcount;
 705         struct completion       free;
 706
 707         struct hns_roce_sge     sge;
 708         u32                     next_sge;
 709
 710         /* 0: flush needed, 1: unneeded */
 711         unsigned long           flush_flag;
 712         struct hns_roce_work    flush_work;
 713         struct hns_roce_rinl_buf rq_inl_buf;
 714         struct list_head        node;           /* all qps are on a list */
 715         struct list_head        rq_node;        /* all recv qps are on a list */
 716         struct list_head        sq_node;        /* all send qps are on a list */
 717 };
 718
 719 struct hns_roce_ib_iboe {
 720         spinlock_t              lock;
 721         struct net_device      *netdevs[HNS_ROCE_MAX_PORTS];
 722         struct notifier_block   nb;
 723         u8                      phy_port[HNS_ROCE_MAX_PORTS];
 724 };
 725
 726 enum {
 727         HNS_ROCE_EQ_STAT_INVALID  = 0,
 728         HNS_ROCE_EQ_STAT_VALID    = 2,
 729 };
 730
 731 struct hns_roce_ceqe {
 732         __le32                  comp;
 733 };
 734
 735 struct hns_roce_aeqe {
 736         __le32 asyn;
 737         union {
 738                 struct {
 739                         __le32 qp;
 740                         u32 rsv0;
 741                         u32 rsv1;
 742                 } qp_event;
 743
 744                 struct {
 745                         __le32 srq;
 746                         u32 rsv0;
 747                         u32 rsv1;
 748                 } srq_event;
 749
 750                 struct {
 751                         __le32 cq;
 752                         u32 rsv0;
 753                         u32 rsv1;
 754                 } cq_event;
 755
 756                 struct {
 757                         __le32 ceqe;
 758                         u32 rsv0;
 759                         u32 rsv1;
 760                 } ce_event;
 761
 762                 struct {
 763                         __le64  out_param;
 764                         __le16  token;
 765                         u8      status;
 766                         u8      rsv0;
 767                 } __packed cmd;
 768          } event;
 769 };
 770
 771 struct hns_roce_eq {
 772         struct hns_roce_dev             *hr_dev;
 773         void __iomem                    *doorbell;
 774
 775         int                             type_flag; /* Aeq:1 ceq:0 */
 776         int                             eqn;
 777         u32                             entries;
 778         int                             log_entries;
 779         int                             eqe_size;
 780         int                             irq;
 781         int                             log_page_size;
 782         int                             cons_index;
 783         struct hns_roce_buf_list        *buf_list;
 784         int                             over_ignore;
 785         int                             coalesce;
 786         int                             arm_st;
 787         int                             hop_num;
 788         struct hns_roce_mtr             mtr;
 789         int                             eq_max_cnt;
 790         int                             eq_period;
 791         int                             shift;
 792         int                             event_type;
 793         int                             sub_type;
 794 };
 795
 796 struct hns_roce_eq_table {
 797         struct hns_roce_eq      *eq;
 798         void __iomem            **eqc_base; /* only for hw v1 */
 799 };
 800
 801 struct hns_roce_caps {
 802         u64             fw_ver;
 803         u8              num_ports;
 804         int             gid_table_len[HNS_ROCE_MAX_PORTS];
 805         int             pkey_table_len[HNS_ROCE_MAX_PORTS];
 806         int             local_ca_ack_delay;
 807         int             num_uars;
 808         u32             phy_num_uars;
 809         u32             max_sq_sg;
 810         u32             max_sq_inline;
 811         u32             max_rq_sg;
 812         u32             max_extend_sg;
 813         int             num_qps;
 814         int             reserved_qps;
 815         int             num_qpc_timer;
 816         int             num_cqc_timer;
 817         int             num_srqs;
 818         u32             max_wqes;
 819         u32             max_srq_wrs;
 820         u32             max_srq_sges;
 821         u32             max_sq_desc_sz;
 822         u32             max_rq_desc_sz;
 823         u32             max_srq_desc_sz;
 824         int             max_qp_init_rdma;
 825         int             max_qp_dest_rdma;
 826         int             num_cqs;
 827         u32             max_cqes;
 828         u32             min_cqes;
 829         u32             min_wqes;
 830         int             reserved_cqs;
 831         int             reserved_srqs;
 832         int             num_aeq_vectors;
 833         int             num_comp_vectors;
 834         int             num_other_vectors;
 835         int             num_mtpts;
 836         u32             num_mtt_segs;
 837         u32             num_cqe_segs;
 838         u32             num_srqwqe_segs;
 839         u32             num_idx_segs;
 840         int             reserved_mrws;
 841         int             reserved_uars;
 842         int             num_pds;
 843         int             reserved_pds;
 844         u32             mtt_entry_sz;
 845         u32             cq_entry_sz;
 846         u32             page_size_cap;
 847         u32             reserved_lkey;
 848         int             mtpt_entry_sz;
 849         int             qpc_entry_sz;
 850         int             irrl_entry_sz;
 851         int             trrl_entry_sz;
 852         int             cqc_entry_sz;
 853         int             sccc_entry_sz;
 854         int             qpc_timer_entry_sz;
 855         int             cqc_timer_entry_sz;
 856         int             srqc_entry_sz;
 857         int             idx_entry_sz;
 858         u32             pbl_ba_pg_sz;
 859         u32             pbl_buf_pg_sz;
 860         u32             pbl_hop_num;
 861         int             aeqe_depth;
 862         int             ceqe_depth;
 863         enum ib_mtu     max_mtu;
 864         u32             qpc_bt_num;
 865         u32             qpc_timer_bt_num;
 866         u32             srqc_bt_num;
 867         u32             cqc_bt_num;
 868         u32             cqc_timer_bt_num;
 869         u32             mpt_bt_num;
 870         u32             sccc_bt_num;
 871         u32             qpc_ba_pg_sz;
 872         u32             qpc_buf_pg_sz;
 873         u32             qpc_hop_num;
 874         u32             srqc_ba_pg_sz;
 875         u32             srqc_buf_pg_sz;
 876         u32             srqc_hop_num;
 877         u32             cqc_ba_pg_sz;
 878         u32             cqc_buf_pg_sz;
 879         u32             cqc_hop_num;
 880         u32             mpt_ba_pg_sz;
 881         u32             mpt_buf_pg_sz;
 882         u32             mpt_hop_num;
 883         u32             mtt_ba_pg_sz;
 884         u32             mtt_buf_pg_sz;
 885         u32             mtt_hop_num;
 886         u32             wqe_sq_hop_num;
 887         u32             wqe_sge_hop_num;
 888         u32             wqe_rq_hop_num;
 889         u32             sccc_ba_pg_sz;
 890         u32             sccc_buf_pg_sz;
 891         u32             sccc_hop_num;
 892         u32             qpc_timer_ba_pg_sz;
 893         u32             qpc_timer_buf_pg_sz;
 894         u32             qpc_timer_hop_num;
 895         u32             cqc_timer_ba_pg_sz;
 896         u32             cqc_timer_buf_pg_sz;
 897         u32             cqc_timer_hop_num;
 898         u32             cqe_ba_pg_sz;   /* page_size = 4K*(2^cqe_ba_pg_sz) */
 899         u32             cqe_buf_pg_sz;
 900         u32             cqe_hop_num;
 901         u32             srqwqe_ba_pg_sz;
 902         u32             srqwqe_buf_pg_sz;
 903         u32             srqwqe_hop_num;
 904         u32             idx_ba_pg_sz;
 905         u32             idx_buf_pg_sz;
 906         u32             idx_hop_num;
 907         u32             eqe_ba_pg_sz;
 908         u32             eqe_buf_pg_sz;
 909         u32             eqe_hop_num;
 910         u32             sl_num;
 911         u32             tsq_buf_pg_sz;
 912         u32             tpq_buf_pg_sz;
 913         u32             chunk_sz;       /* chunk size in non multihop mode */
 914         u64             flags;
 915         u16             default_ceq_max_cnt;
 916         u16             default_ceq_period;
 917         u16             default_aeq_max_cnt;
 918         u16             default_aeq_period;
 919         u16             default_aeq_arm_st;
 920         u16             default_ceq_arm_st;
 921 };
 922
 923 struct hns_roce_dfx_hw {
 924         int (*query_cqc_info)(struct hns_roce_dev *hr_dev, u32 cqn,
 925                               int *buffer);
 926 };
 927
 928 enum hns_roce_device_state {
 929         HNS_ROCE_DEVICE_STATE_INITED,
 930         HNS_ROCE_DEVICE_STATE_RST_DOWN,
 931         HNS_ROCE_DEVICE_STATE_UNINIT,
 932 };
 933
 934 struct hns_roce_hw {
 935         int (*reset)(struct hns_roce_dev *hr_dev, bool enable);
 936         int (*cmq_init)(struct hns_roce_dev *hr_dev);
 937         void (*cmq_exit)(struct hns_roce_dev *hr_dev);
 938         int (*hw_profile)(struct hns_roce_dev *hr_dev);
 939         int (*hw_init)(struct hns_roce_dev *hr_dev);
 940         void (*hw_exit)(struct hns_roce_dev *hr_dev);
 941         int (*post_mbox)(struct hns_roce_dev *hr_dev, u64 in_param,
 942                          u64 out_param, u32 in_modifier, u8 op_modifier, u16 op,
 943                          u16 token, int event);
 944         int (*chk_mbox)(struct hns_roce_dev *hr_dev, unsigned long timeout);
 945         int (*rst_prc_mbox)(struct hns_roce_dev *hr_dev);
 946         int (*set_gid)(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
 947                        const union ib_gid *gid, const struct ib_gid_attr *attr);
 948         int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, u8 *addr);
 949         void (*set_mtu)(struct hns_roce_dev *hr_dev, u8 phy_port,
 950                         enum ib_mtu mtu);
 951         int (*write_mtpt)(void *mb_buf, struct hns_roce_mr *mr,
 952                           unsigned long mtpt_idx);
 953         int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev,
 954                                 struct hns_roce_mr *mr, int flags, u32 pdn,
 955                                 int mr_access_flags, u64 iova, u64 size,
 956                                 void *mb_buf);
 957         int (*frmr_write_mtpt)(void *mb_buf, struct hns_roce_mr *mr);
 958         int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw);
 959         void (*write_cqc)(struct hns_roce_dev *hr_dev,
 960                           struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts,
 961                           dma_addr_t dma_handle);
 962         int (*set_hem)(struct hns_roce_dev *hr_dev,
 963                        struct hns_roce_hem_table *table, int obj, int step_idx);
 964         int (*clear_hem)(struct hns_roce_dev *hr_dev,
 965                          struct hns_roce_hem_table *table, int obj,
 966                          int step_idx);
 967         int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
 968                         int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
 969         int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
 970                          int attr_mask, enum ib_qp_state cur_state,
 971                          enum ib_qp_state new_state);
 972         int (*destroy_qp)(struct ib_qp *ibqp, struct ib_udata *udata);
 973         int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev,
 974                          struct hns_roce_qp *hr_qp);
 975         int (*post_send)(struct ib_qp *ibqp, const struct ib_send_wr *wr,
 976                          const struct ib_send_wr **bad_wr);
 977         int (*post_recv)(struct ib_qp *qp, const struct ib_recv_wr *recv_wr,
 978                          const struct ib_recv_wr **bad_recv_wr);
 979         int (*req_notify_cq)(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
 980         int (*poll_cq)(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
 981         int (*dereg_mr)(struct hns_roce_dev *hr_dev, struct hns_roce_mr *mr,
 982                         struct ib_udata *udata);
 983         void (*destroy_cq)(struct ib_cq *ibcq, struct ib_udata *udata);
 984         int (*modify_cq)(struct ib_cq *cq, u16 cq_count, u16 cq_period);
 985         int (*init_eq)(struct hns_roce_dev *hr_dev);
 986         void (*cleanup_eq)(struct hns_roce_dev *hr_dev);
 987         void (*write_srqc)(struct hns_roce_dev *hr_dev,
 988                            struct hns_roce_srq *srq, u32 pdn, u16 xrcd, u32 cqn,
 989                            void *mb_buf, u64 *mtts_wqe, u64 *mtts_idx,
 990                            dma_addr_t dma_handle_wqe,
 991                            dma_addr_t dma_handle_idx);
 992         int (*modify_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
 993                        enum ib_srq_attr_mask srq_attr_mask,
 994                        struct ib_udata *udata);
 995         int (*query_srq)(struct ib_srq *ibsrq, struct ib_srq_attr *attr);
 996         int (*post_srq_recv)(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
 997                              const struct ib_recv_wr **bad_wr);
 998         const struct ib_device_ops *hns_roce_dev_ops;
 999         const struct ib_device_ops *hns_roce_dev_srq_ops;
1000 };
1001
1002 struct hns_roce_dev {
1003         struct ib_device        ib_dev;
1004         struct platform_device  *pdev;
1005         struct pci_dev          *pci_dev;
1006         struct device           *dev;
1007         struct hns_roce_uar     priv_uar;
1008         const char              *irq_names[HNS_ROCE_MAX_IRQ_NUM];
1009         spinlock_t              sm_lock;
1010         spinlock_t              bt_cmd_lock;
1011         bool                    active;
1012         bool                    is_reset;
1013         bool                    dis_db;
1014         unsigned long           reset_cnt;
1015         struct hns_roce_ib_iboe iboe;
1016         enum hns_roce_device_state state;
1017         struct list_head        qp_list; /* list of all qps on this dev */
1018         spinlock_t              qp_list_lock; /* protect qp_list */
1019
1020         struct list_head        pgdir_list;
1021         struct mutex            pgdir_mutex;
1022         int                     irq[HNS_ROCE_MAX_IRQ_NUM];
1023         u8 __iomem              *reg_base;
1024         struct hns_roce_caps    caps;
1025         struct xarray           qp_table_xa;
1026
1027         unsigned char   dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
1028         u64                     sys_image_guid;
1029         u32                     vendor_id;
1030         u32                     vendor_part_id;
1031         u32                     hw_rev;
1032         void __iomem            *priv_addr;
1033
1034         struct hns_roce_cmdq    cmd;
1035         struct hns_roce_bitmap    pd_bitmap;
1036         struct hns_roce_uar_table uar_table;
1037         struct hns_roce_mr_table  mr_table;
1038         struct hns_roce_cq_table  cq_table;
1039         struct hns_roce_srq_table srq_table;
1040         struct hns_roce_qp_table  qp_table;
1041         struct hns_roce_eq_table  eq_table;
1042         struct hns_roce_hem_table  qpc_timer_table;
1043         struct hns_roce_hem_table  cqc_timer_table;
1044
1045         int                     cmd_mod;
1046         int                     loop_idc;
1047         u32                     sdb_offset;
1048         u32                     odb_offset;
1049         dma_addr_t              tptr_dma_addr;  /* only for hw v1 */
1050         u32                     tptr_size;      /* only for hw v1 */
1051         const struct hns_roce_hw *hw;
1052         void                    *priv;
1053         struct workqueue_struct *irq_workq;
1054         const struct hns_roce_dfx_hw *dfx;
1055 };
1056
1057 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev)
1058 {
1059         return container_of(ib_dev, struct hns_roce_dev, ib_dev);
1060 }
1061
1062 static inline struct hns_roce_ucontext
1063                         *to_hr_ucontext(struct ib_ucontext *ibucontext)
1064 {
1065         return container_of(ibucontext, struct hns_roce_ucontext, ibucontext);
1066 }
1067
1068 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd)
1069 {
1070         return container_of(ibpd, struct hns_roce_pd, ibpd);
1071 }
1072
1073 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah)
1074 {
1075         return container_of(ibah, struct hns_roce_ah, ibah);
1076 }
1077
1078 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr)
1079 {
1080         return container_of(ibmr, struct hns_roce_mr, ibmr);
1081 }
1082
1083 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw)
1084 {
1085         return container_of(ibmw, struct hns_roce_mw, ibmw);
1086 }
1087
1088 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp)
1089 {
1090         return container_of(ibqp, struct hns_roce_qp, ibqp);
1091 }
1092
1093 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq)
1094 {
1095         return container_of(ib_cq, struct hns_roce_cq, ib_cq);
1096 }
1097
1098 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq)
1099 {
1100         return container_of(ibsrq, struct hns_roce_srq, ibsrq);
1101 }
1102
1103 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest)
1104 {
1105         __raw_writeq(*(u64 *) val, dest);
1106 }
1107
1108 static inline struct hns_roce_qp
1109         *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn)
1110 {
1111         return xa_load(&hr_dev->qp_table_xa, qpn & (hr_dev->caps.num_qps - 1));
1112 }
1113
1114 static inline bool hns_roce_buf_is_direct(struct hns_roce_buf *buf)
1115 {
1116         if (buf->page_list)
1117                 return false;
1118
1119         return true;
1120 }
1121
1122 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, int offset)
1123 {
1124         if (hns_roce_buf_is_direct(buf))
1125                 return (char *)(buf->direct.buf) + (offset & (buf->size - 1));
1126
1127         return (char *)(buf->page_list[offset >> buf->page_shift].buf) +
1128                (offset & ((1 << buf->page_shift) - 1));
1129 }
1130
1131 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, int idx)
1132 {
1133         if (hns_roce_buf_is_direct(buf))
1134                 return buf->direct.map + ((dma_addr_t)idx << buf->page_shift);
1135         else
1136                 return buf->page_list[idx].map;
1137 }
1138
1139 static inline u64 to_hr_hw_page_addr(u64 addr)
1140 {
1141         return addr >> PAGE_ADDR_SHIFT;
1142 }
1143
1144 static inline u32 to_hr_hw_page_shift(u32 page_shift)
1145 {
1146         return page_shift - PAGE_ADDR_SHIFT;
1147 }
1148
1149 int hns_roce_init_uar_table(struct hns_roce_dev *dev);
1150 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1151 void hns_roce_uar_free(struct hns_roce_dev *dev, struct hns_roce_uar *uar);
1152 void hns_roce_cleanup_uar_table(struct hns_roce_dev *dev);
1153
1154 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev);
1155 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev);
1156 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status,
1157                         u64 out_param);
1158 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev);
1159 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev);
1160
1161 int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift,
1162                       struct hns_roce_mtt *mtt);
1163 void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev,
1164                           struct hns_roce_mtt *mtt);
1165 int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev,
1166                            struct hns_roce_mtt *mtt, struct hns_roce_buf *buf);
1167
1168 void hns_roce_mtr_init(struct hns_roce_mtr *mtr, int bt_pg_shift,
1169                        int buf_pg_shift);
1170 int hns_roce_mtr_attach(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1171                         dma_addr_t **bufs, struct hns_roce_buf_region *regions,
1172                         int region_cnt);
1173 void hns_roce_mtr_cleanup(struct hns_roce_dev *hr_dev,
1174                           struct hns_roce_mtr *mtr);
1175
1176 /* hns roce hw need current block and next block addr from mtt */
1177 #define MTT_MIN_COUNT    2
1178 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1179                       int offset, u64 *mtt_buf, int mtt_max, u64 *base_addr);
1180 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1181                         struct hns_roce_buf_attr *buf_attr, int page_shift,
1182                         struct ib_udata *udata, unsigned long user_addr);
1183 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev,
1184                           struct hns_roce_mtr *mtr);
1185 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr,
1186                      struct hns_roce_buf_region *regions, int region_cnt,
1187                      dma_addr_t *pages, int page_cnt);
1188
1189 int hns_roce_init_pd_table(struct hns_roce_dev *hr_dev);
1190 int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev);
1191 int hns_roce_init_cq_table(struct hns_roce_dev *hr_dev);
1192 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev);
1193 int hns_roce_init_srq_table(struct hns_roce_dev *hr_dev);
1194
1195 void hns_roce_cleanup_pd_table(struct hns_roce_dev *hr_dev);
1196 void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev);
1197 void hns_roce_cleanup_eq_table(struct hns_roce_dev *hr_dev);
1198 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev);
1199 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev);
1200 void hns_roce_cleanup_srq_table(struct hns_roce_dev *hr_dev);
1201
1202 int hns_roce_bitmap_alloc(struct hns_roce_bitmap *bitmap, unsigned long *obj);
1203 void hns_roce_bitmap_free(struct hns_roce_bitmap *bitmap, unsigned long obj,
1204                          int rr);
1205 int hns_roce_bitmap_init(struct hns_roce_bitmap *bitmap, u32 num, u32 mask,
1206                          u32 reserved_bot, u32 resetrved_top);
1207 void hns_roce_bitmap_cleanup(struct hns_roce_bitmap *bitmap);
1208 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev);
1209 int hns_roce_bitmap_alloc_range(struct hns_roce_bitmap *bitmap, int cnt,
1210                                 int align, unsigned long *obj);
1211 void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
1212                                 unsigned long obj, int cnt,
1213                                 int rr);
1214
1215 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_attr *ah_attr,
1216                        u32 flags, struct ib_udata *udata);
1217 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1218 void hns_roce_destroy_ah(struct ib_ah *ah, u32 flags);
1219
1220 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1221 void hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata);
1222
1223 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc);
1224 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1225                                    u64 virt_addr, int access_flags,
1226                                    struct ib_udata *udata);
1227 int hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, u64 length,
1228                            u64 virt_addr, int mr_access_flags, struct ib_pd *pd,
1229                            struct ib_udata *udata);
1230 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1231                                 u32 max_num_sg, struct ib_udata *udata);
1232 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1233                        unsigned int *sg_offset);
1234 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1235 int hns_roce_hw_destroy_mpt(struct hns_roce_dev *hr_dev,
1236                             struct hns_roce_cmd_mailbox *mailbox,
1237                             unsigned long mpt_index);
1238 unsigned long key_to_hw_index(u32 key);
1239
1240 struct ib_mw *hns_roce_alloc_mw(struct ib_pd *pd, enum ib_mw_type,
1241                                 struct ib_udata *udata);
1242 int hns_roce_dealloc_mw(struct ib_mw *ibmw);
1243
1244 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf);
1245 int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
1246                        struct hns_roce_buf *buf, u32 page_shift);
1247
1248 int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev,
1249                                struct hns_roce_mtt *mtt, struct ib_umem *umem);
1250
1251 void hns_roce_init_buf_region(struct hns_roce_buf_region *region, int hopnum,
1252                               int offset, int buf_cnt);
1253 int hns_roce_alloc_buf_list(struct hns_roce_buf_region *regions,
1254                             dma_addr_t **bufs, int count);
1255 void hns_roce_free_buf_list(dma_addr_t **bufs, int count);
1256
1257 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1258                            int buf_cnt, int start, struct hns_roce_buf *buf);
1259 int hns_roce_get_umem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs,
1260                            int buf_cnt, int start, struct ib_umem *umem,
1261                            int page_shift);
1262
1263 int hns_roce_create_srq(struct ib_srq *srq,
1264                         struct ib_srq_init_attr *srq_init_attr,
1265                         struct ib_udata *udata);
1266 int hns_roce_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr,
1267                         enum ib_srq_attr_mask srq_attr_mask,
1268                         struct ib_udata *udata);
1269 void hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata);
1270
1271 struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
1272                                  struct ib_qp_init_attr *init_attr,
1273                                  struct ib_udata *udata);
1274 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1275                        int attr_mask, struct ib_udata *udata);
1276 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1277 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
1278 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, int n);
1279 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, int n);
1280 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
1281                           struct ib_cq *ib_cq);
1282 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state);
1283 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq,
1284                        struct hns_roce_cq *recv_cq);
1285 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1286                          struct hns_roce_cq *recv_cq);
1287 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp);
1288 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp,
1289                          struct ib_udata *udata);
1290 __be32 send_ieth(const struct ib_send_wr *wr);
1291 int to_hr_qp_type(int qp_type);
1292
1293 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr,
1294                        struct ib_udata *udata);
1295
1296 void hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata);
1297 void hns_roce_free_cqc(struct hns_roce_dev *hr_dev, struct hns_roce_cq *hr_cq);
1298
1299 int hns_roce_db_map_user(struct hns_roce_ucontext *context,
1300                          struct ib_udata *udata, unsigned long virt,
1301                          struct hns_roce_db *db);
1302 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context,
1303                             struct hns_roce_db *db);
1304 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db,
1305                       int order);
1306 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db);
1307
1308 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn);
1309 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type);
1310 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type);
1311 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type);
1312 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index);
1313 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev);
1314 int hns_roce_init(struct hns_roce_dev *hr_dev);
1315 void hns_roce_exit(struct hns_roce_dev *hr_dev);
1316
1317 int hns_roce_fill_res_entry(struct sk_buff *msg,
1318                             struct rdma_restrack_entry *res);
1319 #endif /* _HNS_ROCE_DEVICE_H */