2 * Copyright(c) 2015 - 2017 Intel Corporation.
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
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10 * it under the terms of version 2 of the GNU General Public License as
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48 #include <linux/pci.h>
50 #include <linux/delay.h>
51 #include <linux/vmalloc.h>
52 #include <linux/aer.h>
53 #include <linux/module.h>
56 #include "chip_registers.h"
59 /* link speed vector for Gen3 speed - not in Linux headers */
60 #define GEN1_SPEED_VECTOR 0x1
61 #define GEN2_SPEED_VECTOR 0x2
62 #define GEN3_SPEED_VECTOR 0x3
65 * This file contains PCIe utility routines.
69 * Code to adjust PCIe capabilities.
71 static void tune_pcie_caps(struct hfi1_devdata *);
74 * Do all the common PCIe setup and initialization.
75 * devdata is not yet allocated, and is not allocated until after this
76 * routine returns success. Therefore dd_dev_err() can't be used for error
79 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent)
83 ret = pci_enable_device(pdev);
86 * This can happen (in theory) iff:
87 * We did a chip reset, and then failed to reprogram the
88 * BAR, or the chip reset due to an internal error. We then
89 * unloaded the driver and reloaded it.
91 * Both reset cases set the BAR back to initial state. For
92 * the latter case, the AER sticky error bit at offset 0x718
93 * should be set, but the Linux kernel doesn't yet know
94 * about that, it appears. If the original BAR was retained
95 * in the kernel data structures, this may be OK.
97 hfi1_early_err(&pdev->dev, "pci enable failed: error %d\n",
102 ret = pci_request_regions(pdev, DRIVER_NAME);
104 hfi1_early_err(&pdev->dev,
105 "pci_request_regions fails: err %d\n", -ret);
109 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
112 * If the 64 bit setup fails, try 32 bit. Some systems
113 * do not setup 64 bit maps on systems with 2GB or less
116 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
118 hfi1_early_err(&pdev->dev,
119 "Unable to set DMA mask: %d\n", ret);
122 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
124 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
127 hfi1_early_err(&pdev->dev,
128 "Unable to set DMA consistent mask: %d\n", ret);
132 pci_set_master(pdev);
133 (void)pci_enable_pcie_error_reporting(pdev);
137 hfi1_pcie_cleanup(pdev);
143 * Clean what was done in hfi1_pcie_init()
145 void hfi1_pcie_cleanup(struct pci_dev *pdev)
147 pci_disable_device(pdev);
149 * Release regions should be called after the disable. OK to
150 * call if request regions has not been called or failed.
152 pci_release_regions(pdev);
156 * Do remaining PCIe setup, once dd is allocated, and save away
157 * fields required to re-initialize after a chip reset, or for
158 * various other purposes
160 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev)
163 resource_size_t addr;
166 addr = pci_resource_start(pdev, 0);
167 len = pci_resource_len(pdev, 0);
170 * The TXE PIO buffers are at the tail end of the chip space.
171 * Cut them off and map them separately.
174 /* sanity check vs expectations */
175 if (len != TXE_PIO_SEND + TXE_PIO_SIZE) {
176 dd_dev_err(dd, "chip PIO range does not match\n");
180 dd->kregbase1 = ioremap_nocache(addr, RCV_ARRAY);
181 if (!dd->kregbase1) {
182 dd_dev_err(dd, "UC mapping of kregbase1 failed\n");
185 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY);
186 dd->chip_rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT);
187 dd_dev_info(dd, "RcvArray count: %u\n", dd->chip_rcv_array_count);
188 dd->base2_start = RCV_ARRAY + dd->chip_rcv_array_count * 8;
190 dd->kregbase2 = ioremap_nocache(
191 addr + dd->base2_start,
192 TXE_PIO_SEND - dd->base2_start);
193 if (!dd->kregbase2) {
194 dd_dev_err(dd, "UC mapping of kregbase2 failed\n");
197 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2,
198 TXE_PIO_SEND - dd->base2_start);
200 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE);
202 dd_dev_err(dd, "WC mapping of send buffers failed\n");
205 dd_dev_info(dd, "WC piobase: %p\n for %x", dd->piobase, TXE_PIO_SIZE);
207 dd->physaddr = addr; /* used for io_remap, etc. */
210 * Map the chip's RcvArray as write-combining to allow us
211 * to write an entire cacheline worth of entries in one shot.
213 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY,
214 dd->chip_rcv_array_count * 8);
215 if (!dd->rcvarray_wc) {
216 dd_dev_err(dd, "WC mapping of receive array failed\n");
219 dd_dev_info(dd, "WC RcvArray: %p for %x\n",
220 dd->rcvarray_wc, dd->chip_rcv_array_count * 8);
222 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */
226 hfi1_pcie_ddcleanup(dd);
231 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior
232 * to releasing the dd memory.
233 * Void because all of the core pcie cleanup functions are void.
235 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd)
237 dd->flags &= ~HFI1_PRESENT;
239 iounmap(dd->kregbase1);
240 dd->kregbase1 = NULL;
242 iounmap(dd->kregbase2);
243 dd->kregbase2 = NULL;
245 iounmap(dd->rcvarray_wc);
246 dd->rcvarray_wc = NULL;
248 iounmap(dd->piobase);
252 /* return the PCIe link speed from the given link status */
253 static u32 extract_speed(u16 linkstat)
257 switch (linkstat & PCI_EXP_LNKSTA_CLS) {
258 default: /* not defined, assume Gen1 */
259 case PCI_EXP_LNKSTA_CLS_2_5GB:
260 speed = 2500; /* Gen 1, 2.5GHz */
262 case PCI_EXP_LNKSTA_CLS_5_0GB:
263 speed = 5000; /* Gen 2, 5GHz */
265 case GEN3_SPEED_VECTOR:
266 speed = 8000; /* Gen 3, 8GHz */
272 /* return the PCIe link speed from the given link status */
273 static u32 extract_width(u16 linkstat)
275 return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
278 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */
279 static void update_lbus_info(struct hfi1_devdata *dd)
284 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
286 dd_dev_err(dd, "Unable to read from PCI config\n");
290 dd->lbus_width = extract_width(linkstat);
291 dd->lbus_speed = extract_speed(linkstat);
292 snprintf(dd->lbus_info, sizeof(dd->lbus_info),
293 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width);
297 * Read in the current PCIe link width and speed. Find if the link is
300 int pcie_speeds(struct hfi1_devdata *dd)
303 struct pci_dev *parent = dd->pcidev->bus->self;
306 if (!pci_is_pcie(dd->pcidev)) {
307 dd_dev_err(dd, "Can't find PCI Express capability!\n");
311 /* find if our max speed is Gen3 and parent supports Gen3 speeds */
312 dd->link_gen3_capable = 1;
314 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap);
316 dd_dev_err(dd, "Unable to read from PCI config\n");
320 if ((linkcap & PCI_EXP_LNKCAP_SLS) != GEN3_SPEED_VECTOR) {
322 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n",
323 linkcap & PCI_EXP_LNKCAP_SLS);
324 dd->link_gen3_capable = 0;
328 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed
330 if (parent && dd->pcidev->bus->max_bus_speed != PCIE_SPEED_8_0GT) {
331 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n");
332 dd->link_gen3_capable = 0;
335 /* obtain the link width and current speed */
336 update_lbus_info(dd);
338 dd_dev_info(dd, "%s\n", dd->lbus_info);
345 * - actual number of interrupts allocated or
346 * - 0 if fell back to INTx.
349 int request_msix(struct hfi1_devdata *dd, u32 msireq)
353 nvec = pci_alloc_irq_vectors(dd->pcidev, 1, msireq,
354 PCI_IRQ_MSIX | PCI_IRQ_LEGACY);
356 dd_dev_err(dd, "pci_alloc_irq_vectors() failed: %d\n", nvec);
362 /* check for legacy IRQ */
363 if (nvec == 1 && !dd->pcidev->msix_enabled)
369 /* restore command and BARs after a reset has wiped them out */
370 int restore_pci_variables(struct hfi1_devdata *dd)
374 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command);
378 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
383 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
388 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom);
392 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL,
397 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL,
402 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2,
407 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0);
411 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
412 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2,
420 dd_dev_err(dd, "Unable to write to PCI config\n");
424 /* Save BARs and command to rewrite after device reset */
425 int save_pci_variables(struct hfi1_devdata *dd)
429 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
434 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
439 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom);
443 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command);
447 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL,
452 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL,
457 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2,
462 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0);
466 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
467 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2,
475 dd_dev_err(dd, "Unable to read from PCI config\n");
480 * BIOS may not set PCIe bus-utilization parameters for best performance.
481 * Check and optionally adjust them to maximize our throughput.
483 static int hfi1_pcie_caps;
484 module_param_named(pcie_caps, hfi1_pcie_caps, int, S_IRUGO);
485 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
487 uint aspm_mode = ASPM_MODE_DISABLED;
488 module_param_named(aspm, aspm_mode, uint, S_IRUGO);
489 MODULE_PARM_DESC(aspm, "PCIe ASPM: 0: disable, 1: enable, 2: dynamic");
491 static void tune_pcie_caps(struct hfi1_devdata *dd)
493 struct pci_dev *parent;
494 u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
495 u16 rc_mrrs, ep_mrrs, max_mrrs, ectl;
499 * Turn on extended tags in DevCtl in case the BIOS has turned it off
500 * to improve WFR SDMA bandwidth
502 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl);
503 if ((!ret) && !(ectl & PCI_EXP_DEVCTL_EXT_TAG)) {
504 dd_dev_info(dd, "Enabling PCIe extended tags\n");
505 ectl |= PCI_EXP_DEVCTL_EXT_TAG;
506 ret = pcie_capability_write_word(dd->pcidev,
507 PCI_EXP_DEVCTL, ectl);
509 dd_dev_info(dd, "Unable to write to PCI config\n");
511 /* Find out supported and configured values for parent (root) */
512 parent = dd->pcidev->bus->self;
514 * The driver cannot perform the tuning if it does not have
515 * access to the upstream component.
518 dd_dev_info(dd, "Parent not found\n");
521 if (!pci_is_root_bus(parent->bus)) {
522 dd_dev_info(dd, "Parent not root\n");
525 if (!pci_is_pcie(parent)) {
526 dd_dev_info(dd, "Parent is not PCI Express capable\n");
529 if (!pci_is_pcie(dd->pcidev)) {
530 dd_dev_info(dd, "PCI device is not PCI Express capable\n");
533 rc_mpss = parent->pcie_mpss;
534 rc_mps = ffs(pcie_get_mps(parent)) - 8;
535 /* Find out supported and configured values for endpoint (us) */
536 ep_mpss = dd->pcidev->pcie_mpss;
537 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
539 /* Find max payload supported by root, endpoint */
540 if (rc_mpss > ep_mpss)
543 /* If Supported greater than limit in module param, limit it */
544 if (rc_mpss > (hfi1_pcie_caps & 7))
545 rc_mpss = hfi1_pcie_caps & 7;
546 /* If less than (allowed, supported), bump root payload */
547 if (rc_mpss > rc_mps) {
549 pcie_set_mps(parent, 128 << rc_mps);
551 /* If less than (allowed, supported), bump endpoint payload */
552 if (rc_mpss > ep_mps) {
554 pcie_set_mps(dd->pcidev, 128 << ep_mps);
558 * Now the Read Request size.
559 * No field for max supported, but PCIe spec limits it to 4096,
560 * which is code '5' (log2(4096) - 7)
563 if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7))
564 max_mrrs = (hfi1_pcie_caps >> 4) & 7;
566 max_mrrs = 128 << max_mrrs;
567 rc_mrrs = pcie_get_readrq(parent);
568 ep_mrrs = pcie_get_readrq(dd->pcidev);
570 if (max_mrrs > rc_mrrs) {
572 pcie_set_readrq(parent, rc_mrrs);
574 if (max_mrrs > ep_mrrs) {
576 pcie_set_readrq(dd->pcidev, ep_mrrs);
580 /* End of PCIe capability tuning */
583 * From here through hfi1_pci_err_handler definition is invoked via
584 * PCI error infrastructure, registered via pci
586 static pci_ers_result_t
587 pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
589 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
590 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
593 case pci_channel_io_normal:
594 dd_dev_info(dd, "State Normal, ignoring\n");
597 case pci_channel_io_frozen:
598 dd_dev_info(dd, "State Frozen, requesting reset\n");
599 pci_disable_device(pdev);
600 ret = PCI_ERS_RESULT_NEED_RESET;
603 case pci_channel_io_perm_failure:
605 dd_dev_info(dd, "State Permanent Failure, disabling\n");
606 /* no more register accesses! */
607 dd->flags &= ~HFI1_PRESENT;
608 hfi1_disable_after_error(dd);
610 /* else early, or other problem */
611 ret = PCI_ERS_RESULT_DISCONNECT;
614 default: /* shouldn't happen */
615 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n",
622 static pci_ers_result_t
623 pci_mmio_enabled(struct pci_dev *pdev)
626 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
627 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
629 if (dd && dd->pport) {
630 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL);
632 ret = PCI_ERS_RESULT_NEED_RESET;
634 "HFI1 mmio_enabled function called, read wordscntr %llx, returning %d\n",
640 static pci_ers_result_t
641 pci_slot_reset(struct pci_dev *pdev)
643 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
645 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n");
646 return PCI_ERS_RESULT_CAN_RECOVER;
650 pci_resume(struct pci_dev *pdev)
652 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
654 dd_dev_info(dd, "HFI1 resume function called\n");
655 pci_cleanup_aer_uncorrect_error_status(pdev);
657 * Running jobs will fail, since it's asynchronous
658 * unlike sysfs-requested reset. Better than
661 hfi1_init(dd, 1); /* same as re-init after reset */
664 const struct pci_error_handlers hfi1_pci_err_handler = {
665 .error_detected = pci_error_detected,
666 .mmio_enabled = pci_mmio_enabled,
667 .slot_reset = pci_slot_reset,
668 .resume = pci_resume,
671 /*============================================================================*/
672 /* PCIe Gen3 support */
675 * This code is separated out because it is expected to be removed in the
676 * final shipping product. If not, then it will be revisited and items
677 * will be moved to more standard locations.
680 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */
681 #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */
682 #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */
683 #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */
685 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */
686 #define DL_ERR_NONE 0x0 /* no error */
687 #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */
688 /* or response data */
689 #define DL_ERR_DISABLED 0x2 /* hfi disabled */
690 #define DL_ERR_SECURITY 0x3 /* security check failed */
691 #define DL_ERR_SBUS 0x4 /* SBus status error */
692 #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/
694 /* gasket block secondary bus reset delay */
695 #define SBR_DELAY_US 200000 /* 200ms */
697 /* mask for PCIe capability register lnkctl2 target link speed */
698 #define LNKCTL2_TARGET_LINK_SPEED_MASK 0xf
700 static uint pcie_target = 3;
701 module_param(pcie_target, uint, S_IRUGO);
702 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)");
704 static uint pcie_force;
705 module_param(pcie_force, uint, S_IRUGO);
706 MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed");
708 static uint pcie_retry = 5;
709 module_param(pcie_retry, uint, S_IRUGO);
710 MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed");
712 #define UNSET_PSET 255
713 #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */
714 #define DEFAULT_MCP_PSET 6 /* MCP HFI */
715 static uint pcie_pset = UNSET_PSET;
716 module_param(pcie_pset, uint, S_IRUGO);
717 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10");
719 static uint pcie_ctle = 3; /* discrete on, integrated on */
720 module_param(pcie_ctle, uint, S_IRUGO);
721 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off");
723 /* equalization columns */
728 /* discrete silicon preliminary equalization values */
729 static const u8 discrete_preliminary_eq[11][3] = {
731 { 0x00, 0x00, 0x12 }, /* p0 */
732 { 0x00, 0x00, 0x0c }, /* p1 */
733 { 0x00, 0x00, 0x0f }, /* p2 */
734 { 0x00, 0x00, 0x09 }, /* p3 */
735 { 0x00, 0x00, 0x00 }, /* p4 */
736 { 0x06, 0x00, 0x00 }, /* p5 */
737 { 0x09, 0x00, 0x00 }, /* p6 */
738 { 0x06, 0x00, 0x0f }, /* p7 */
739 { 0x09, 0x00, 0x09 }, /* p8 */
740 { 0x0c, 0x00, 0x00 }, /* p9 */
741 { 0x00, 0x00, 0x18 }, /* p10 */
744 /* integrated silicon preliminary equalization values */
745 static const u8 integrated_preliminary_eq[11][3] = {
747 { 0x00, 0x1e, 0x07 }, /* p0 */
748 { 0x00, 0x1e, 0x05 }, /* p1 */
749 { 0x00, 0x1e, 0x06 }, /* p2 */
750 { 0x00, 0x1e, 0x04 }, /* p3 */
751 { 0x00, 0x1e, 0x00 }, /* p4 */
752 { 0x03, 0x1e, 0x00 }, /* p5 */
753 { 0x04, 0x1e, 0x00 }, /* p6 */
754 { 0x03, 0x1e, 0x06 }, /* p7 */
755 { 0x03, 0x1e, 0x04 }, /* p8 */
756 { 0x05, 0x1e, 0x00 }, /* p9 */
757 { 0x00, 0x1e, 0x0a }, /* p10 */
760 static const u8 discrete_ctle_tunings[11][4] = {
762 { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */
763 { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */
764 { 0x50, 0x09, 0x06, 0x06 }, /* p2 */
765 { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */
766 { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */
767 { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */
768 { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */
769 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */
770 { 0x48, 0x09, 0x06, 0x06 }, /* p8 */
771 { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */
772 { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */
775 static const u8 integrated_ctle_tunings[11][4] = {
777 { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */
778 { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */
779 { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */
780 { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */
781 { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */
782 { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */
783 { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */
784 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */
785 { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */
786 { 0x38, 0x09, 0x06, 0x06 }, /* p9 */
787 { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */
790 /* helper to format the value to write to hardware */
791 #define eq_value(pre, curr, post) \
793 PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \
794 | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \
795 | (((u32)(post)) << \
796 PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT))
799 * Load the given EQ preset table into the PCIe hardware.
801 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs,
804 struct pci_dev *pdev = dd->pcidev;
808 u8 c_minus1, c0, c_plus1;
811 for (i = 0; i < 11; i++) {
813 pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i);
814 /* write the value */
815 c_minus1 = eq[i][PREC] / div;
816 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div);
817 c_plus1 = eq[i][POST] / div;
818 pci_write_config_dword(pdev, PCIE_CFG_REG_PL102,
819 eq_value(c_minus1, c0, c_plus1));
820 /* check if these coefficients violate EQ rules */
821 ret = pci_read_config_dword(dd->pcidev,
822 PCIE_CFG_REG_PL105, &violation);
824 dd_dev_err(dd, "Unable to read from PCI config\n");
830 & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){
831 if (hit_error == 0) {
833 "Gen3 EQ Table Coefficient rule violations\n");
834 dd_dev_err(dd, " prec attn post\n");
836 dd_dev_err(dd, " p%02d: %02x %02x %02x\n",
837 i, (u32)eq[i][0], (u32)eq[i][1],
839 dd_dev_err(dd, " %02x %02x %02x\n",
840 (u32)c_minus1, (u32)c0, (u32)c_plus1);
850 * Steps to be done after the PCIe firmware is downloaded and
851 * before the SBR for the Pcie Gen3.
852 * The SBus resource is already being held.
854 static void pcie_post_steps(struct hfi1_devdata *dd)
858 set_sbus_fast_mode(dd);
860 * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1.
861 * This avoids a spurious framing error that can otherwise be
862 * generated by the MAC layer.
864 * Use individual addresses since no broadcast is set up.
866 for (i = 0; i < NUM_PCIE_SERDES; i++) {
867 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i],
868 0x03, WRITE_SBUS_RECEIVER, 0x00022132);
871 clear_sbus_fast_mode(dd);
875 * Trigger a secondary bus reset (SBR) on ourselves using our parent.
877 * Based on pci_parent_bus_reset() which is not exported by the
880 static int trigger_sbr(struct hfi1_devdata *dd)
882 struct pci_dev *dev = dd->pcidev;
883 struct pci_dev *pdev;
886 if (!dev->bus->self) {
887 dd_dev_err(dd, "%s: no parent device\n", __func__);
891 /* should not be anyone else on the bus */
892 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
895 "%s: another device is on the same bus\n",
901 * A secondary bus reset (SBR) issues a hot reset to our device.
902 * The following routine does a 1s wait after the reset is dropped
903 * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 -
904 * Conventional Reset, paragraph 3, line 35 also says that a 1s
905 * delay after a reset is required. Per spec requirements,
906 * the link is either working or not after that point.
908 pci_reset_bridge_secondary_bus(dev->bus->self);
914 * Write the given gasket interrupt register.
916 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index,
919 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8),
920 (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) |
921 ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT)));
925 * Tell the gasket logic how to react to the reset.
927 static void arm_gasket_logic(struct hfi1_devdata *dd)
931 reg = (((u64)1 << dd->hfi1_id) <<
932 ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) |
933 ((u64)pcie_serdes_broadcast[dd->hfi1_id] <<
934 ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT |
935 ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK |
936 ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) <<
937 ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT);
938 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg);
939 /* read back to push the write */
940 read_csr(dd, ASIC_PCIE_SD_HOST_CMD);
944 * CCE_PCIE_CTRL long name helpers
945 * We redefine these shorter macros to use in the code while leaving
946 * chip_registers.h to be autogenerated from the hardware spec.
948 #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK
949 #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT
950 #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK
951 #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT
952 #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT
953 #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT
954 #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK
955 #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT
956 #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK
957 #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT
960 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C).
962 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname)
970 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL);
973 * For Discrete, use full-swing.
974 * - PCIe TX defaults to full-swing.
975 * Leave this register as default.
976 * For Integrated, use half-swing
977 * - Copy xmt_margin and xmt_margin_oe
978 * from Gen1/Gen2 to Gen3.
980 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */
981 /* extract initial fields */
982 xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT)
983 & MARGIN_GEN1_GEN2_MASK;
984 xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT)
985 & MARGIN_G1_G2_OVERWRITE_MASK;
986 lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK;
987 lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT)
991 * For A0, EFUSE values are not set. Override with the
996 * xmt_margin and OverwiteEnabel should be the
997 * same for Gen1/Gen2 and Gen3
1000 xmt_margin_oe = 0x1;
1001 lane_delay = 0xF; /* Delay 240ns. */
1002 lane_bundle = 0x0; /* Set to 1 lane. */
1005 /* overwrite existing values */
1006 pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT)
1007 | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT)
1008 | (xmt_margin << MARGIN_SHIFT)
1009 | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT)
1010 | (lane_delay << LANE_DELAY_SHIFT)
1011 | (lane_bundle << LANE_BUNDLE_SHIFT);
1013 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl);
1016 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n",
1021 * Do all the steps needed to transition the PCIe link to Gen3 speed.
1023 int do_pcie_gen3_transition(struct hfi1_devdata *dd)
1025 struct pci_dev *parent = dd->pcidev->bus->self;
1031 int do_retry, retry_count = 0;
1034 uint pset = pcie_pset;
1035 u16 target_vector, target_speed;
1036 u16 lnkctl2, vendor;
1039 const u8 (*ctle_tunings)[4];
1040 uint static_ctle_mode;
1041 int return_error = 0;
1043 /* PCIe Gen3 is for the ASIC only */
1044 if (dd->icode != ICODE_RTL_SILICON)
1047 if (pcie_target == 1) { /* target Gen1 */
1048 target_vector = GEN1_SPEED_VECTOR;
1049 target_speed = 2500;
1050 } else if (pcie_target == 2) { /* target Gen2 */
1051 target_vector = GEN2_SPEED_VECTOR;
1052 target_speed = 5000;
1053 } else if (pcie_target == 3) { /* target Gen3 */
1054 target_vector = GEN3_SPEED_VECTOR;
1055 target_speed = 8000;
1057 /* off or invalid target - skip */
1058 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__);
1062 /* if already at target speed, done (unless forced) */
1063 if (dd->lbus_speed == target_speed) {
1064 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__,
1066 pcie_force ? "re-doing anyway" : "skipping");
1072 * The driver cannot do the transition if it has no access to the
1073 * upstream component
1076 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n",
1082 * Do the Gen3 transition. Steps are those of the PCIe Gen3
1086 /* step 1: pcie link working in gen1/gen2 */
1088 /* step 2: if either side is not capable of Gen3, done */
1089 if (pcie_target == 3 && !dd->link_gen3_capable) {
1090 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n");
1095 /* hold the SBus resource across the firmware download and SBR */
1096 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
1098 dd_dev_err(dd, "%s: unable to acquire SBus resource\n",
1103 /* make sure thermal polling is not causing interrupts */
1104 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN);
1106 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
1108 dd_dev_info(dd, "%s: Disabled therm polling\n",
1113 /* the SBus download will reset the spico for thermal */
1115 /* step 3: download SBus Master firmware */
1116 /* step 4: download PCIe Gen3 SerDes firmware */
1117 dd_dev_info(dd, "%s: downloading firmware\n", __func__);
1118 ret = load_pcie_firmware(dd);
1120 /* do not proceed if the firmware cannot be downloaded */
1125 /* step 5: set up device parameter settings */
1126 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__);
1129 * PcieCfgSpcie1 - Link Control 3
1130 * Leave at reset value. No need to set PerfEq - link equalization
1131 * will be performed automatically after the SBR when the target
1135 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */
1136 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff);
1138 /* step 5a: Set Synopsys Port Logic registers */
1141 * PcieCfgRegPl2 - Port Force Link
1143 * Set the low power field to 0x10 to avoid unnecessary power
1144 * management messages. All other fields are zero.
1146 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT;
1147 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32);
1150 * PcieCfgRegPl100 - Gen3 Control
1152 * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl
1153 * turn on PcieCfgRegPl100.EqEieosCnt
1154 * Everything else zero.
1156 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK;
1157 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32);
1160 * PcieCfgRegPl101 - Gen3 EQ FS and LF
1161 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping
1162 * PcieCfgRegPl103 - Gen3 EQ Preset Index
1163 * PcieCfgRegPl105 - Gen3 EQ Status
1165 * Give initial EQ settings.
1167 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */
1168 /* 1000mV, FS=24, LF = 8 */
1172 eq = discrete_preliminary_eq;
1173 default_pset = DEFAULT_DISCRETE_PSET;
1174 ctle_tunings = discrete_ctle_tunings;
1175 /* bit 0 - discrete on/off */
1176 static_ctle_mode = pcie_ctle & 0x1;
1178 /* 400mV, FS=29, LF = 9 */
1182 eq = integrated_preliminary_eq;
1183 default_pset = DEFAULT_MCP_PSET;
1184 ctle_tunings = integrated_ctle_tunings;
1185 /* bit 1 - integrated on/off */
1186 static_ctle_mode = (pcie_ctle >> 1) & 0x1;
1188 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101,
1190 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) |
1192 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT));
1193 ret = load_eq_table(dd, eq, fs, div);
1198 * PcieCfgRegPl106 - Gen3 EQ Control
1200 * Set Gen3EqPsetReqVec, leave other fields 0.
1202 if (pset == UNSET_PSET)
1203 pset = default_pset;
1204 if (pset > 10) { /* valid range is 0-10, inclusive */
1205 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n",
1206 __func__, pset, default_pset);
1207 pset = default_pset;
1209 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pset);
1210 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106,
1212 PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) |
1213 PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK |
1214 PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK);
1217 * step 5b: Do post firmware download steps via SBus
1219 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__);
1220 pcie_post_steps(dd);
1223 * step 5c: Program gasket interrupts
1225 /* set the Rx Bit Rate to REFCLK ratio */
1226 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050);
1227 /* disable pCal for PCIe Gen3 RX equalization */
1228 /* select adaptive or static CTLE */
1229 write_gasket_interrupt(dd, intnum++, 0x0026,
1230 0x5b01 | (static_ctle_mode << 3));
1232 * Enable iCal for PCIe Gen3 RX equalization, and set which
1233 * evaluation of RX_EQ_EVAL will launch the iCal procedure.
1235 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202);
1237 if (static_ctle_mode) {
1238 /* apply static CTLE tunings */
1239 u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw;
1241 pcie_dc = ctle_tunings[pset][0];
1242 pcie_lf = ctle_tunings[pset][1];
1243 pcie_hf = ctle_tunings[pset][2];
1244 pcie_bw = ctle_tunings[pset][3];
1245 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc);
1246 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf);
1247 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf);
1248 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw);
1251 /* terminate list */
1252 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000);
1255 * step 5d: program XMT margin
1257 write_xmt_margin(dd, __func__);
1260 * step 5e: disable active state power management (ASPM). It
1261 * will be enabled if required later
1263 dd_dev_info(dd, "%s: clearing ASPM\n", __func__);
1264 aspm_hw_disable_l1(dd);
1267 * step 5f: clear DirectSpeedChange
1268 * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the
1269 * change in the speed target from starting before we are ready.
1270 * This field defaults to 0 and we are not changing it, so nothing
1274 /* step 5g: Set target link speed */
1276 * Set target link speed to be target on both device and parent.
1277 * On setting the parent: Some system BIOSs "helpfully" set the
1278 * parent target speed to Gen2 to match the ASIC's initial speed.
1279 * We can set the target Gen3 because we have already checked
1280 * that it is Gen3 capable earlier.
1282 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__);
1283 ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2);
1285 dd_dev_err(dd, "Unable to read from PCI config\n");
1290 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
1292 /* only write to parent if target is not as high as ours */
1293 if ((lnkctl2 & LNKCTL2_TARGET_LINK_SPEED_MASK) < target_vector) {
1294 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK;
1295 lnkctl2 |= target_vector;
1296 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
1298 ret = pcie_capability_write_word(parent,
1299 PCI_EXP_LNKCTL2, lnkctl2);
1301 dd_dev_err(dd, "Unable to write to PCI config\n");
1306 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__);
1309 dd_dev_info(dd, "%s: setting target link speed\n", __func__);
1310 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2);
1312 dd_dev_err(dd, "Unable to read from PCI config\n");
1317 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
1319 lnkctl2 &= ~LNKCTL2_TARGET_LINK_SPEED_MASK;
1320 lnkctl2 |= target_vector;
1321 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
1323 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2);
1325 dd_dev_err(dd, "Unable to write to PCI config\n");
1330 /* step 5h: arm gasket logic */
1331 /* hold DC in reset across the SBR */
1332 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
1333 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */
1334 /* save firmware control across the SBR */
1335 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL);
1337 dd_dev_info(dd, "%s: arming gasket logic\n", __func__);
1338 arm_gasket_logic(dd);
1341 * step 6: quiesce PCIe link
1342 * The chip has already been reset, so there will be no traffic
1343 * from the chip. Linux has no easy way to enforce that it will
1344 * not try to access the device, so we just need to hope it doesn't
1345 * do it while we are doing the reset.
1349 * step 7: initiate the secondary bus reset (SBR)
1350 * step 8: hardware brings the links back up
1351 * step 9: wait for link speed transition to be complete
1353 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__);
1354 ret = trigger_sbr(dd);
1358 /* step 10: decide what to do next */
1360 /* check if we can read PCI space */
1361 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor);
1364 "%s: read of VendorID failed after SBR, err %d\n",
1369 if (vendor == 0xffff) {
1370 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__);
1376 /* restore PCI space registers we know were reset */
1377 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__);
1378 ret = restore_pci_variables(dd);
1380 dd_dev_err(dd, "%s: Could not restore PCI variables\n",
1386 /* restore firmware control */
1387 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl);
1390 * Check the gasket block status.
1392 * This is the first CSR read after the SBR. If the read returns
1393 * all 1s (fails), the link did not make it back.
1395 * Once we're sure we can read and write, clear the DC reset after
1396 * the SBR. Then check for any per-lane errors. Then look over
1399 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS);
1400 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg);
1401 if (reg == ~0ull) { /* PCIe read failed/timeout */
1402 dd_dev_err(dd, "SBR failed - unable to read from device\n");
1408 /* clear the DC reset */
1409 write_csr(dd, CCE_DC_CTRL, 0);
1411 /* Set the LED off */
1414 /* check for any per-lane errors */
1415 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32);
1417 dd_dev_err(dd, "Unable to read from PCI config\n");
1422 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32);
1424 /* extract status, look for our HFI */
1425 status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT)
1426 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK;
1427 if ((status & (1 << dd->hfi1_id)) == 0) {
1429 "%s: gasket status 0x%x, expecting 0x%x\n",
1430 __func__, status, 1 << dd->hfi1_id);
1436 err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT)
1437 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK;
1439 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err);
1444 /* update our link information cache */
1445 update_lbus_info(dd);
1446 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__,
1449 if (dd->lbus_speed != target_speed) { /* not target */
1451 do_retry = retry_count < pcie_retry;
1452 dd_dev_err(dd, "PCIe link speed did not switch to Gen%d%s\n",
1453 pcie_target, do_retry ? ", retrying" : "");
1456 msleep(100); /* allow time to settle */
1464 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
1466 dd_dev_info(dd, "%s: Re-enable therm polling\n",
1469 release_chip_resource(dd, CR_SBUS);
1471 /* return no error if it is OK to be at current speed */
1472 if (ret && !return_error) {
1473 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n");
1477 dd_dev_info(dd, "%s: done\n", __func__);