4 * Copyright(c) 2015-2017 Intel Corporation.
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
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50 #include <linux/interrupt.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/mutex.h>
54 #include <linux/list.h>
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/idr.h>
60 #include <linux/completion.h>
61 #include <linux/kref.h>
62 #include <linux/sched.h>
63 #include <linux/cdev.h>
64 #include <linux/delay.h>
65 #include <linux/kthread.h>
66 #include <linux/i2c.h>
67 #include <linux/i2c-algo-bit.h>
68 #include <rdma/ib_hdrs.h>
69 #include <rdma/opa_addr.h>
70 #include <linux/rhashtable.h>
71 #include <linux/netdevice.h>
72 #include <rdma/rdma_vt.h>
73 #include <rdma/opa_addr.h>
75 #include "chip_registers.h"
85 /* bumped 1 from s/w major version of TrueScale */
86 #define HFI1_CHIP_VERS_MAJ 3U
88 /* don't care about this except printing */
89 #define HFI1_CHIP_VERS_MIN 0U
91 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
92 #define HFI1_OUI 0x001175
93 #define HFI1_OUI_LSB 40
95 #define DROP_PACKET_OFF 0
96 #define DROP_PACKET_ON 1
98 #define NEIGHBOR_TYPE_HFI 0
99 #define NEIGHBOR_TYPE_SWITCH 1
101 extern unsigned long hfi1_cap_mask;
102 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
103 #define HFI1_CAP_UGET_MASK(mask, cap) \
104 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
105 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
106 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
107 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
108 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
109 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
111 /* Offline Disabled Reason is 4-bits */
112 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
115 * Control context is always 0 and handles the error packets.
116 * It also handles the VL15 and multicast packets.
118 #define HFI1_CTRL_CTXT 0
121 * Driver context will store software counters for each of the events
122 * associated with these status registers
124 #define NUM_CCE_ERR_STATUS_COUNTERS 41
125 #define NUM_RCV_ERR_STATUS_COUNTERS 64
126 #define NUM_MISC_ERR_STATUS_COUNTERS 13
127 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
128 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
129 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
130 #define NUM_SEND_ERR_STATUS_COUNTERS 3
131 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
132 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
135 * per driver stats, either not device nor port-specific, or
136 * summed over all of the devices and ports.
137 * They are described by name via ipathfs filesystem, so layout
138 * and number of elements can change without breaking compatibility.
139 * If members are added or deleted hfi1_statnames[] in debugfs.c must
142 struct hfi1_ib_stats {
143 __u64 sps_ints; /* number of interrupts handled */
144 __u64 sps_errints; /* number of error interrupts */
145 __u64 sps_txerrs; /* tx-related packet errors */
146 __u64 sps_rcverrs; /* non-crc rcv packet errors */
147 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
148 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
149 __u64 sps_ctxts; /* number of contexts currently open */
150 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
155 extern struct hfi1_ib_stats hfi1_stats;
156 extern const struct pci_error_handlers hfi1_pci_err_handler;
159 * First-cut criterion for "device is active" is
160 * two thousand dwords combined Tx, Rx traffic per
161 * 5-second interval. SMA packets are 64 dwords,
162 * and occur "a few per second", presumably each way.
164 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
167 * Below contains all data related to a single context (formerly called port).
170 struct hfi1_opcode_stats_perctx;
172 struct ctxt_eager_bufs {
173 ssize_t size; /* total size of eager buffers */
174 u32 count; /* size of buffers array */
175 u32 numbufs; /* number of buffers allocated */
176 u32 alloced; /* number of rcvarray entries used */
177 u32 rcvtid_size; /* size of each eager rcv tid */
178 u32 threshold; /* head update threshold */
179 struct eager_buffer {
191 struct list_head list;
195 struct hfi1_ctxtdata {
196 /* shadow the ctxt's RcvCtrl register */
198 /* rcvhdrq base, needs mmap before useful */
200 /* kernel virtual address where hdrqtail is updated */
201 volatile __le64 *rcvhdrtail_kvaddr;
202 /* when waiting for rcv or pioavail */
203 wait_queue_head_t wait;
204 /* rcvhdrq size (for freeing) */
206 /* number of rcvhdrq entries */
208 /* size of each of the rcvhdrq entries */
210 /* mmap of hdrq, must fit in 44 bits */
211 dma_addr_t rcvhdrq_dma;
212 dma_addr_t rcvhdrqtailaddr_dma;
213 struct ctxt_eager_bufs egrbufs;
214 /* this receive context's assigned PIO ACK send context */
215 struct send_context *sc;
217 /* dynamic receive available interrupt timeout */
218 u32 rcvavail_timeout;
219 /* Reference count the base context usage */
222 /* Device context index */
225 * non-zero if ctxt can be shared, and defines the maximum number of
226 * sub-contexts for this device context.
229 /* non-zero if ctxt is being shared. */
234 /* number of RcvArray groups for this context. */
235 u32 rcv_array_groups;
236 /* index of first eager TID entry. */
238 /* number of expected TID entries */
240 /* index of first expected TID entry. */
243 struct exp_tid_set tid_group_list;
244 struct exp_tid_set tid_used_list;
245 struct exp_tid_set tid_full_list;
247 /* lock protecting all Expected TID data */
248 struct mutex exp_lock;
249 /* per-context configuration flags */
251 /* per-context event flags for fileops/intr communication */
252 unsigned long event_flags;
253 /* total number of polled urgent packets */
255 /* saved total number of polled urgent packets for poll edge trigger */
257 /* same size as task_struct .comm[], command that opened context */
258 char comm[TASK_COMM_LEN];
259 /* so file ops can get at unit */
260 struct hfi1_devdata *dd;
261 /* so functions that need physical port can get it easily */
262 struct hfi1_pportdata *ppd;
263 /* associated msix interrupt */
265 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
266 void *subctxt_uregbase;
267 /* An array of pages for the eager receive buffers * N */
268 void *subctxt_rcvegrbuf;
269 /* An array of pages for the eager header queue entries * N */
270 void *subctxt_rcvhdr_base;
271 /* Bitmask of in use context(s) */
272 DECLARE_BITMAP(in_use_ctxts, HFI1_MAX_SHARED_CTXTS);
273 /* The version of the library which opened this ctxt */
275 /* Type of packets or conditions we want to poll for */
277 /* receive packet sequence counter */
279 /* ctxt rcvhdrq head offset */
281 /* QPs waiting for context processing */
282 struct list_head qp_wait_list;
283 /* interrupt handling */
284 u64 imask; /* clear interrupt mask */
285 int ireg; /* clear interrupt register */
286 unsigned numa_id; /* numa node of this context */
287 /* verbs rx_stats per rcd */
288 struct hfi1_opcode_stats_perctx *opstats;
290 /* Is ASPM interrupt supported for this context */
291 bool aspm_intr_supported;
292 /* ASPM state (enabled/disabled) for this context */
294 /* Timer for re-enabling ASPM if interrupt activity quietens down */
295 struct timer_list aspm_timer;
296 /* Lock to serialize between intr, timer intr and user threads */
297 spinlock_t aspm_lock;
298 /* Is ASPM processing enabled for this context (in intr context) */
299 bool aspm_intr_enable;
300 /* Last interrupt timestamp */
301 ktime_t aspm_ts_last_intr;
302 /* Last timestamp at which we scheduled a timer for this context */
303 ktime_t aspm_ts_timer_sched;
306 * The interrupt handler for a particular receive context can vary
307 * throughout it's lifetime. This is not a lock protected data member so
308 * it must be updated atomically and the prev and new value must always
309 * be valid. Worst case is we process an extra interrupt and up to 64
310 * packets with the wrong interrupt handler.
312 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded);
314 /* Indicates that this is vnic context */
317 /* vnic queue index this context is mapped to */
322 * Represents a single packet at a high level. Put commonly computed things in
323 * here so we do not have to keep doing them over and over. The rule of thumb is
324 * if something is used one time to derive some value, store that something in
325 * here. If it is used multiple times, then store the result of that derivation
332 struct hfi1_ctxtdata *rcd;
335 struct ib_other_headers *ohdr;
359 #define HFI1_PKT_TYPE_9B 0
360 #define HFI1_PKT_TYPE_16B 1
365 #define OPA_16B_L4_MASK 0xFFull
366 #define OPA_16B_SC_MASK 0x1F00000ull
367 #define OPA_16B_SC_SHIFT 20
368 #define OPA_16B_LID_MASK 0xFFFFFull
369 #define OPA_16B_DLID_MASK 0xF000ull
370 #define OPA_16B_DLID_SHIFT 20
371 #define OPA_16B_DLID_HIGH_SHIFT 12
372 #define OPA_16B_SLID_MASK 0xF00ull
373 #define OPA_16B_SLID_SHIFT 20
374 #define OPA_16B_SLID_HIGH_SHIFT 8
375 #define OPA_16B_BECN_MASK 0x80000000ull
376 #define OPA_16B_BECN_SHIFT 31
377 #define OPA_16B_FECN_MASK 0x10000000ull
378 #define OPA_16B_FECN_SHIFT 28
379 #define OPA_16B_L2_MASK 0x60000000ull
380 #define OPA_16B_L2_SHIFT 29
381 #define OPA_16B_PKEY_MASK 0xFFFF0000ull
382 #define OPA_16B_PKEY_SHIFT 16
383 #define OPA_16B_LEN_MASK 0x7FF00000ull
384 #define OPA_16B_LEN_SHIFT 20
385 #define OPA_16B_RC_MASK 0xE000000ull
386 #define OPA_16B_RC_SHIFT 25
387 #define OPA_16B_AGE_MASK 0xFF0000ull
388 #define OPA_16B_AGE_SHIFT 16
389 #define OPA_16B_ENTROPY_MASK 0xFFFFull
392 * OPA 16B L2/L4 Encodings
394 #define OPA_16B_L4_9B 0x00
395 #define OPA_16B_L2_TYPE 0x02
396 #define OPA_16B_L4_IB_LOCAL 0x09
397 #define OPA_16B_L4_IB_GLOBAL 0x0A
398 #define OPA_16B_L4_ETHR OPA_VNIC_L4_ETHR
400 static inline u8 hfi1_16B_get_l4(struct hfi1_16b_header *hdr)
402 return (u8)(hdr->lrh[2] & OPA_16B_L4_MASK);
405 static inline u8 hfi1_16B_get_sc(struct hfi1_16b_header *hdr)
407 return (u8)((hdr->lrh[1] & OPA_16B_SC_MASK) >> OPA_16B_SC_SHIFT);
410 static inline u32 hfi1_16B_get_dlid(struct hfi1_16b_header *hdr)
412 return (u32)((hdr->lrh[1] & OPA_16B_LID_MASK) |
413 (((hdr->lrh[2] & OPA_16B_DLID_MASK) >>
414 OPA_16B_DLID_HIGH_SHIFT) << OPA_16B_DLID_SHIFT));
417 static inline u32 hfi1_16B_get_slid(struct hfi1_16b_header *hdr)
419 return (u32)((hdr->lrh[0] & OPA_16B_LID_MASK) |
420 (((hdr->lrh[2] & OPA_16B_SLID_MASK) >>
421 OPA_16B_SLID_HIGH_SHIFT) << OPA_16B_SLID_SHIFT));
424 static inline u8 hfi1_16B_get_becn(struct hfi1_16b_header *hdr)
426 return (u8)((hdr->lrh[0] & OPA_16B_BECN_MASK) >> OPA_16B_BECN_SHIFT);
429 static inline u8 hfi1_16B_get_fecn(struct hfi1_16b_header *hdr)
431 return (u8)((hdr->lrh[1] & OPA_16B_FECN_MASK) >> OPA_16B_FECN_SHIFT);
434 static inline u8 hfi1_16B_get_l2(struct hfi1_16b_header *hdr)
436 return (u8)((hdr->lrh[1] & OPA_16B_L2_MASK) >> OPA_16B_L2_SHIFT);
439 static inline u16 hfi1_16B_get_pkey(struct hfi1_16b_header *hdr)
441 return (u16)((hdr->lrh[2] & OPA_16B_PKEY_MASK) >> OPA_16B_PKEY_SHIFT);
444 static inline u8 hfi1_16B_get_rc(struct hfi1_16b_header *hdr)
446 return (u8)((hdr->lrh[1] & OPA_16B_RC_MASK) >> OPA_16B_RC_SHIFT);
449 static inline u8 hfi1_16B_get_age(struct hfi1_16b_header *hdr)
451 return (u8)((hdr->lrh[3] & OPA_16B_AGE_MASK) >> OPA_16B_AGE_SHIFT);
454 static inline u16 hfi1_16B_get_len(struct hfi1_16b_header *hdr)
456 return (u16)((hdr->lrh[0] & OPA_16B_LEN_MASK) >> OPA_16B_LEN_SHIFT);
459 static inline u16 hfi1_16B_get_entropy(struct hfi1_16b_header *hdr)
461 return (u16)(hdr->lrh[3] & OPA_16B_ENTROPY_MASK);
464 #define OPA_16B_MAKE_QW(low_dw, high_dw) (((u64)(high_dw) << 32) | (low_dw))
469 #define OPA_16B_BTH_PAD_MASK 7
470 static inline u8 hfi1_16B_bth_get_pad(struct ib_other_headers *ohdr)
472 return (u8)((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_PAD_SHIFT) &
473 OPA_16B_BTH_PAD_MASK);
476 struct rvt_sge_state;
479 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
480 * Mostly for MADs that set or query link parameters, also ipath
483 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
484 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */
485 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */
486 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */
487 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
488 #define HFI1_IB_CFG_SPD 5 /* current Link spd */
489 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
490 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
491 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
492 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
493 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */
494 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
495 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
496 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
497 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
498 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
499 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */
500 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */
501 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19
502 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
503 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */
506 * HFI or Host Link States
508 * These describe the states the driver thinks the logical and physical
509 * states are in. Used as an argument to set_link_state(). Implemented
510 * as bits for easy multi-state checking. The actual state can only be
513 #define __HLS_UP_INIT_BP 0
514 #define __HLS_UP_ARMED_BP 1
515 #define __HLS_UP_ACTIVE_BP 2
516 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */
517 #define __HLS_DN_POLL_BP 4
518 #define __HLS_DN_DISABLE_BP 5
519 #define __HLS_DN_OFFLINE_BP 6
520 #define __HLS_VERIFY_CAP_BP 7
521 #define __HLS_GOING_UP_BP 8
522 #define __HLS_GOING_OFFLINE_BP 9
523 #define __HLS_LINK_COOLDOWN_BP 10
525 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
526 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
527 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
528 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */
529 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
530 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
531 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
532 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
533 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
534 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
535 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
537 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
538 #define HLS_DOWN ~(HLS_UP)
540 #define HLS_DEFAULT HLS_DN_POLL
542 /* use this MTU size if none other is given */
543 #define HFI1_DEFAULT_ACTIVE_MTU 10240
544 /* use this MTU size as the default maximum */
545 #define HFI1_DEFAULT_MAX_MTU 10240
546 /* default partition key */
547 #define DEFAULT_PKEY 0xffff
550 * Possible fabric manager config parameters for fm_{get,set}_table()
552 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */
553 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */
554 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */
555 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */
556 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */
557 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */
560 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
561 * these are bits so they can be combined, e.g.
562 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB
564 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01
565 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02
566 #define HFI1_RCVCTRL_CTXT_ENB 0x04
567 #define HFI1_RCVCTRL_CTXT_DIS 0x08
568 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
569 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
570 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
571 #define HFI1_RCVCTRL_PKEY_DIS 0x80
572 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
573 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
574 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
575 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
576 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
577 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
578 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
579 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
581 /* partition enforcement flags */
582 #define HFI1_PART_ENFORCE_IN 0x1
583 #define HFI1_PART_ENFORCE_OUT 0x2
585 /* how often we check for synthetic counter wrap around */
586 #define SYNTH_CNT_TIME 3
589 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */
590 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */
591 #define CNTR_DISABLED 0x2 /* Disable this counter */
592 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */
593 #define CNTR_VL 0x8 /* Per VL counter */
594 #define CNTR_SDMA 0x10
595 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */
596 #define CNTR_MODE_W 0x0
597 #define CNTR_MODE_R 0x1
599 /* VLs Supported/Operational */
600 #define HFI1_MIN_VLS_SUPPORTED 1
601 #define HFI1_MAX_VLS_SUPPORTED 8
603 #define HFI1_GUIDS_PER_PORT 5
604 #define HFI1_PORT_GUID_INDEX 0
606 static inline void incr_cntr64(u64 *cntr)
608 if (*cntr < (u64)-1LL)
612 static inline void incr_cntr32(u32 *cntr)
614 if (*cntr < (u32)-1LL)
618 #define MAX_NAME_SIZE 64
619 struct hfi1_msix_entry {
624 struct irq_affinity_notify notify;
627 /* per-SL CCA information */
629 struct hrtimer hrtimer;
630 struct hfi1_pportdata *ppd; /* read-only */
631 int sl; /* read-only */
632 u16 ccti; /* read/write - current value of CCTI */
635 struct link_down_reason {
637 * SMA-facing value. Should be set from .latest when
638 * HLS_UP_* -> HLS_DN_* transition actually occurs.
650 struct vl_arb_cache {
651 /* protect vl arb cache */
653 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
657 * The structure below encapsulates data relevant to a physical IB Port.
658 * Current chips support only one such port, but the separation
659 * clarifies things a bit. Note that to conform to IB conventions,
660 * port-numbers are one-based. The first or only port is port1.
662 struct hfi1_pportdata {
663 struct hfi1_ibport ibport_data;
665 struct hfi1_devdata *dd;
666 struct kobject pport_cc_kobj;
667 struct kobject sc2vl_kobj;
668 struct kobject sl2sc_kobj;
669 struct kobject vl2mtu_kobj;
672 struct qsfp_data qsfp_info;
673 /* Values for SI tuning of SerDes */
683 /* did we read platform config from scratch registers? */
684 bool config_from_scratch;
686 /* GUIDs for this interface, in host order, guids[0] is a port guid */
687 u64 guids[HFI1_GUIDS_PER_PORT];
689 /* GUID for peer interface, in host order */
692 /* up or down physical link state */
696 * this address is mapped read-only into user processes so they can
697 * get status cheaply, whenever they want. One qword of status per port
701 /* SendDMA related entries */
703 struct workqueue_struct *hfi1_wq;
704 struct workqueue_struct *link_wq;
706 /* move out of interrupt context */
707 struct work_struct link_vc_work;
708 struct work_struct link_up_work;
709 struct work_struct link_down_work;
710 struct work_struct sma_message_work;
711 struct work_struct freeze_work;
712 struct work_struct link_downgrade_work;
713 struct work_struct link_bounce_work;
714 struct delayed_work start_link_work;
715 /* host link state variables */
716 struct mutex hls_lock;
719 /* these are the "32 bit" regs */
721 u32 ibmtu; /* The MTU programmed for this unit */
723 * Current max size IB packet (in bytes) including IB headers, that
724 * we can send. Changes when ibmtu changes.
727 u32 current_egress_rate; /* units [10^6 bits/sec] */
728 /* LID programmed for this instance */
730 /* list of pkeys programmed; 0 if not set */
731 u16 pkeys[MAX_PKEY_VALUES];
732 u16 link_width_supported;
733 u16 link_width_downgrade_supported;
734 u16 link_speed_supported;
735 u16 link_width_enabled;
736 u16 link_width_downgrade_enabled;
737 u16 link_speed_enabled;
738 u16 link_width_active;
739 u16 link_width_downgrade_tx_active;
740 u16 link_width_downgrade_rx_active;
741 u16 link_speed_active;
744 u8 actual_vls_operational;
745 /* LID mask control */
747 /* Rx Polarity inversion (compensate for ~tx on partner) */
750 u8 hw_pidx; /* physical port index */
751 u8 port; /* IB port number and index into dd->pports - 1 */
752 /* type of neighbor node */
755 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */
756 u8 neighbor_port_number;
757 u8 is_sm_config_started;
758 u8 offline_disabled_reason;
759 u8 is_active_optimize_enabled;
760 u8 driver_link_ready; /* driver ready for active link */
761 u8 link_enabled; /* link enabled? */
763 u8 local_tx_rate; /* rate given to 8051 firmware */
766 /* placeholders for IB MAD packet settings */
767 u8 overrun_threshold;
768 u8 phy_error_threshold;
769 unsigned int is_link_down_queued;
771 /* Used to override LED behavior for things like maintenance beaconing*/
773 * Alternates per phase of blink
774 * [0] holds LED off duration, [1] holds LED on duration
776 unsigned long led_override_vals[2];
777 u8 led_override_phase; /* LSB picks from vals[] */
778 atomic_t led_override_timer_active;
779 /* Used to flash LEDs in override mode */
780 struct timer_list led_override_timer;
786 * cca_timer_lock protects access to the per-SL cca_timer
787 * structures (specifically the ccti member).
789 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
790 struct cca_timer cca_timer[OPA_MAX_SLS];
792 /* List of congestion control table entries */
793 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
795 /* congestion entries, each entry corresponding to a SL */
796 struct opa_congestion_setting_entry_shadow
797 congestion_entries[OPA_MAX_SLS];
800 * cc_state_lock protects (write) access to the per-port
803 spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
805 struct cc_state __rcu *cc_state;
807 /* Total number of congestion control table entries */
810 /* Bit map identifying service level */
811 u32 cc_sl_control_map;
813 /* CA's max number of 64 entry units in the congestion control table */
814 u8 cc_max_table_entries;
817 * begin congestion log related entries
818 * cc_log_lock protects all congestion log related data
820 spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
821 u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
822 u16 threshold_event_counter;
823 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
824 int cc_log_idx; /* index for logging events */
825 int cc_mad_idx; /* index for reporting events */
826 /* end congestion log related entries */
828 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
830 /* port relative counter buffer */
832 /* port relative synthetic counter buffer */
834 /* port_xmit_discards are synthesized from different egress errors */
835 u64 port_xmit_discards;
836 u64 port_xmit_discards_vl[C_VL_COUNT];
837 u64 port_xmit_constraint_errors;
838 u64 port_rcv_constraint_errors;
839 /* count of 'link_err' interrupts from DC */
841 /* number of times link retrained successfully */
843 /* number of times a link unknown frame was reported */
844 u64 unknown_frame_count;
845 /* port_ltp_crc_mode is returned in 'portinfo' MADs */
846 u16 port_ltp_crc_mode;
847 /* port_crc_mode_enabled is the crc we support */
848 u8 port_crc_mode_enabled;
849 /* mgmt_allowed is also returned in 'portinfo' MADs */
851 u8 part_enforce; /* partition enforcement flags */
852 struct link_down_reason local_link_down_reason;
853 struct link_down_reason neigh_link_down_reason;
854 /* Value to be sent to link peer on LinkDown .*/
855 u8 remote_link_down_reason;
856 /* Error events that will cause a port bounce. */
857 u32 port_error_action;
858 struct work_struct linkstate_active_work;
859 /* Does this port need to prescan for FECNs */
863 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
865 typedef void (*opcode_handler)(struct hfi1_packet *packet);
866 typedef void (*hfi1_make_req)(struct rvt_qp *qp,
867 struct hfi1_pkt_state *ps,
868 struct rvt_swqe *wqe);
871 /* return values for the RHF receive functions */
872 #define RHF_RCV_CONTINUE 0 /* keep going */
873 #define RHF_RCV_DONE 1 /* stop, this packet processed */
874 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */
876 struct rcv_array_data {
884 struct send_context *sc;
887 /* 16 to directly index */
888 #define PER_VL_SEND_CONTEXTS 16
890 struct err_info_rcvport {
896 struct err_info_constraint {
903 unsigned int curr; /* current temperature */
904 unsigned int lo_lim; /* low temperature limit */
905 unsigned int hi_lim; /* high temperature limit */
906 unsigned int crit_lim; /* critical temperature limit */
907 u8 triggers; /* temperature triggers */
910 struct hfi1_i2c_bus {
911 struct hfi1_devdata *controlling_dd; /* current controlling device */
912 struct i2c_adapter adapter; /* bus details */
913 struct i2c_algo_bit_data algo; /* bus algorithm details */
914 int num; /* bus number, 0 or 1 */
917 /* common data between shared ASIC HFIs */
918 struct hfi1_asic_data {
919 struct hfi1_devdata *dds[2]; /* back pointers */
920 struct mutex asic_resource_mutex;
921 struct hfi1_i2c_bus *i2c_bus0;
922 struct hfi1_i2c_bus *i2c_bus1;
925 /* sizes for both the QP and RSM map tables */
926 #define NUM_MAP_ENTRIES 256
927 #define NUM_MAP_REGS 32
930 * Number of VNIC contexts used. Ensure it is less than or equal to
931 * max queues supported by VNIC (HFI1_VNIC_MAX_QUEUE).
933 #define HFI1_NUM_VNIC_CTXT 8
935 /* Number of VNIC RSM entries */
936 #define NUM_VNIC_MAP_ENTRIES 8
938 /* Virtual NIC information */
939 struct hfi1_vnic_data {
940 struct hfi1_ctxtdata *ctxt[HFI1_NUM_VNIC_CTXT];
941 struct kmem_cache *txreq_cache;
949 struct hfi1_vnic_vport_info;
951 /* device data struct now contains only "general per-device" info.
952 * fields related to a physical IB port are in a hfi1_pportdata struct.
957 #define BOARD_VERS_MAX 96 /* how long the version string can be */
958 #define SERIAL_MAX 16 /* length of the serial number */
960 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64);
961 struct hfi1_devdata {
962 struct hfi1_ibdev verbs_dev; /* must be first */
963 struct list_head list;
964 /* pointers to related structs for this device */
965 /* pci access data structure */
966 struct pci_dev *pcidev;
967 struct cdev user_cdev;
968 struct cdev diag_cdev;
970 struct device *user_device;
971 struct device *diag_device;
972 struct device *ui_device;
974 /* first mapping up to RcvArray */
975 u8 __iomem *kregbase1;
976 resource_size_t physaddr;
978 /* second uncached mapping from RcvArray to pio send buffers */
979 u8 __iomem *kregbase2;
980 /* for detecting offset above kregbase2 address */
983 /* Per VL data. Enough for all VLs but not all elements are set/used. */
984 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
985 /* send context data */
986 struct send_context_info *send_contexts;
987 /* map hardware send contexts to software index */
989 /* spinlock for allocating and releasing send context resources */
991 /* lock for pio_map */
992 spinlock_t pio_map_lock;
993 /* Send Context initialization lock. */
994 spinlock_t sc_init_lock;
995 /* lock for sdma_map */
996 spinlock_t sde_map_lock;
997 /* array of kernel send contexts */
998 struct send_context **kernel_send_context;
999 /* array of vl maps */
1000 struct pio_vl_map __rcu *pio_map;
1001 /* default flags to last descriptor */
1004 /* fields common to all SDMA engines */
1006 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */
1007 dma_addr_t sdma_heads_phys;
1008 void *sdma_pad_dma; /* DMA'ed by chip */
1009 dma_addr_t sdma_pad_phys;
1010 /* for deallocation */
1011 size_t sdma_heads_size;
1012 /* number from the chip */
1013 u32 chip_sdma_engines;
1016 /* array of engines sized by num_sdma */
1017 struct sdma_engine *per_sdma;
1018 /* array of vl maps */
1019 struct sdma_vl_map __rcu *sdma_map;
1020 /* SPC freeze waitqueue and variable */
1021 wait_queue_head_t sdma_unfreeze_wq;
1022 atomic_t sdma_unfreeze_count;
1024 u32 lcb_access_count; /* count of LCB users */
1026 /* common data between shared ASIC HFIs in this OS */
1027 struct hfi1_asic_data *asic_data;
1029 /* mem-mapped pointer to base of PIO buffers */
1030 void __iomem *piobase;
1032 * write-combining mem-mapped pointer to base of RcvArray
1035 void __iomem *rcvarray_wc;
1037 * credit return base - a per-NUMA range of DMA address that
1038 * the chip will use to update the per-context free counter
1040 struct credit_return_base *cr_base;
1042 /* send context numbers and sizes for each type */
1043 struct sc_config_sizes sc_sizes[SC_MAX];
1045 char *boardname; /* human readable board info */
1050 u64 z_send_schedule;
1052 u64 __percpu *send_schedule;
1053 /* number of reserved contexts for VNIC usage */
1054 u16 num_vnic_contexts;
1055 /* number of receive contexts in use by the driver */
1056 u32 num_rcv_contexts;
1057 /* number of pio send contexts in use by the driver */
1058 u32 num_send_contexts;
1060 * number of ctxts available for PSM open
1063 /* total number of available user/PSM contexts */
1064 u32 num_user_contexts;
1065 /* base receive interrupt timeout, in CSR units */
1066 u32 rcv_intr_timeout_csr;
1068 u32 freezelen; /* max length of freezemsg */
1069 u64 __iomem *egrtidbase;
1070 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */
1071 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */
1072 spinlock_t uctxt_lock; /* protect rcd changes */
1073 struct mutex dc8051_lock; /* exclusive access to 8051 */
1074 struct workqueue_struct *update_cntr_wq;
1075 struct work_struct update_cntr_work;
1076 /* exclusive access to 8051 memory */
1077 spinlock_t dc8051_memlock;
1078 int dc8051_timed_out; /* remember if the 8051 timed out */
1080 * A page that will hold event notification bitmaps for all
1081 * contexts. This page will be mapped into all processes.
1083 unsigned long *events;
1085 * per unit status, see also portdata statusp
1086 * mapped read-only into user processes so they can get unit and
1087 * IB link status cheaply
1089 struct hfi1_status *status;
1091 /* revision register shadow */
1093 /* Base GUID for device (network order) */
1096 /* these are the "32 bit" regs */
1098 /* value we put in kr_rcvhdrsize */
1100 /* number of receive contexts the chip supports */
1101 u32 chip_rcv_contexts;
1102 /* number of receive array entries */
1103 u32 chip_rcv_array_count;
1104 /* number of PIO send contexts the chip supports */
1105 u32 chip_send_contexts;
1106 /* number of bytes in the PIO memory buffer */
1107 u32 chip_pio_mem_size;
1108 /* number of bytes in the SDMA memory buffer */
1109 u32 chip_sdma_mem_size;
1111 /* size of each rcvegrbuffer */
1114 u16 rcvegrbufsize_shift;
1115 /* both sides of the PCIe link are gen3 capable */
1116 u8 link_gen3_capable;
1118 /* localbus width (1, 2,4,8,16,32) from config space */
1120 /* localbus speed in MHz */
1122 int unit; /* unit # of this chip */
1123 int node; /* home node of this chip */
1125 /* save these PCI fields to restore after a reset */
1137 * ASCII serial number, from flash, large enough for original
1138 * all digit strings, and longer serial number format
1140 u8 serial[SERIAL_MAX];
1141 /* human readable board version */
1142 u8 boardversion[BOARD_VERS_MAX];
1143 u8 lbus_info[32]; /* human readable localbus info */
1144 /* chip major rev, from CceRevision */
1146 /* chip minor rev, from CceRevision */
1150 /* implementation code */
1152 /* vAU of this device */
1154 /* vCU of this device */
1156 /* link credits of this device */
1158 /* initial vl15 credits to use */
1162 * Cached value for vl15buf, read during verify cap interrupt. VL15
1163 * credits are to be kept at 0 and set when handling the link-up
1164 * interrupt. This removes the possibility of receiving VL15 MAD
1165 * packets before this HFI is ready.
1169 /* Misc small ints */
1173 u16 irev; /* implementation revision */
1174 u32 dc8051_ver; /* 8051 firmware version */
1176 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
1177 struct platform_config platform_config;
1178 struct platform_config_cache pcfg_cache;
1180 struct diag_client *diag_client;
1182 /* MSI-X information */
1183 struct hfi1_msix_entry *msix_entries;
1184 u32 num_msix_entries;
1185 u32 first_dyn_msix_idx;
1187 /* INTx information */
1188 u32 requested_intx_irq; /* did we request one? */
1190 /* general interrupt: mask of handled interrupts */
1191 u64 gi_mask[CCE_NUM_INT_CSRS];
1193 struct rcv_array_data rcv_entries;
1195 /* cycle length of PS* counters in HW (in picoseconds) */
1196 u16 psxmitwait_check_rate;
1199 * 64 bit synthetic counters
1201 struct timer_list synth_stats_timer;
1207 size_t cntrnameslen;
1213 * remembered values for synthetic counters
1222 char *portcntrnames;
1223 size_t portcntrnameslen;
1225 struct err_info_rcvport err_info_rcvport;
1226 struct err_info_constraint err_info_rcv_constraint;
1227 struct err_info_constraint err_info_xmit_constraint;
1229 atomic_t drop_packet;
1231 u8 err_info_uncorrectable;
1232 u8 err_info_fmconfig;
1235 * Software counters for the status bits defined by the
1236 * associated error status registers
1238 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1239 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1240 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1241 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1242 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1243 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1244 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1246 /* Software counter that spans all contexts */
1247 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1248 /* Software counter that spans all DMA engines */
1249 u64 sw_send_dma_eng_err_status_cnt[
1250 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1251 /* Software counter that aggregates all cce_err_status errors */
1252 u64 sw_cce_err_status_aggregate;
1253 /* Software counter that aggregates all bypass packet rcv errors */
1254 u64 sw_rcv_bypass_packet_errors;
1255 /* receive interrupt function */
1256 rhf_rcv_function_ptr normal_rhf_rcv_functions[8];
1258 /* Save the enabled LCB error bits */
1262 * Capability to have different send engines simply by changing a
1265 send_routine process_pio_send ____cacheline_aligned_in_smp;
1266 send_routine process_dma_send;
1267 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1268 u64 pbc, const void *from, size_t count);
1269 int (*process_vnic_dma_send)(struct hfi1_devdata *dd, u8 q_idx,
1270 struct hfi1_vnic_vport_info *vinfo,
1271 struct sk_buff *skb, u64 pbc, u8 plen);
1272 /* hfi1_pportdata, points to array of (physical) port-specific
1273 * data structs, indexed by pidx (0..n-1)
1275 struct hfi1_pportdata *pport;
1276 /* receive context data */
1277 struct hfi1_ctxtdata **rcd;
1278 u64 __percpu *int_counter;
1279 /* verbs tx opcode stats */
1280 struct hfi1_opcode_stats_perctx __percpu *tx_opstats;
1281 /* device (not port) flags, basically device capabilities */
1283 /* Number of physical ports available */
1285 /* Lowest context number which can be used by user processes or VNIC */
1286 u8 first_dyn_alloc_ctxt;
1287 /* adding a new field here would make it part of this cacheline */
1289 /* seqlock for sc2vl */
1290 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp;
1292 /* receive interrupt functions */
1293 rhf_rcv_function_ptr *rhf_rcv_function_map;
1294 u64 __percpu *rcv_limit;
1295 u16 rhf_offset; /* offset of RHF within receive header entry */
1296 /* adding a new field here would make it part of this cacheline */
1298 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1303 /* Timer and counter used to detect RcvBufOvflCnt changes */
1304 struct timer_list rcverr_timer;
1306 wait_queue_head_t event_queue;
1308 /* receive context tail dummy address */
1309 __le64 *rcvhdrtail_dummy_kvaddr;
1310 dma_addr_t rcvhdrtail_dummy_dma;
1313 /* Serialize ASPM enable/disable between multiple verbs contexts */
1314 spinlock_t aspm_lock;
1315 /* Number of verbs contexts which have disabled ASPM */
1316 atomic_t aspm_disabled_cnt;
1317 /* Keeps track of user space clients */
1318 atomic_t user_refcount;
1319 /* Used to wait for outstanding user space clients before dev removal */
1320 struct completion user_comp;
1322 bool eprom_available; /* true if EPROM is available for this device */
1323 bool aspm_supported; /* Does HW support ASPM */
1324 bool aspm_enabled; /* ASPM state: enabled/disabled */
1325 struct rhashtable *sdma_rht;
1327 struct kobject kobj;
1330 struct hfi1_vnic_data vnic;
1333 static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare)
1335 return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES;
1338 /* 8051 firmware version helper */
1339 #define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c))
1340 #define dc8051_ver_maj(a) (((a) & 0xff0000) >> 16)
1341 #define dc8051_ver_min(a) (((a) & 0x00ff00) >> 8)
1342 #define dc8051_ver_patch(a) ((a) & 0x0000ff)
1344 /* f_put_tid types */
1345 #define PT_EXPECTED 0
1347 #define PT_INVALID_FLUSH 2
1348 #define PT_INVALID 3
1352 struct mmu_rb_handler;
1354 /* Private data for file operations */
1355 struct hfi1_filedata {
1356 struct hfi1_devdata *dd;
1357 struct hfi1_ctxtdata *uctxt;
1358 struct hfi1_user_sdma_comp_q *cq;
1359 struct hfi1_user_sdma_pkt_q *pq;
1361 /* for cpu affinity; -1 if none */
1364 struct mmu_rb_handler *handler;
1365 struct tid_rb_node **entry_to_rb;
1366 spinlock_t tid_lock; /* protect tid_[limit,used] counters */
1370 u32 invalid_tid_idx;
1371 /* protect invalid_tids array and invalid_tid_idx */
1372 spinlock_t invalid_lock;
1373 struct mm_struct *mm;
1376 extern struct list_head hfi1_dev_list;
1377 extern spinlock_t hfi1_devs_lock;
1378 struct hfi1_devdata *hfi1_lookup(int unit);
1380 static inline unsigned long uctxt_offset(struct hfi1_ctxtdata *uctxt)
1382 return (uctxt->ctxt - uctxt->dd->first_dyn_alloc_ctxt) *
1383 HFI1_MAX_SHARED_CTXTS;
1386 int hfi1_init(struct hfi1_devdata *dd, int reinit);
1387 int hfi1_count_active_units(void);
1389 int hfi1_diag_add(struct hfi1_devdata *dd);
1390 void hfi1_diag_remove(struct hfi1_devdata *dd);
1391 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1393 void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1395 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1396 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd);
1397 int hfi1_create_kctxts(struct hfi1_devdata *dd);
1398 int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa,
1399 struct hfi1_ctxtdata **rcd);
1400 void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd);
1401 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
1402 struct hfi1_devdata *dd, u8 hw_pidx, u8 port);
1403 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1404 int hfi1_rcd_put(struct hfi1_ctxtdata *rcd);
1405 void hfi1_rcd_get(struct hfi1_ctxtdata *rcd);
1406 struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
1408 struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt);
1409 int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread);
1410 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1411 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1412 void set_all_slowpath(struct hfi1_devdata *dd);
1413 void hfi1_vnic_synchronize_irq(struct hfi1_devdata *dd);
1414 void hfi1_set_vnic_msix_info(struct hfi1_ctxtdata *rcd);
1415 void hfi1_reset_vnic_msix_info(struct hfi1_ctxtdata *rcd);
1417 extern const struct pci_device_id hfi1_pci_tbl[];
1418 void hfi1_make_ud_req_9B(struct rvt_qp *qp,
1419 struct hfi1_pkt_state *ps,
1420 struct rvt_swqe *wqe);
1422 void hfi1_make_ud_req_16B(struct rvt_qp *qp,
1423 struct hfi1_pkt_state *ps,
1424 struct rvt_swqe *wqe);
1426 /* receive packet handler dispositions */
1427 #define RCV_PKT_OK 0x0 /* keep going */
1428 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */
1429 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */
1431 /* calculate the current RHF address */
1432 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1434 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset;
1437 int hfi1_reset_device(int);
1439 void receive_interrupt_work(struct work_struct *work);
1441 /* extract service channel from header and rhf */
1442 static inline int hfi1_9B_get_sc5(struct ib_header *hdr, u64 rhf)
1444 return ib_get_sc(hdr) | ((!!(rhf_dc_info(rhf))) << 4);
1447 #define HFI1_JKEY_WIDTH 16
1448 #define HFI1_JKEY_MASK (BIT(16) - 1)
1449 #define HFI1_ADMIN_JKEY_RANGE 32
1452 * J_KEYs are split and allocated in the following groups:
1453 * 0 - 31 - users with administrator privileges
1454 * 32 - 63 - kernel protocols using KDETH packets
1455 * 64 - 65535 - all other users using KDETH packets
1457 static inline u16 generate_jkey(kuid_t uid)
1459 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK;
1461 if (capable(CAP_SYS_ADMIN))
1462 jkey &= HFI1_ADMIN_JKEY_RANGE - 1;
1464 jkey |= BIT(HFI1_JKEY_WIDTH - 1);
1470 * active_egress_rate
1472 * returns the active egress rate in units of [10^6 bits/sec]
1474 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1476 u16 link_speed = ppd->link_speed_active;
1477 u16 link_width = ppd->link_width_active;
1480 if (link_speed == OPA_LINK_SPEED_25G)
1481 egress_rate = 25000;
1482 else /* assume OPA_LINK_SPEED_12_5G */
1483 egress_rate = 12500;
1485 switch (link_width) {
1486 case OPA_LINK_WIDTH_4X:
1489 case OPA_LINK_WIDTH_3X:
1492 case OPA_LINK_WIDTH_2X:
1496 /* assume IB_WIDTH_1X */
1506 * Returns the number of 'fabric clock cycles' to egress a packet
1507 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock
1508 * rate is (approximately) 805 MHz, the units of the returned value
1511 static inline u32 egress_cycles(u32 len, u32 rate)
1518 * (length) [bits] / (rate) [bits/sec]
1519 * ---------------------------------------------------
1520 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec]
1523 cycles = len * 8; /* bits */
1530 void set_link_ipg(struct hfi1_pportdata *ppd);
1531 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u32 rlid, u32 lqpn,
1532 u32 rqpn, u8 svc_type);
1533 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn,
1534 u32 pkey, u32 slid, u32 dlid, u8 sc5,
1535 const struct ib_grh *old_grh);
1536 void return_cnp_16B(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1537 u32 remote_qpn, u32 pkey, u32 slid, u32 dlid,
1538 u8 sc5, const struct ib_grh *old_grh);
1539 typedef void (*hfi1_handle_cnp)(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1540 u32 remote_qpn, u32 pkey, u32 slid, u32 dlid,
1541 u8 sc5, const struct ib_grh *old_grh);
1543 #define PKEY_CHECK_INVALID -1
1544 int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1545 u8 sc5, int8_t s_pkey_index);
1547 #define PACKET_EGRESS_TIMEOUT 350
1548 static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1550 /* Pause at least 1us, to ensure chip returns all credits */
1551 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1553 udelay(usec ? usec : 1);
1557 * sc_to_vlt() reverse lookup sc to vl
1561 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1566 if (sc5 >= OPA_MAX_SCS)
1570 seq = read_seqbegin(&dd->sc2vl_lock);
1571 rval = *(((u8 *)dd->sc2vl) + sc5);
1572 } while (read_seqretry(&dd->sc2vl_lock, seq));
1577 #define PKEY_MEMBER_MASK 0x8000
1578 #define PKEY_LOW_15_MASK 0x7fff
1581 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1582 * being an entry from the ingress partition key table), return 0
1583 * otherwise. Use the matching criteria for ingress partition keys
1584 * specified in the OPAv1 spec., section 9.10.14.
1586 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1588 u16 mkey = pkey & PKEY_LOW_15_MASK;
1589 u16 ment = ent & PKEY_LOW_15_MASK;
1593 * If pkey[15] is clear (limited partition member),
1594 * is bit 15 in the corresponding table element
1595 * clear (limited member)?
1597 if (!(pkey & PKEY_MEMBER_MASK))
1598 return !!(ent & PKEY_MEMBER_MASK);
1605 * ingress_pkey_table_search - search the entire pkey table for
1606 * an entry which matches 'pkey'. return 0 if a match is found,
1609 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1613 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1614 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1621 * ingress_pkey_table_fail - record a failure of ingress pkey validation,
1622 * i.e., increment port_rcv_constraint_errors for the port, and record
1623 * the 'error info' for this failure.
1625 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
1628 struct hfi1_devdata *dd = ppd->dd;
1630 incr_cntr64(&ppd->port_rcv_constraint_errors);
1631 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1632 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1633 dd->err_info_rcv_constraint.slid = slid;
1634 dd->err_info_rcv_constraint.pkey = pkey;
1639 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1
1640 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx
1641 * is a hint as to the best place in the partition key table to begin
1642 * searching. This function should not be called on the data path because
1643 * of performance reasons. On datapath pkey check is expected to be done
1644 * by HW and rcv_pkey_check function should be called instead.
1646 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1647 u8 sc5, u8 idx, u32 slid, bool force)
1649 if (!(force) && !(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1652 /* If SC15, pkey[0:14] must be 0x7fff */
1653 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1656 /* Is the pkey = 0x0, or 0x8000? */
1657 if ((pkey & PKEY_LOW_15_MASK) == 0)
1660 /* The most likely matching pkey has index 'idx' */
1661 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1664 /* no match - try the whole table */
1665 if (!ingress_pkey_table_search(ppd, pkey))
1669 ingress_pkey_table_fail(ppd, pkey, slid);
1674 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1
1675 * otherwise. It only ensures pkey is vlid for QP0. This function
1676 * should be called on the data path instead of ingress_pkey_check
1677 * as on data path, pkey check is done by HW (except for QP0).
1679 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1682 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1685 /* If SC15, pkey[0:14] must be 0x7fff */
1686 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1691 ingress_pkey_table_fail(ppd, pkey, slid);
1697 /* MTU enumeration, 256-4k match IB */
1699 #define OPA_MTU_256 1
1700 #define OPA_MTU_512 2
1701 #define OPA_MTU_1024 3
1702 #define OPA_MTU_2048 4
1703 #define OPA_MTU_4096 5
1705 u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1706 int mtu_to_enum(u32 mtu, int default_if_bad);
1707 u16 enum_to_mtu(int mtu);
1708 static inline int valid_ib_mtu(unsigned int mtu)
1710 return mtu == 256 || mtu == 512 ||
1711 mtu == 1024 || mtu == 2048 ||
1715 static inline int valid_opa_max_mtu(unsigned int mtu)
1717 return mtu >= 2048 &&
1718 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1721 int set_mtu(struct hfi1_pportdata *ppd);
1723 int hfi1_set_lid(struct hfi1_pportdata *ppd, u32 lid, u8 lmc);
1724 void hfi1_disable_after_error(struct hfi1_devdata *dd);
1725 int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit);
1726 int hfi1_rcvbuf_validate(u32 size, u8 type, u16 *encode);
1728 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t);
1729 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t);
1731 void set_up_vau(struct hfi1_devdata *dd, u8 vau);
1732 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf);
1733 void reset_link_credits(struct hfi1_devdata *dd);
1734 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1736 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc);
1738 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1743 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1745 return container_of(dev, struct hfi1_devdata, verbs_dev);
1748 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1750 return dd_from_dev(to_idev(ibdev));
1753 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1755 return container_of(ibp, struct hfi1_pportdata, ibport_data);
1758 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi)
1760 return container_of(rdi, struct hfi1_ibdev, rdi);
1763 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1765 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1766 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1768 WARN_ON(pidx >= dd->num_pports);
1769 return &dd->pport[pidx].ibport_data;
1772 static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd)
1774 return &rcd->ppd->ibport_data;
1777 void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt,
1779 static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt,
1785 if (pkt->etype == RHF_RCV_TYPE_BYPASS) {
1786 fecn = hfi1_16B_get_fecn(pkt->hdr);
1787 becn = hfi1_16B_get_becn(pkt->hdr);
1789 fecn = ib_bth_get_fecn(pkt->ohdr);
1790 becn = ib_bth_get_becn(pkt->ohdr);
1792 if (unlikely(fecn || becn)) {
1793 hfi1_process_ecn_slowpath(qp, pkt, do_cnp);
1800 * Return the indexed PKEY from the port PKEY table.
1802 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1804 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1807 if (index >= ARRAY_SIZE(ppd->pkeys))
1810 ret = ppd->pkeys[index];
1816 * Return the indexed GUID from the port GUIDs table.
1818 static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index)
1820 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1822 WARN_ON(index >= HFI1_GUIDS_PER_PORT);
1823 return cpu_to_be64(ppd->guids[index]);
1827 * Called by readers of cc_state only, must call under rcu_read_lock().
1829 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
1831 return rcu_dereference(ppd->cc_state);
1835 * Called by writers of cc_state only, must call under cc_state_lock.
1838 struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd)
1840 return rcu_dereference_protected(ppd->cc_state,
1841 lockdep_is_held(&ppd->cc_state_lock));
1845 * values for dd->flags (_device_ related flags)
1847 #define HFI1_INITTED 0x1 /* chip and driver up and initted */
1848 #define HFI1_PRESENT 0x2 /* chip accesses can be done */
1849 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */
1850 #define HFI1_HAS_SDMA_TIMEOUT 0x8
1851 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */
1852 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */
1854 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1855 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
1857 /* ctxt_flag bit offsets */
1858 /* base context has not finished initializing */
1859 #define HFI1_CTXT_BASE_UNINIT 1
1860 /* base context initaliation failed */
1861 #define HFI1_CTXT_BASE_FAILED 2
1862 /* waiting for a packet to arrive */
1863 #define HFI1_CTXT_WAITING_RCV 3
1864 /* waiting for an urgent packet to arrive */
1865 #define HFI1_CTXT_WAITING_URG 4
1867 /* free up any allocated data at closes */
1868 struct hfi1_devdata *hfi1_init_dd(struct pci_dev *pdev,
1869 const struct pci_device_id *ent);
1870 void hfi1_free_devdata(struct hfi1_devdata *dd);
1871 struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra);
1873 /* LED beaconing functions */
1874 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
1875 unsigned int timeoff);
1876 void shutdown_led_override(struct hfi1_pportdata *ppd);
1878 #define HFI1_CREDIT_RETURN_RATE (100)
1881 * The number of words for the KDETH protocol field. If this is
1882 * larger then the actual field used, then part of the payload
1883 * will be in the header.
1885 * Optimally, we want this sized so that a typical case will
1886 * use full cache lines. The typical local KDETH header would
1897 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS
1899 #define DEFAULT_RCVHDRSIZE 9
1902 * Maximal header byte count:
1913 * We also want to maintain a cache line alignment to assist DMA'ing
1914 * of the header bytes. Round up to a good size.
1916 #define DEFAULT_RCVHDR_ENTSIZE 32
1918 bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm,
1919 u32 nlocked, u32 npages);
1920 int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr,
1921 size_t npages, bool writable, struct page **pages);
1922 void hfi1_release_user_pages(struct mm_struct *mm, struct page **p,
1923 size_t npages, bool dirty);
1925 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1927 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL;
1930 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1933 * volatile because it's a DMA target from the chip, routine is
1934 * inlined, and don't want register caching or reordering.
1936 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr);
1943 extern const char ib_hfi1_version[];
1945 int hfi1_device_create(struct hfi1_devdata *dd);
1946 void hfi1_device_remove(struct hfi1_devdata *dd);
1948 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
1949 struct kobject *kobj);
1950 int hfi1_verbs_register_sysfs(struct hfi1_devdata *dd);
1951 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *dd);
1952 /* Hook for sysfs read of QSFP */
1953 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
1955 int hfi1_pcie_init(struct pci_dev *pdev, const struct pci_device_id *ent);
1956 void hfi1_clean_up_interrupts(struct hfi1_devdata *dd);
1957 void hfi1_pcie_cleanup(struct pci_dev *pdev);
1958 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev);
1959 void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
1960 int pcie_speeds(struct hfi1_devdata *dd);
1961 int request_msix(struct hfi1_devdata *dd, u32 msireq);
1962 int restore_pci_variables(struct hfi1_devdata *dd);
1963 int save_pci_variables(struct hfi1_devdata *dd);
1964 int do_pcie_gen3_transition(struct hfi1_devdata *dd);
1965 int parse_platform_config(struct hfi1_devdata *dd);
1966 int get_platform_config_field(struct hfi1_devdata *dd,
1967 enum platform_config_table_type_encoding
1968 table_type, int table_index, int field_index,
1969 u32 *data, u32 len);
1971 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi);
1974 * Flush write combining store buffers (if present) and perform a write
1977 static inline void flush_wc(void)
1979 asm volatile("sfence" : : : "memory");
1982 void handle_eflags(struct hfi1_packet *packet);
1983 int process_receive_ib(struct hfi1_packet *packet);
1984 int process_receive_bypass(struct hfi1_packet *packet);
1985 int process_receive_error(struct hfi1_packet *packet);
1986 int kdeth_process_expected(struct hfi1_packet *packet);
1987 int kdeth_process_eager(struct hfi1_packet *packet);
1988 int process_receive_invalid(struct hfi1_packet *packet);
1989 void seqfile_dump_rcd(struct seq_file *s, struct hfi1_ctxtdata *rcd);
1991 /* global module parameter variables */
1992 extern unsigned int hfi1_max_mtu;
1993 extern unsigned int hfi1_cu;
1994 extern unsigned int user_credit_return_threshold;
1995 extern int num_user_contexts;
1996 extern unsigned long n_krcvqs;
1997 extern uint krcvqs[];
1998 extern int krcvqsset;
1999 extern uint kdeth_qp;
2000 extern uint loopback;
2001 extern uint quick_linkup;
2002 extern uint rcv_intr_timeout;
2003 extern uint rcv_intr_count;
2004 extern uint rcv_intr_dynamic;
2005 extern ushort link_crc_mask;
2007 extern struct mutex hfi1_mutex;
2009 /* Number of seconds before our card status check... */
2010 #define STATUS_TIMEOUT 60
2012 #define DRIVER_NAME "hfi1"
2013 #define HFI1_USER_MINOR_BASE 0
2014 #define HFI1_TRACE_MINOR 127
2015 #define HFI1_NMINORS 255
2017 #define PCI_VENDOR_ID_INTEL 0x8086
2018 #define PCI_DEVICE_ID_INTEL0 0x24f0
2019 #define PCI_DEVICE_ID_INTEL1 0x24f1
2021 #define HFI1_PKT_USER_SC_INTEGRITY \
2022 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
2023 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \
2024 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
2025 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
2027 #define HFI1_PKT_KERNEL_SC_INTEGRITY \
2028 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
2030 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
2033 u64 base_sc_integrity;
2035 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2036 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2040 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2041 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
2042 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2043 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2044 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2045 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
2046 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2047 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2048 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2049 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
2050 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2051 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2052 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
2053 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
2054 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
2055 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2057 if (ctxt_type == SC_USER)
2058 base_sc_integrity |= HFI1_PKT_USER_SC_INTEGRITY;
2060 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
2062 /* turn on send-side job key checks if !A0 */
2064 base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2066 return base_sc_integrity;
2069 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
2071 u64 base_sdma_integrity;
2073 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2074 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2077 base_sdma_integrity =
2078 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2079 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2080 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2081 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2082 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2083 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2084 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2085 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
2086 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2087 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2088 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
2089 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
2090 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
2091 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2093 if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
2094 base_sdma_integrity |=
2095 SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK;
2097 /* turn on send-side job key checks if !A0 */
2099 base_sdma_integrity |=
2100 SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2102 return base_sdma_integrity;
2106 * hfi1_early_err is used (only!) to print early errors before devdata is
2107 * allocated, or when dd->pcidev may not be valid, and at the tail end of
2108 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is
2109 * the same as dd_dev_err, but is used when the message really needs
2110 * the IB port# to be definitive as to what's happening..
2112 #define hfi1_early_err(dev, fmt, ...) \
2113 dev_err(dev, fmt, ##__VA_ARGS__)
2115 #define hfi1_early_info(dev, fmt, ...) \
2116 dev_info(dev, fmt, ##__VA_ARGS__)
2118 #define dd_dev_emerg(dd, fmt, ...) \
2119 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
2120 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2122 #define dd_dev_err(dd, fmt, ...) \
2123 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
2124 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2126 #define dd_dev_err_ratelimited(dd, fmt, ...) \
2127 dev_err_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2128 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2131 #define dd_dev_warn(dd, fmt, ...) \
2132 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
2133 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2135 #define dd_dev_warn_ratelimited(dd, fmt, ...) \
2136 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2137 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2140 #define dd_dev_info(dd, fmt, ...) \
2141 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
2142 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2144 #define dd_dev_info_ratelimited(dd, fmt, ...) \
2145 dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2146 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2149 #define dd_dev_dbg(dd, fmt, ...) \
2150 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
2151 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2153 #define hfi1_dev_porterr(dd, port, fmt, ...) \
2154 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
2155 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), (port), ##__VA_ARGS__)
2158 * this is used for formatting hw error messages...
2160 struct hfi1_hwerror_msgs {
2167 void hfi1_format_hwerrors(u64 hwerrs,
2168 const struct hfi1_hwerror_msgs *hwerrmsgs,
2169 size_t nhwerrmsgs, char *msg, size_t lmsg);
2171 #define USER_OPCODE_CHECK_VAL 0xC0
2172 #define USER_OPCODE_CHECK_MASK 0xC0
2173 #define OPCODE_CHECK_VAL_DISABLED 0x0
2174 #define OPCODE_CHECK_MASK_DISABLED 0x0
2176 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
2178 struct hfi1_pportdata *ppd;
2181 dd->z_int_counter = get_all_cpu_total(dd->int_counter);
2182 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
2183 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule);
2185 ppd = (struct hfi1_pportdata *)(dd + 1);
2186 for (i = 0; i < dd->num_pports; i++, ppd++) {
2187 ppd->ibport_data.rvp.z_rc_acks =
2188 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks);
2189 ppd->ibport_data.rvp.z_rc_qacks =
2190 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks);
2194 /* Control LED state */
2195 static inline void setextled(struct hfi1_devdata *dd, u32 on)
2198 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
2200 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
2203 /* return the i2c resource given the target */
2204 static inline u32 i2c_target(u32 target)
2206 return target ? CR_I2C2 : CR_I2C1;
2209 /* return the i2c chain chip resource that this HFI uses for QSFP */
2210 static inline u32 qsfp_resource(struct hfi1_devdata *dd)
2212 return i2c_target(dd->hfi1_id);
2215 /* Is this device integrated or discrete? */
2216 static inline bool is_integrated(struct hfi1_devdata *dd)
2218 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1;
2221 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
2223 #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
2224 #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev))
2226 static inline void hfi1_update_ah_attr(struct ib_device *ibdev,
2227 struct rdma_ah_attr *attr)
2229 struct hfi1_pportdata *ppd;
2230 struct hfi1_ibport *ibp;
2231 u32 dlid = rdma_ah_get_dlid(attr);
2234 * Kernel clients may not have setup GRH information
2237 ibp = to_iport(ibdev, rdma_ah_get_port_num(attr));
2238 ppd = ppd_from_ibp(ibp);
2239 if ((((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ||
2240 (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE))) &&
2241 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)) &&
2242 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2243 (!(rdma_ah_get_ah_flags(attr) & IB_AH_GRH))) ||
2244 (rdma_ah_get_make_grd(attr))) {
2245 rdma_ah_set_ah_flags(attr, IB_AH_GRH);
2246 rdma_ah_set_interface_id(attr, OPA_MAKE_ID(dlid));
2247 rdma_ah_set_subnet_prefix(attr, ibp->rvp.gid_prefix);
2252 * hfi1_check_mcast- Check if the given lid is
2253 * in the OPA multicast range.
2255 * The LID might either reside in ah.dlid or might be
2256 * in the GRH of the address handle as DGID if extended
2257 * addresses are in use.
2259 static inline bool hfi1_check_mcast(u32 lid)
2261 return ((lid >= opa_get_mcast_base(OPA_MCAST_NR)) &&
2262 (lid != be32_to_cpu(OPA_LID_PERMISSIVE)));
2265 #define opa_get_lid(lid, format) \
2266 __opa_get_lid(lid, OPA_PORT_PACKET_FORMAT_##format)
2268 /* Convert a lid to a specific lid space */
2269 static inline u32 __opa_get_lid(u32 lid, u8 format)
2271 bool is_mcast = hfi1_check_mcast(lid);
2274 case OPA_PORT_PACKET_FORMAT_8B:
2275 case OPA_PORT_PACKET_FORMAT_10B:
2277 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2279 return lid & 0xFFFFF;
2280 case OPA_PORT_PACKET_FORMAT_16B:
2282 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2284 return lid & 0xFFFFFF;
2285 case OPA_PORT_PACKET_FORMAT_9B:
2288 opa_get_mcast_base(OPA_MCAST_NR) +
2289 be16_to_cpu(IB_MULTICAST_LID_BASE));
2291 return lid & 0xFFFF;
2297 /* Return true if the given lid is the OPA 16B multicast range */
2298 static inline bool hfi1_is_16B_mcast(u32 lid)
2301 opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 16B)) &&
2302 (lid != opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B)));
2305 static inline void hfi1_make_opa_lid(struct rdma_ah_attr *attr)
2307 const struct ib_global_route *grh = rdma_ah_read_grh(attr);
2308 u32 dlid = rdma_ah_get_dlid(attr);
2310 /* Modify ah_attr.dlid to be in the 32 bit LID space.
2311 * This is how the address will be laid out:
2312 * Assuming MCAST_NR to be 4,
2313 * 32 bit permissive LID = 0xFFFFFFFF
2314 * Multicast LID range = 0xFFFFFFFE to 0xF0000000
2315 * Unicast LID range = 0xEFFFFFFF to 1
2318 if (ib_is_opa_gid(&grh->dgid))
2319 dlid = opa_get_lid_from_gid(&grh->dgid);
2320 else if ((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) &&
2321 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2322 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)))
2323 dlid = dlid - be16_to_cpu(IB_MULTICAST_LID_BASE) +
2324 opa_get_mcast_base(OPA_MCAST_NR);
2325 else if (dlid == be16_to_cpu(IB_LID_PERMISSIVE))
2326 dlid = be32_to_cpu(OPA_LID_PERMISSIVE);
2328 rdma_ah_set_dlid(attr, dlid);
2331 static inline u8 hfi1_get_packet_type(u32 lid)
2333 /* 9B if lid > 0xF0000000 */
2334 if (lid >= opa_get_mcast_base(OPA_MCAST_NR))
2335 return HFI1_PKT_TYPE_9B;
2337 /* 16B if lid > 0xC000 */
2338 if (lid >= opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 9B))
2339 return HFI1_PKT_TYPE_16B;
2341 return HFI1_PKT_TYPE_9B;
2344 static inline bool hfi1_get_hdr_type(u32 lid, struct rdma_ah_attr *attr)
2347 * If there was an incoming 16B packet with permissive
2348 * LIDs, OPA GIDs would have been programmed when those
2349 * packets were received. A 16B packet will have to
2350 * be sent in response to that packet. Return a 16B
2351 * header type if that's the case.
2353 if (rdma_ah_get_dlid(attr) == be32_to_cpu(OPA_LID_PERMISSIVE))
2354 return (ib_is_opa_gid(&rdma_ah_read_grh(attr)->dgid)) ?
2355 HFI1_PKT_TYPE_16B : HFI1_PKT_TYPE_9B;
2358 * Return a 16B header type if either the the destination
2359 * or source lid is extended.
2361 if (hfi1_get_packet_type(rdma_ah_get_dlid(attr)) == HFI1_PKT_TYPE_16B)
2362 return HFI1_PKT_TYPE_16B;
2364 return hfi1_get_packet_type(lid);
2367 static inline void hfi1_make_ext_grh(struct hfi1_packet *packet,
2368 struct ib_grh *grh, u32 slid,
2371 struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2372 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2378 grh->sgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2379 if (slid == opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B))
2380 grh->sgid.global.interface_id =
2381 OPA_MAKE_ID(be32_to_cpu(OPA_LID_PERMISSIVE));
2383 grh->sgid.global.interface_id = OPA_MAKE_ID(slid);
2386 * Upper layers (like mad) may compare the dgid in the
2387 * wc that is obtained here with the sgid_index in
2388 * the wr. Since sgid_index in wr is always 0 for
2389 * extended lids, set the dgid here to the default
2392 grh->dgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2393 grh->dgid.global.interface_id =
2394 cpu_to_be64(ppd->guids[HFI1_PORT_GUID_INDEX]);
2397 static inline int hfi1_get_16b_padding(u32 hdr_size, u32 payload)
2399 return -(hdr_size + payload + (SIZE_OF_CRC << 2) +
2403 static inline void hfi1_make_ib_hdr(struct ib_header *hdr,
2407 hdr->lrh[0] = cpu_to_be16(lrh0);
2408 hdr->lrh[1] = cpu_to_be16(dlid);
2409 hdr->lrh[2] = cpu_to_be16(len);
2410 hdr->lrh[3] = cpu_to_be16(slid);
2413 static inline void hfi1_make_16b_hdr(struct hfi1_16b_header *hdr,
2416 bool becn, bool fecn, u8 l4,
2420 u32 lrh1 = 0x40000000;
2424 lrh0 = (lrh0 & ~OPA_16B_BECN_MASK) | (becn << OPA_16B_BECN_SHIFT);
2425 lrh0 = (lrh0 & ~OPA_16B_LEN_MASK) | (len << OPA_16B_LEN_SHIFT);
2426 lrh0 = (lrh0 & ~OPA_16B_LID_MASK) | (slid & OPA_16B_LID_MASK);
2427 lrh1 = (lrh1 & ~OPA_16B_FECN_MASK) | (fecn << OPA_16B_FECN_SHIFT);
2428 lrh1 = (lrh1 & ~OPA_16B_SC_MASK) | (sc << OPA_16B_SC_SHIFT);
2429 lrh1 = (lrh1 & ~OPA_16B_LID_MASK) | (dlid & OPA_16B_LID_MASK);
2430 lrh2 = (lrh2 & ~OPA_16B_SLID_MASK) |
2431 ((slid >> OPA_16B_SLID_SHIFT) << OPA_16B_SLID_HIGH_SHIFT);
2432 lrh2 = (lrh2 & ~OPA_16B_DLID_MASK) |
2433 ((dlid >> OPA_16B_DLID_SHIFT) << OPA_16B_DLID_HIGH_SHIFT);
2434 lrh2 = (lrh2 & ~OPA_16B_PKEY_MASK) | (pkey << OPA_16B_PKEY_SHIFT);
2435 lrh2 = (lrh2 & ~OPA_16B_L4_MASK) | l4;
2442 #endif /* _HFI1_KERNEL_H */