1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 * Copyright 2018-2019 Amazon.com, Inc. or its affiliates. All rights reserved.
7 #include "efa_regs_defs.h"
9 #define ADMIN_CMD_TIMEOUT_US 30000000 /* usecs */
11 #define EFA_REG_READ_TIMEOUT_US 50000 /* usecs */
12 #define EFA_MMIO_READ_INVALID 0xffffffff
14 #define EFA_POLL_INTERVAL_MS 100 /* msecs */
16 #define EFA_ASYNC_QUEUE_DEPTH 16
17 #define EFA_ADMIN_QUEUE_DEPTH 32
20 ((EFA_ADMIN_API_VERSION_MAJOR << EFA_REGS_VERSION_MAJOR_VERSION_SHIFT) | \
21 (EFA_ADMIN_API_VERSION_MINOR & EFA_REGS_VERSION_MINOR_VERSION_MASK))
23 #define EFA_CTRL_MAJOR 0
24 #define EFA_CTRL_MINOR 0
25 #define EFA_CTRL_SUB_MINOR 1
27 #define MIN_EFA_CTRL_VER \
28 (((EFA_CTRL_MAJOR) << \
29 (EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \
30 ((EFA_CTRL_MINOR) << \
31 (EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \
34 #define EFA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x)))
35 #define EFA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32))
37 #define EFA_REGS_ADMIN_INTR_MASK 1
45 struct completion wait_event;
46 struct efa_admin_acq_entry *user_cqe;
48 enum efa_cmd_status status;
49 /* status from the device */
55 static const char *efa_com_cmd_str(u8 cmd)
57 #define EFA_CMD_STR_CASE(_cmd) case EFA_ADMIN_##_cmd: return #_cmd
60 EFA_CMD_STR_CASE(CREATE_QP);
61 EFA_CMD_STR_CASE(MODIFY_QP);
62 EFA_CMD_STR_CASE(QUERY_QP);
63 EFA_CMD_STR_CASE(DESTROY_QP);
64 EFA_CMD_STR_CASE(CREATE_AH);
65 EFA_CMD_STR_CASE(DESTROY_AH);
66 EFA_CMD_STR_CASE(REG_MR);
67 EFA_CMD_STR_CASE(DEREG_MR);
68 EFA_CMD_STR_CASE(CREATE_CQ);
69 EFA_CMD_STR_CASE(DESTROY_CQ);
70 EFA_CMD_STR_CASE(GET_FEATURE);
71 EFA_CMD_STR_CASE(SET_FEATURE);
72 EFA_CMD_STR_CASE(GET_STATS);
73 EFA_CMD_STR_CASE(ALLOC_PD);
74 EFA_CMD_STR_CASE(DEALLOC_PD);
75 EFA_CMD_STR_CASE(ALLOC_UAR);
76 EFA_CMD_STR_CASE(DEALLOC_UAR);
77 default: return "unknown command opcode";
79 #undef EFA_CMD_STR_CASE
82 static u32 efa_com_reg_read32(struct efa_com_dev *edev, u16 offset)
84 struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
85 struct efa_admin_mmio_req_read_less_resp *read_resp;
86 unsigned long exp_time;
90 read_resp = mmio_read->read_resp;
92 spin_lock(&mmio_read->lock);
95 /* trash DMA req_id to identify when hardware is done */
96 read_resp->req_id = mmio_read->seq_num + 0x9aL;
97 mmio_read_reg = (offset << EFA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) &
98 EFA_REGS_MMIO_REG_READ_REG_OFF_MASK;
99 mmio_read_reg |= mmio_read->seq_num &
100 EFA_REGS_MMIO_REG_READ_REQ_ID_MASK;
102 writel(mmio_read_reg, edev->reg_bar + EFA_REGS_MMIO_REG_READ_OFF);
104 exp_time = jiffies + usecs_to_jiffies(mmio_read->mmio_read_timeout);
106 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num)
109 } while (time_is_after_jiffies(exp_time));
111 if (read_resp->req_id != mmio_read->seq_num) {
112 ibdev_err_ratelimited(
114 "Reading register timed out. expected: req id[%u] offset[%#x] actual: req id[%u] offset[%#x]\n",
115 mmio_read->seq_num, offset, read_resp->req_id,
117 err = EFA_MMIO_READ_INVALID;
121 if (read_resp->reg_off != offset) {
122 ibdev_err_ratelimited(
124 "Reading register failed: wrong offset provided\n");
125 err = EFA_MMIO_READ_INVALID;
129 err = read_resp->reg_val;
131 spin_unlock(&mmio_read->lock);
135 static int efa_com_admin_init_sq(struct efa_com_dev *edev)
137 struct efa_com_admin_queue *aq = &edev->aq;
138 struct efa_com_admin_sq *sq = &aq->sq;
139 u16 size = aq->depth * sizeof(*sq->entries);
145 dma_alloc_coherent(aq->dmadev, size, &sq->dma_addr, GFP_KERNEL);
149 spin_lock_init(&sq->lock);
155 sq->db_addr = (u32 __iomem *)(edev->reg_bar + EFA_REGS_AQ_PROD_DB_OFF);
157 addr_high = EFA_DMA_ADDR_TO_UINT32_HIGH(sq->dma_addr);
158 addr_low = EFA_DMA_ADDR_TO_UINT32_LOW(sq->dma_addr);
160 writel(addr_low, edev->reg_bar + EFA_REGS_AQ_BASE_LO_OFF);
161 writel(addr_high, edev->reg_bar + EFA_REGS_AQ_BASE_HI_OFF);
163 aq_caps = aq->depth & EFA_REGS_AQ_CAPS_AQ_DEPTH_MASK;
164 aq_caps |= (sizeof(struct efa_admin_aq_entry) <<
165 EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) &
166 EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK;
168 writel(aq_caps, edev->reg_bar + EFA_REGS_AQ_CAPS_OFF);
173 static int efa_com_admin_init_cq(struct efa_com_dev *edev)
175 struct efa_com_admin_queue *aq = &edev->aq;
176 struct efa_com_admin_cq *cq = &aq->cq;
177 u16 size = aq->depth * sizeof(*cq->entries);
183 dma_alloc_coherent(aq->dmadev, size, &cq->dma_addr, GFP_KERNEL);
187 spin_lock_init(&cq->lock);
192 addr_high = EFA_DMA_ADDR_TO_UINT32_HIGH(cq->dma_addr);
193 addr_low = EFA_DMA_ADDR_TO_UINT32_LOW(cq->dma_addr);
195 writel(addr_low, edev->reg_bar + EFA_REGS_ACQ_BASE_LO_OFF);
196 writel(addr_high, edev->reg_bar + EFA_REGS_ACQ_BASE_HI_OFF);
198 acq_caps = aq->depth & EFA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK;
199 acq_caps |= (sizeof(struct efa_admin_acq_entry) <<
200 EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) &
201 EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK;
202 acq_caps |= (aq->msix_vector_idx <<
203 EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_SHIFT) &
204 EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_MASK;
206 writel(acq_caps, edev->reg_bar + EFA_REGS_ACQ_CAPS_OFF);
211 static int efa_com_admin_init_aenq(struct efa_com_dev *edev,
212 struct efa_aenq_handlers *aenq_handlers)
214 struct efa_com_aenq *aenq = &edev->aenq;
215 u32 addr_low, addr_high, aenq_caps;
218 if (!aenq_handlers) {
219 ibdev_err(edev->efa_dev, "aenq handlers pointer is NULL\n");
223 size = EFA_ASYNC_QUEUE_DEPTH * sizeof(*aenq->entries);
224 aenq->entries = dma_alloc_coherent(edev->dmadev, size, &aenq->dma_addr,
229 aenq->aenq_handlers = aenq_handlers;
230 aenq->depth = EFA_ASYNC_QUEUE_DEPTH;
234 addr_low = EFA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr);
235 addr_high = EFA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr);
237 writel(addr_low, edev->reg_bar + EFA_REGS_AENQ_BASE_LO_OFF);
238 writel(addr_high, edev->reg_bar + EFA_REGS_AENQ_BASE_HI_OFF);
240 aenq_caps = aenq->depth & EFA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK;
241 aenq_caps |= (sizeof(struct efa_admin_aenq_entry) <<
242 EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) &
243 EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK;
244 aenq_caps |= (aenq->msix_vector_idx
245 << EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_SHIFT) &
246 EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_MASK;
247 writel(aenq_caps, edev->reg_bar + EFA_REGS_AENQ_CAPS_OFF);
250 * Init cons_db to mark that all entries in the queue
251 * are initially available
253 writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);
258 /* ID to be used with efa_com_get_comp_ctx */
259 static u16 efa_com_alloc_ctx_id(struct efa_com_admin_queue *aq)
263 spin_lock(&aq->comp_ctx_lock);
264 ctx_id = aq->comp_ctx_pool[aq->comp_ctx_pool_next];
265 aq->comp_ctx_pool_next++;
266 spin_unlock(&aq->comp_ctx_lock);
271 static void efa_com_dealloc_ctx_id(struct efa_com_admin_queue *aq,
274 spin_lock(&aq->comp_ctx_lock);
275 aq->comp_ctx_pool_next--;
276 aq->comp_ctx_pool[aq->comp_ctx_pool_next] = ctx_id;
277 spin_unlock(&aq->comp_ctx_lock);
280 static inline void efa_com_put_comp_ctx(struct efa_com_admin_queue *aq,
281 struct efa_comp_ctx *comp_ctx)
283 u16 cmd_id = comp_ctx->user_cqe->acq_common_descriptor.command &
284 EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
285 u16 ctx_id = cmd_id & (aq->depth - 1);
287 ibdev_dbg(aq->efa_dev, "Put completion command_id %#x\n", cmd_id);
288 comp_ctx->occupied = 0;
289 efa_com_dealloc_ctx_id(aq, ctx_id);
292 static struct efa_comp_ctx *efa_com_get_comp_ctx(struct efa_com_admin_queue *aq,
293 u16 cmd_id, bool capture)
295 u16 ctx_id = cmd_id & (aq->depth - 1);
297 if (aq->comp_ctx[ctx_id].occupied && capture) {
298 ibdev_err_ratelimited(
300 "Completion context for command_id %#x is occupied\n",
306 aq->comp_ctx[ctx_id].occupied = 1;
307 ibdev_dbg(aq->efa_dev,
308 "Take completion ctxt for command_id %#x\n", cmd_id);
311 return &aq->comp_ctx[ctx_id];
314 static struct efa_comp_ctx *__efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq,
315 struct efa_admin_aq_entry *cmd,
316 size_t cmd_size_in_bytes,
317 struct efa_admin_acq_entry *comp,
318 size_t comp_size_in_bytes)
320 struct efa_admin_aq_entry *aqe;
321 struct efa_comp_ctx *comp_ctx;
327 queue_size_mask = aq->depth - 1;
328 pi = aq->sq.pc & queue_size_mask;
330 ctx_id = efa_com_alloc_ctx_id(aq);
332 /* cmd_id LSBs are the ctx_id and MSBs are entropy bits from pc */
333 cmd_id = ctx_id & queue_size_mask;
334 cmd_id |= aq->sq.pc & ~queue_size_mask;
335 cmd_id &= EFA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
337 cmd->aq_common_descriptor.command_id = cmd_id;
338 cmd->aq_common_descriptor.flags |= aq->sq.phase &
339 EFA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
341 comp_ctx = efa_com_get_comp_ctx(aq, cmd_id, true);
343 efa_com_dealloc_ctx_id(aq, ctx_id);
344 return ERR_PTR(-EINVAL);
347 comp_ctx->status = EFA_CMD_SUBMITTED;
348 comp_ctx->comp_size = comp_size_in_bytes;
349 comp_ctx->user_cqe = comp;
350 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode;
352 reinit_completion(&comp_ctx->wait_event);
354 aqe = &aq->sq.entries[pi];
355 memset(aqe, 0, sizeof(*aqe));
356 memcpy(aqe, cmd, cmd_size_in_bytes);
359 atomic64_inc(&aq->stats.submitted_cmd);
361 if ((aq->sq.pc & queue_size_mask) == 0)
362 aq->sq.phase = !aq->sq.phase;
364 /* barrier not needed in case of writel */
365 writel(aq->sq.pc, aq->sq.db_addr);
370 static inline int efa_com_init_comp_ctxt(struct efa_com_admin_queue *aq)
372 size_t pool_size = aq->depth * sizeof(*aq->comp_ctx_pool);
373 size_t size = aq->depth * sizeof(struct efa_comp_ctx);
374 struct efa_comp_ctx *comp_ctx;
377 aq->comp_ctx = devm_kzalloc(aq->dmadev, size, GFP_KERNEL);
378 aq->comp_ctx_pool = devm_kzalloc(aq->dmadev, pool_size, GFP_KERNEL);
379 if (!aq->comp_ctx || !aq->comp_ctx_pool) {
380 devm_kfree(aq->dmadev, aq->comp_ctx_pool);
381 devm_kfree(aq->dmadev, aq->comp_ctx);
385 for (i = 0; i < aq->depth; i++) {
386 comp_ctx = efa_com_get_comp_ctx(aq, i, false);
388 init_completion(&comp_ctx->wait_event);
390 aq->comp_ctx_pool[i] = i;
393 spin_lock_init(&aq->comp_ctx_lock);
395 aq->comp_ctx_pool_next = 0;
400 static struct efa_comp_ctx *efa_com_submit_admin_cmd(struct efa_com_admin_queue *aq,
401 struct efa_admin_aq_entry *cmd,
402 size_t cmd_size_in_bytes,
403 struct efa_admin_acq_entry *comp,
404 size_t comp_size_in_bytes)
406 struct efa_comp_ctx *comp_ctx;
408 spin_lock(&aq->sq.lock);
409 if (!test_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state)) {
410 ibdev_err_ratelimited(aq->efa_dev, "Admin queue is closed\n");
411 spin_unlock(&aq->sq.lock);
412 return ERR_PTR(-ENODEV);
415 comp_ctx = __efa_com_submit_admin_cmd(aq, cmd, cmd_size_in_bytes, comp,
417 spin_unlock(&aq->sq.lock);
418 if (IS_ERR(comp_ctx))
419 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
424 static void efa_com_handle_single_admin_completion(struct efa_com_admin_queue *aq,
425 struct efa_admin_acq_entry *cqe)
427 struct efa_comp_ctx *comp_ctx;
430 cmd_id = cqe->acq_common_descriptor.command &
431 EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
433 comp_ctx = efa_com_get_comp_ctx(aq, cmd_id, false);
435 ibdev_err(aq->efa_dev,
436 "comp_ctx is NULL. Changing the admin queue running state\n");
437 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
441 comp_ctx->status = EFA_CMD_COMPLETED;
442 comp_ctx->comp_status = cqe->acq_common_descriptor.status;
443 if (comp_ctx->user_cqe)
444 memcpy(comp_ctx->user_cqe, cqe, comp_ctx->comp_size);
446 if (!test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state))
447 complete(&comp_ctx->wait_event);
450 static void efa_com_handle_admin_completion(struct efa_com_admin_queue *aq)
452 struct efa_admin_acq_entry *cqe;
458 queue_size_mask = aq->depth - 1;
460 ci = aq->cq.cc & queue_size_mask;
461 phase = aq->cq.phase;
463 cqe = &aq->cq.entries[ci];
465 /* Go over all the completions */
466 while ((READ_ONCE(cqe->acq_common_descriptor.flags) &
467 EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) {
469 * Do not read the rest of the completion entry before the
470 * phase bit was validated
473 efa_com_handle_single_admin_completion(aq, cqe);
477 if (ci == aq->depth) {
482 cqe = &aq->cq.entries[ci];
485 aq->cq.cc += comp_num;
486 aq->cq.phase = phase;
487 aq->sq.cc += comp_num;
488 atomic64_add(comp_num, &aq->stats.completed_cmd);
491 static int efa_com_comp_status_to_errno(u8 comp_status)
493 switch (comp_status) {
494 case EFA_ADMIN_SUCCESS:
496 case EFA_ADMIN_RESOURCE_ALLOCATION_FAILURE:
498 case EFA_ADMIN_UNSUPPORTED_OPCODE:
500 case EFA_ADMIN_BAD_OPCODE:
501 case EFA_ADMIN_MALFORMED_REQUEST:
502 case EFA_ADMIN_ILLEGAL_PARAMETER:
503 case EFA_ADMIN_UNKNOWN_ERROR:
510 static int efa_com_wait_and_process_admin_cq_polling(struct efa_comp_ctx *comp_ctx,
511 struct efa_com_admin_queue *aq)
513 unsigned long timeout;
517 timeout = jiffies + usecs_to_jiffies(aq->completion_timeout);
520 spin_lock_irqsave(&aq->cq.lock, flags);
521 efa_com_handle_admin_completion(aq);
522 spin_unlock_irqrestore(&aq->cq.lock, flags);
524 if (comp_ctx->status != EFA_CMD_SUBMITTED)
527 if (time_is_before_jiffies(timeout)) {
528 ibdev_err_ratelimited(
530 "Wait for completion (polling) timeout\n");
531 /* EFA didn't have any completion */
532 atomic64_inc(&aq->stats.no_completion);
534 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
539 msleep(aq->poll_interval);
542 err = efa_com_comp_status_to_errno(comp_ctx->comp_status);
544 efa_com_put_comp_ctx(aq, comp_ctx);
548 static int efa_com_wait_and_process_admin_cq_interrupts(struct efa_comp_ctx *comp_ctx,
549 struct efa_com_admin_queue *aq)
554 wait_for_completion_timeout(&comp_ctx->wait_event,
555 usecs_to_jiffies(aq->completion_timeout));
558 * In case the command wasn't completed find out the root cause.
559 * There might be 2 kinds of errors
560 * 1) No completion (timeout reached)
561 * 2) There is completion but the device didn't get any msi-x interrupt.
563 if (comp_ctx->status == EFA_CMD_SUBMITTED) {
564 spin_lock_irqsave(&aq->cq.lock, flags);
565 efa_com_handle_admin_completion(aq);
566 spin_unlock_irqrestore(&aq->cq.lock, flags);
568 atomic64_inc(&aq->stats.no_completion);
570 if (comp_ctx->status == EFA_CMD_COMPLETED)
571 ibdev_err_ratelimited(
573 "The device sent a completion but the driver didn't receive any MSI-X interrupt for admin cmd %s(%d) status %d (ctx: 0x%p, sq producer: %d, sq consumer: %d, cq consumer: %d)\n",
574 efa_com_cmd_str(comp_ctx->cmd_opcode),
575 comp_ctx->cmd_opcode, comp_ctx->status,
576 comp_ctx, aq->sq.pc, aq->sq.cc, aq->cq.cc);
578 ibdev_err_ratelimited(
580 "The device didn't send any completion for admin cmd %s(%d) status %d (ctx 0x%p, sq producer: %d, sq consumer: %d, cq consumer: %d)\n",
581 efa_com_cmd_str(comp_ctx->cmd_opcode),
582 comp_ctx->cmd_opcode, comp_ctx->status,
583 comp_ctx, aq->sq.pc, aq->sq.cc, aq->cq.cc);
585 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
590 err = efa_com_comp_status_to_errno(comp_ctx->comp_status);
592 efa_com_put_comp_ctx(aq, comp_ctx);
597 * There are two types to wait for completion.
598 * Polling mode - wait until the completion is available.
599 * Async mode - wait on wait queue until the completion is ready
600 * (or the timeout expired).
601 * It is expected that the IRQ called efa_com_handle_admin_completion
602 * to mark the completions.
604 static int efa_com_wait_and_process_admin_cq(struct efa_comp_ctx *comp_ctx,
605 struct efa_com_admin_queue *aq)
607 if (test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state))
608 return efa_com_wait_and_process_admin_cq_polling(comp_ctx, aq);
610 return efa_com_wait_and_process_admin_cq_interrupts(comp_ctx, aq);
614 * efa_com_cmd_exec - Execute admin command
616 * @cmd: the admin command to execute.
617 * @cmd_size: the command size.
618 * @comp: command completion return entry.
619 * @comp_size: command completion size.
620 * Submit an admin command and then wait until the device will return a
622 * The completion will be copied into comp.
624 * @return - 0 on success, negative value on failure.
626 int efa_com_cmd_exec(struct efa_com_admin_queue *aq,
627 struct efa_admin_aq_entry *cmd,
629 struct efa_admin_acq_entry *comp,
632 struct efa_comp_ctx *comp_ctx;
637 /* In case of queue FULL */
638 down(&aq->avail_cmds);
640 ibdev_dbg(aq->efa_dev, "%s (opcode %d)\n",
641 efa_com_cmd_str(cmd->aq_common_descriptor.opcode),
642 cmd->aq_common_descriptor.opcode);
643 comp_ctx = efa_com_submit_admin_cmd(aq, cmd, cmd_size, comp, comp_size);
644 if (IS_ERR(comp_ctx)) {
645 ibdev_err_ratelimited(
647 "Failed to submit command %s (opcode %u) err %ld\n",
648 efa_com_cmd_str(cmd->aq_common_descriptor.opcode),
649 cmd->aq_common_descriptor.opcode, PTR_ERR(comp_ctx));
652 return PTR_ERR(comp_ctx);
655 err = efa_com_wait_and_process_admin_cq(comp_ctx, aq);
657 ibdev_err_ratelimited(
659 "Failed to process command %s (opcode %u) comp_status %d err %d\n",
660 efa_com_cmd_str(cmd->aq_common_descriptor.opcode),
661 cmd->aq_common_descriptor.opcode, comp_ctx->comp_status,
670 * efa_com_admin_destroy - Destroy the admin and the async events queues.
671 * @edev: EFA communication layer struct
673 void efa_com_admin_destroy(struct efa_com_dev *edev)
675 struct efa_com_admin_queue *aq = &edev->aq;
676 struct efa_com_aenq *aenq = &edev->aenq;
677 struct efa_com_admin_cq *cq = &aq->cq;
678 struct efa_com_admin_sq *sq = &aq->sq;
681 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
683 devm_kfree(edev->dmadev, aq->comp_ctx_pool);
684 devm_kfree(edev->dmadev, aq->comp_ctx);
686 size = aq->depth * sizeof(*sq->entries);
687 dma_free_coherent(edev->dmadev, size, sq->entries, sq->dma_addr);
689 size = aq->depth * sizeof(*cq->entries);
690 dma_free_coherent(edev->dmadev, size, cq->entries, cq->dma_addr);
692 size = aenq->depth * sizeof(*aenq->entries);
693 dma_free_coherent(edev->dmadev, size, aenq->entries, aenq->dma_addr);
697 * efa_com_set_admin_polling_mode - Set the admin completion queue polling mode
698 * @edev: EFA communication layer struct
699 * @polling: Enable/Disable polling mode
701 * Set the admin completion mode.
703 void efa_com_set_admin_polling_mode(struct efa_com_dev *edev, bool polling)
708 mask_value = EFA_REGS_ADMIN_INTR_MASK;
710 writel(mask_value, edev->reg_bar + EFA_REGS_INTR_MASK_OFF);
712 set_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state);
714 clear_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state);
717 static void efa_com_stats_init(struct efa_com_dev *edev)
719 atomic64_t *s = (atomic64_t *)&edev->aq.stats;
722 for (i = 0; i < sizeof(edev->aq.stats) / sizeof(*s); i++, s++)
727 * efa_com_admin_init - Init the admin and the async queues
728 * @edev: EFA communication layer struct
729 * @aenq_handlers: Those handlers to be called upon event.
731 * Initialize the admin submission and completion queues.
732 * Initialize the asynchronous events notification queues.
734 * @return - 0 on success, negative value on failure.
736 int efa_com_admin_init(struct efa_com_dev *edev,
737 struct efa_aenq_handlers *aenq_handlers)
739 struct efa_com_admin_queue *aq = &edev->aq;
745 dev_sts = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF);
746 if (!(dev_sts & EFA_REGS_DEV_STS_READY_MASK)) {
747 ibdev_err(edev->efa_dev,
748 "Device isn't ready, abort com init %#x\n", dev_sts);
752 aq->depth = EFA_ADMIN_QUEUE_DEPTH;
754 aq->dmadev = edev->dmadev;
755 aq->efa_dev = edev->efa_dev;
756 set_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state);
758 sema_init(&aq->avail_cmds, aq->depth);
760 efa_com_stats_init(edev);
762 err = efa_com_init_comp_ctxt(aq);
766 err = efa_com_admin_init_sq(edev);
768 goto err_destroy_comp_ctxt;
770 err = efa_com_admin_init_cq(edev);
774 efa_com_set_admin_polling_mode(edev, false);
776 err = efa_com_admin_init_aenq(edev, aenq_handlers);
780 cap = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF);
781 timeout = (cap & EFA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
782 EFA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
784 /* the resolution of timeout reg is 100ms */
785 aq->completion_timeout = timeout * 100000;
787 aq->completion_timeout = ADMIN_CMD_TIMEOUT_US;
789 aq->poll_interval = EFA_POLL_INTERVAL_MS;
791 set_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state);
796 dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->cq.entries),
797 aq->cq.entries, aq->cq.dma_addr);
799 dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->sq.entries),
800 aq->sq.entries, aq->sq.dma_addr);
801 err_destroy_comp_ctxt:
802 devm_kfree(edev->dmadev, aq->comp_ctx);
808 * efa_com_admin_q_comp_intr_handler - admin queue interrupt handler
809 * @edev: EFA communication layer struct
811 * This method goes over the admin completion queue and wakes up
812 * all the pending threads that wait on the commands wait event.
814 * @note: Should be called after MSI-X interrupt.
816 void efa_com_admin_q_comp_intr_handler(struct efa_com_dev *edev)
820 spin_lock_irqsave(&edev->aq.cq.lock, flags);
821 efa_com_handle_admin_completion(&edev->aq);
822 spin_unlock_irqrestore(&edev->aq.cq.lock, flags);
826 * efa_handle_specific_aenq_event:
827 * return the handler that is relevant to the specific event group
829 static efa_aenq_handler efa_com_get_specific_aenq_cb(struct efa_com_dev *edev,
832 struct efa_aenq_handlers *aenq_handlers = edev->aenq.aenq_handlers;
834 if (group < EFA_MAX_HANDLERS && aenq_handlers->handlers[group])
835 return aenq_handlers->handlers[group];
837 return aenq_handlers->unimplemented_handler;
841 * efa_com_aenq_intr_handler - AENQ interrupt handler
842 * @edev: EFA communication layer struct
843 * @data: Data of interrupt handler.
845 * Go over the async event notification queue and call the proper aenq handler.
847 void efa_com_aenq_intr_handler(struct efa_com_dev *edev, void *data)
849 struct efa_admin_aenq_common_desc *aenq_common;
850 struct efa_com_aenq *aenq = &edev->aenq;
851 struct efa_admin_aenq_entry *aenq_e;
852 efa_aenq_handler handler_cb;
857 ci = aenq->cc & (aenq->depth - 1);
859 aenq_e = &aenq->entries[ci]; /* Get first entry */
860 aenq_common = &aenq_e->aenq_common_desc;
862 /* Go over all the events */
863 while ((READ_ONCE(aenq_common->flags) &
864 EFA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == phase) {
866 * Do not read the rest of the completion entry before the
867 * phase bit was validated
871 /* Handle specific event*/
872 handler_cb = efa_com_get_specific_aenq_cb(edev,
874 handler_cb(data, aenq_e); /* call the actual event handler*/
876 /* Get next event entry */
880 if (ci == aenq->depth) {
884 aenq_e = &aenq->entries[ci];
885 aenq_common = &aenq_e->aenq_common_desc;
888 aenq->cc += processed;
891 /* Don't update aenq doorbell if there weren't any processed events */
895 /* barrier not needed in case of writel */
896 writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);
899 static void efa_com_mmio_reg_read_resp_addr_init(struct efa_com_dev *edev)
901 struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
905 /* dma_addr_bits is unknown at this point */
906 addr_high = (mmio_read->read_resp_dma_addr >> 32) & GENMASK(31, 0);
907 addr_low = mmio_read->read_resp_dma_addr & GENMASK(31, 0);
909 writel(addr_high, edev->reg_bar + EFA_REGS_MMIO_RESP_HI_OFF);
910 writel(addr_low, edev->reg_bar + EFA_REGS_MMIO_RESP_LO_OFF);
913 int efa_com_mmio_reg_read_init(struct efa_com_dev *edev)
915 struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
917 spin_lock_init(&mmio_read->lock);
918 mmio_read->read_resp =
919 dma_alloc_coherent(edev->dmadev, sizeof(*mmio_read->read_resp),
920 &mmio_read->read_resp_dma_addr, GFP_KERNEL);
921 if (!mmio_read->read_resp)
924 efa_com_mmio_reg_read_resp_addr_init(edev);
926 mmio_read->read_resp->req_id = 0;
927 mmio_read->seq_num = 0;
928 mmio_read->mmio_read_timeout = EFA_REG_READ_TIMEOUT_US;
933 void efa_com_mmio_reg_read_destroy(struct efa_com_dev *edev)
935 struct efa_com_mmio_read *mmio_read = &edev->mmio_read;
937 dma_free_coherent(edev->dmadev, sizeof(*mmio_read->read_resp),
938 mmio_read->read_resp, mmio_read->read_resp_dma_addr);
941 int efa_com_validate_version(struct efa_com_dev *edev)
948 * Make sure the EFA version and the controller version are at least
949 * as the driver expects
951 ver = efa_com_reg_read32(edev, EFA_REGS_VERSION_OFF);
952 ctrl_ver = efa_com_reg_read32(edev,
953 EFA_REGS_CONTROLLER_VERSION_OFF);
955 ibdev_dbg(edev->efa_dev, "efa device version: %d.%d\n",
956 (ver & EFA_REGS_VERSION_MAJOR_VERSION_MASK) >>
957 EFA_REGS_VERSION_MAJOR_VERSION_SHIFT,
958 ver & EFA_REGS_VERSION_MINOR_VERSION_MASK);
960 if (ver < MIN_EFA_VER) {
961 ibdev_err(edev->efa_dev,
962 "EFA version is lower than the minimal version the driver supports\n");
966 ibdev_dbg(edev->efa_dev,
967 "efa controller version: %d.%d.%d implementation version %d\n",
968 (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >>
969 EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT,
970 (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >>
971 EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT,
972 (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK),
973 (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >>
974 EFA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT);
977 (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) |
978 (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) |
979 (ctrl_ver & EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK);
981 /* Validate the ctrl version without the implementation ID */
982 if (ctrl_ver_masked < MIN_EFA_CTRL_VER) {
983 ibdev_err(edev->efa_dev,
984 "EFA ctrl version is lower than the minimal ctrl version the driver supports\n");
992 * efa_com_get_dma_width - Retrieve physical dma address width the device
994 * @edev: EFA communication layer struct
996 * Retrieve the maximum physical address bits the device can handle.
998 * @return: > 0 on Success and negative value otherwise.
1000 int efa_com_get_dma_width(struct efa_com_dev *edev)
1002 u32 caps = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF);
1005 width = (caps & EFA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >>
1006 EFA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT;
1008 ibdev_dbg(edev->efa_dev, "DMA width: %d\n", width);
1010 if (width < 32 || width > 64) {
1011 ibdev_err(edev->efa_dev, "DMA width illegal value: %d\n", width);
1015 edev->dma_addr_bits = width;
1020 static int wait_for_reset_state(struct efa_com_dev *edev, u32 timeout,
1025 for (i = 0; i < timeout; i++) {
1026 val = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF);
1028 if ((val & EFA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) ==
1032 ibdev_dbg(edev->efa_dev, "Reset indication val %d\n", val);
1033 msleep(EFA_POLL_INTERVAL_MS);
1040 * efa_com_dev_reset - Perform device FLR to the device.
1041 * @edev: EFA communication layer struct
1042 * @reset_reason: Specify what is the trigger for the reset in case of an error.
1044 * @return - 0 on success, negative value on failure.
1046 int efa_com_dev_reset(struct efa_com_dev *edev,
1047 enum efa_regs_reset_reason_types reset_reason)
1049 u32 stat, timeout, cap, reset_val;
1052 stat = efa_com_reg_read32(edev, EFA_REGS_DEV_STS_OFF);
1053 cap = efa_com_reg_read32(edev, EFA_REGS_CAPS_OFF);
1055 if (!(stat & EFA_REGS_DEV_STS_READY_MASK)) {
1056 ibdev_err(edev->efa_dev,
1057 "Device isn't ready, can't reset device\n");
1061 timeout = (cap & EFA_REGS_CAPS_RESET_TIMEOUT_MASK) >>
1062 EFA_REGS_CAPS_RESET_TIMEOUT_SHIFT;
1064 ibdev_err(edev->efa_dev, "Invalid timeout value\n");
1069 reset_val = EFA_REGS_DEV_CTL_DEV_RESET_MASK;
1070 reset_val |= (reset_reason << EFA_REGS_DEV_CTL_RESET_REASON_SHIFT) &
1071 EFA_REGS_DEV_CTL_RESET_REASON_MASK;
1072 writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);
1074 /* reset clears the mmio readless address, restore it */
1075 efa_com_mmio_reg_read_resp_addr_init(edev);
1077 err = wait_for_reset_state(edev, timeout,
1078 EFA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK);
1080 ibdev_err(edev->efa_dev, "Reset indication didn't turn on\n");
1085 writel(0, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);
1086 err = wait_for_reset_state(edev, timeout, 0);
1088 ibdev_err(edev->efa_dev, "Reset indication didn't turn off\n");
1092 timeout = (cap & EFA_REGS_CAPS_ADMIN_CMD_TO_MASK) >>
1093 EFA_REGS_CAPS_ADMIN_CMD_TO_SHIFT;
1095 /* the resolution of timeout reg is 100ms */
1096 edev->aq.completion_timeout = timeout * 100000;
1098 edev->aq.completion_timeout = ADMIN_CMD_TIMEOUT_US;