1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
3 * Copyright 2018-2021 Amazon.com, Inc. or its affiliates. All rights reserved.
6 #ifndef _EFA_ADMIN_CMDS_H_
7 #define _EFA_ADMIN_CMDS_H_
9 #define EFA_ADMIN_API_VERSION_MAJOR 0
10 #define EFA_ADMIN_API_VERSION_MINOR 1
12 /* EFA admin queue opcodes */
13 enum efa_admin_aq_opcode {
14 EFA_ADMIN_CREATE_QP = 1,
15 EFA_ADMIN_MODIFY_QP = 2,
16 EFA_ADMIN_QUERY_QP = 3,
17 EFA_ADMIN_DESTROY_QP = 4,
18 EFA_ADMIN_CREATE_AH = 5,
19 EFA_ADMIN_DESTROY_AH = 6,
21 EFA_ADMIN_DEREG_MR = 8,
22 EFA_ADMIN_CREATE_CQ = 9,
23 EFA_ADMIN_DESTROY_CQ = 10,
24 EFA_ADMIN_GET_FEATURE = 11,
25 EFA_ADMIN_SET_FEATURE = 12,
26 EFA_ADMIN_GET_STATS = 13,
27 EFA_ADMIN_ALLOC_PD = 14,
28 EFA_ADMIN_DEALLOC_PD = 15,
29 EFA_ADMIN_ALLOC_UAR = 16,
30 EFA_ADMIN_DEALLOC_UAR = 17,
31 EFA_ADMIN_MAX_OPCODE = 17,
34 enum efa_admin_aq_feature_id {
35 EFA_ADMIN_DEVICE_ATTR = 1,
36 EFA_ADMIN_AENQ_CONFIG = 2,
37 EFA_ADMIN_NETWORK_ATTR = 3,
38 EFA_ADMIN_QUEUE_ATTR = 4,
39 EFA_ADMIN_HW_HINTS = 5,
40 EFA_ADMIN_HOST_INFO = 6,
43 /* QP transport type */
44 enum efa_admin_qp_type {
45 /* Unreliable Datagram */
46 EFA_ADMIN_QP_TYPE_UD = 1,
47 /* Scalable Reliable Datagram */
48 EFA_ADMIN_QP_TYPE_SRD = 2,
52 enum efa_admin_qp_state {
53 EFA_ADMIN_QP_STATE_RESET = 0,
54 EFA_ADMIN_QP_STATE_INIT = 1,
55 EFA_ADMIN_QP_STATE_RTR = 2,
56 EFA_ADMIN_QP_STATE_RTS = 3,
57 EFA_ADMIN_QP_STATE_SQD = 4,
58 EFA_ADMIN_QP_STATE_SQE = 5,
59 EFA_ADMIN_QP_STATE_ERR = 6,
62 enum efa_admin_get_stats_type {
63 EFA_ADMIN_GET_STATS_TYPE_BASIC = 0,
64 EFA_ADMIN_GET_STATS_TYPE_MESSAGES = 1,
65 EFA_ADMIN_GET_STATS_TYPE_RDMA_READ = 2,
68 enum efa_admin_get_stats_scope {
69 EFA_ADMIN_GET_STATS_SCOPE_ALL = 0,
70 EFA_ADMIN_GET_STATS_SCOPE_QUEUE = 1,
74 * QP allocation sizes, converted by fabric QueuePair (QP) create command
75 * from QP capabilities.
77 struct efa_admin_qp_alloc_size {
78 /* Send descriptor ring size in bytes */
79 u32 send_queue_ring_size;
81 /* Max number of WQEs that can be outstanding on send queue. */
85 * Recv descriptor ring size in bytes, sufficient for user-provided
88 u32 recv_queue_ring_size;
90 /* Max number of WQEs that can be outstanding on recv queue */
94 struct efa_admin_create_qp_cmd {
95 /* Common Admin Queue descriptor */
96 struct efa_admin_aq_common_desc aq_common_desc;
98 /* Protection Domain associated with this QP */
105 * 0 : sq_virt - If set, SQ ring base address is
106 * virtual (IOVA returned by MR registration)
107 * 1 : rq_virt - If set, RQ ring base address is
108 * virtual (IOVA returned by MR registration)
109 * 7:2 : reserved - MBZ
114 * Send queue (SQ) ring base physical address. This field is not
115 * used if this is a Low Latency Queue(LLQ).
119 /* Receive queue (RQ) ring base address. */
122 /* Index of CQ to be associated with Send Queue completions */
125 /* Index of CQ to be associated with Recv Queue completions */
129 * Memory registration key for the SQ ring, used only when not in
130 * LLQ mode and base address is virtual
135 * Memory registration key for the RQ ring, used only when base
140 /* Requested QP allocation sizes */
141 struct efa_admin_qp_alloc_size qp_alloc_size;
153 struct efa_admin_create_qp_resp {
154 /* Common Admin Queue completion descriptor */
155 struct efa_admin_acq_common_desc acq_common_desc;
158 * Opaque handle to be used for consequent admin operations on the
164 * QP number in the given EFA virtual device. Least-significant bits (as
165 * needed according to max_qp) carry unique QP ID
172 /* Index of sub-CQ for Send Queue completions */
175 /* Index of sub-CQ for Receive Queue completions */
178 /* SQ doorbell address, as offset to PCIe DB BAR */
181 /* RQ doorbell address, as offset to PCIe DB BAR */
185 * low latency send queue ring base address as an offset to PCIe
188 u32 llq_descriptors_offset;
191 struct efa_admin_modify_qp_cmd {
192 /* Common Admin Queue descriptor */
193 struct efa_admin_aq_common_desc aq_common_desc;
196 * Mask indicating which fields should be updated
201 * 4 : sq_drained_async_notify
207 /* QP handle returned by create_qp command */
213 /* Override current QP state (before applying the transition) */
222 /* Enable async notification when SQ is drained */
223 u8 sq_drained_async_notify;
225 /* Number of RNR retries (valid only for SRD QPs) */
232 struct efa_admin_modify_qp_resp {
233 /* Common Admin Queue completion descriptor */
234 struct efa_admin_acq_common_desc acq_common_desc;
237 struct efa_admin_query_qp_cmd {
238 /* Common Admin Queue descriptor */
239 struct efa_admin_aq_common_desc aq_common_desc;
241 /* QP handle returned by create_qp command */
245 struct efa_admin_query_qp_resp {
246 /* Common Admin Queue completion descriptor */
247 struct efa_admin_acq_common_desc acq_common_desc;
258 /* Indicates that draining is in progress */
261 /* Number of RNR retries (valid only for SRD QPs) */
268 struct efa_admin_destroy_qp_cmd {
269 /* Common Admin Queue descriptor */
270 struct efa_admin_aq_common_desc aq_common_desc;
272 /* QP handle returned by create_qp command */
276 struct efa_admin_destroy_qp_resp {
277 /* Common Admin Queue completion descriptor */
278 struct efa_admin_acq_common_desc acq_common_desc;
282 * Create Address Handle command parameters. Must not be called more than
283 * once for the same destination
285 struct efa_admin_create_ah_cmd {
286 /* Common Admin Queue descriptor */
287 struct efa_admin_aq_common_desc aq_common_desc;
289 /* Destination address in network byte order */
299 struct efa_admin_create_ah_resp {
300 /* Common Admin Queue completion descriptor */
301 struct efa_admin_acq_common_desc acq_common_desc;
303 /* Target interface address handle (opaque) */
310 struct efa_admin_destroy_ah_cmd {
311 /* Common Admin Queue descriptor */
312 struct efa_admin_aq_common_desc aq_common_desc;
314 /* Target interface address handle (opaque) */
321 struct efa_admin_destroy_ah_resp {
322 /* Common Admin Queue completion descriptor */
323 struct efa_admin_acq_common_desc acq_common_desc;
327 * Registration of MemoryRegion, required for QP working with Virtual
328 * Addresses. In standard verbs semantics, region length is limited to 2GB
329 * space, but EFA offers larger MR support for large memory space, to ease
330 * on users working with very large datasets (i.e. full GPU memory mapping).
332 struct efa_admin_reg_mr_cmd {
333 /* Common Admin Queue descriptor */
334 struct efa_admin_aq_common_desc aq_common_desc;
336 /* Protection Domain */
342 /* Physical Buffer List, each element is page-aligned. */
345 * Inline array of guest-physical page addresses of user
346 * memory pages (optimization for short region
349 u64 inline_pbl_array[4];
351 /* points to PBL (direct or indirect, chained if needed) */
352 struct efa_admin_ctrl_buff_info pbl;
355 /* Memory region length, in bytes. */
359 * flags and page size
360 * 4:0 : phys_page_size_shift - page size is (1 <<
361 * phys_page_size_shift). Page size is used for
362 * building the Virtual to Physical address mapping
363 * 6:5 : reserved - MBZ
364 * 7 : mem_addr_phy_mode_en - Enable bit for physical
365 * memory registration (no translation), can be used
366 * only by privileged clients. If set, PBL must
367 * contain a single entry.
373 * 0 : local_write_enable - Local write permissions:
374 * must be set for RQ buffers and buffers posted for
376 * 1 : reserved1 - MBZ
377 * 2 : remote_read_enable - Remote read permissions:
378 * must be set to enable RDMA read from the region
379 * 7:3 : reserved2 - MBZ
386 /* number of pages in PBL (redundant, could be calculated) */
390 * IO Virtual Address associated with this MR. If
391 * mem_addr_phy_mode_en is set, contains the physical address of
397 struct efa_admin_reg_mr_resp {
398 /* Common Admin Queue completion descriptor */
399 struct efa_admin_acq_common_desc acq_common_desc;
402 * L_Key, to be used in conjunction with local buffer references in
403 * SQ and RQ WQE, or with virtual RQ/CQ rings
408 * R_Key, to be used in RDMA messages to refer to remotely accessed
414 struct efa_admin_dereg_mr_cmd {
415 /* Common Admin Queue descriptor */
416 struct efa_admin_aq_common_desc aq_common_desc;
418 /* L_Key, memory region's l_key */
422 struct efa_admin_dereg_mr_resp {
423 /* Common Admin Queue completion descriptor */
424 struct efa_admin_acq_common_desc acq_common_desc;
427 struct efa_admin_create_cq_cmd {
428 struct efa_admin_aq_common_desc aq_common_desc;
431 * 4:0 : reserved5 - MBZ
432 * 5 : interrupt_mode_enabled - if set, cq operates
433 * in interrupt mode (i.e. CQ events and MSI-X are
434 * generated), otherwise - polling
435 * 6 : virt - If set, ring base address is virtual
436 * (IOVA returned by MR registration)
437 * 7 : reserved6 - MBZ
442 * 4:0 : cq_entry_size_words - size of CQ entry in
443 * 32-bit words, valid values: 4, 8.
444 * 7:5 : reserved7 - MBZ
448 /* completion queue depth in # of entries. must be power of 2 */
451 /* msix vector assigned to this cq */
455 * CQ ring base address, virtual or physical depending on 'virt'
458 struct efa_common_mem_addr cq_ba;
461 * Memory registration key for the ring, used only when base
467 * number of sub cqs - must be equal to sub_cqs_per_cq of queue
476 struct efa_admin_create_cq_resp {
477 struct efa_admin_acq_common_desc acq_common_desc;
481 /* actual cq depth in number of entries */
485 struct efa_admin_destroy_cq_cmd {
486 struct efa_admin_aq_common_desc aq_common_desc;
494 struct efa_admin_destroy_cq_resp {
495 struct efa_admin_acq_common_desc acq_common_desc;
499 * EFA AQ Get Statistics command. Extended statistics are placed in control
500 * buffer pointed by AQ entry
502 struct efa_admin_aq_get_stats_cmd {
503 struct efa_admin_aq_common_desc aq_common_descriptor;
506 /* command specific inline data */
507 u32 inline_data_w1[3];
509 struct efa_admin_ctrl_buff_info control_buffer;
512 /* stats type as defined in enum efa_admin_get_stats_type */
515 /* stats scope defined in enum efa_admin_get_stats_scope */
521 struct efa_admin_basic_stats {
533 struct efa_admin_messages_stats {
543 struct efa_admin_rdma_read_stats {
553 struct efa_admin_acq_get_stats_resp {
554 struct efa_admin_acq_common_desc acq_common_desc;
557 struct efa_admin_basic_stats basic_stats;
559 struct efa_admin_messages_stats messages_stats;
561 struct efa_admin_rdma_read_stats rdma_read_stats;
565 struct efa_admin_get_set_feature_common_desc {
569 /* as appears in efa_admin_aq_feature_id */
576 struct efa_admin_feature_device_attr_desc {
577 /* Bitmap of efa_admin_aq_feature_id */
578 u64 supported_features;
580 /* Bitmap of supported page sizes in MR registrations */
585 u32 admin_api_version;
589 /* Bar used for SQ and RQ doorbells */
592 /* Indicates how many bits are used on physical address access */
595 /* Indicates how many bits are used on virtual address access */
599 * 0 : rdma_read - If set, RDMA Read is supported on
601 * 1 : rnr_retry - If set, RNR retry is supported on
603 * 31:2 : reserved - MBZ
607 /* Max RDMA transfer size in bytes */
611 struct efa_admin_feature_queue_attr_desc {
612 /* The maximum number of queue pairs supported */
615 /* Maximum number of WQEs per Send Queue */
618 /* Maximum size of data that can be sent inline in a Send WQE */
621 /* Maximum number of buffer descriptors per Recv Queue */
624 /* The maximum number of completion queues supported per VF */
627 /* Maximum number of CQEs per Completion Queue */
630 /* Number of sub-CQs to be created for each CQ */
633 /* Minimum number of WQEs per SQ */
636 /* Maximum number of SGEs (buffers) allowed for a single send WQE */
637 u16 max_wr_send_sges;
639 /* Maximum number of SGEs allowed for a single recv WQE */
640 u16 max_wr_recv_sges;
642 /* The maximum number of memory regions supported */
645 /* The maximum number of pages can be registered */
648 /* The maximum number of protection domains supported */
651 /* The maximum number of address handles supported */
654 /* The maximum size of LLQ in bytes */
657 /* Maximum number of SGEs for a single RDMA read WQE */
658 u16 max_wr_rdma_sges;
661 * Maximum number of bytes that can be written to SQ between two
662 * consecutive doorbells (in units of 64B). Driver must ensure that only
663 * complete WQEs are written to queue before issuing a doorbell.
664 * Examples: max_tx_batch=16 and WQE size = 64B, means up to 16 WQEs can
665 * be written to SQ between two consecutive doorbells. max_tx_batch=11
666 * and WQE size = 128B, means up to 5 WQEs can be written to SQ between
667 * two consecutive doorbells. Zero means unlimited.
672 struct efa_admin_feature_aenq_desc {
673 /* bitmask for AENQ groups the device can report */
674 u32 supported_groups;
676 /* bitmask for AENQ groups to report */
680 struct efa_admin_feature_network_attr_desc {
681 /* Raw address data in network byte order */
684 /* max packet payload size in bytes */
689 * When hint value is 0, hints capabilities are not supported or driver
690 * should use its own predefined value
692 struct efa_admin_hw_hints {
694 u16 mmio_read_timeout;
697 u16 driver_watchdog_timeout;
700 u16 admin_completion_timeout;
702 /* poll interval in ms */
706 struct efa_admin_get_feature_cmd {
707 struct efa_admin_aq_common_desc aq_common_descriptor;
709 struct efa_admin_ctrl_buff_info control_buffer;
711 struct efa_admin_get_set_feature_common_desc feature_common;
716 struct efa_admin_get_feature_resp {
717 struct efa_admin_acq_common_desc acq_common_desc;
722 struct efa_admin_feature_device_attr_desc device_attr;
724 struct efa_admin_feature_aenq_desc aenq;
726 struct efa_admin_feature_network_attr_desc network_attr;
728 struct efa_admin_feature_queue_attr_desc queue_attr;
730 struct efa_admin_hw_hints hw_hints;
734 struct efa_admin_set_feature_cmd {
735 struct efa_admin_aq_common_desc aq_common_descriptor;
737 struct efa_admin_ctrl_buff_info control_buffer;
739 struct efa_admin_get_set_feature_common_desc feature_common;
744 /* AENQ configuration */
745 struct efa_admin_feature_aenq_desc aenq;
749 struct efa_admin_set_feature_resp {
750 struct efa_admin_acq_common_desc acq_common_desc;
757 struct efa_admin_alloc_pd_cmd {
758 struct efa_admin_aq_common_desc aq_common_descriptor;
761 struct efa_admin_alloc_pd_resp {
762 struct efa_admin_acq_common_desc acq_common_desc;
771 struct efa_admin_dealloc_pd_cmd {
772 struct efa_admin_aq_common_desc aq_common_descriptor;
781 struct efa_admin_dealloc_pd_resp {
782 struct efa_admin_acq_common_desc acq_common_desc;
785 struct efa_admin_alloc_uar_cmd {
786 struct efa_admin_aq_common_desc aq_common_descriptor;
789 struct efa_admin_alloc_uar_resp {
790 struct efa_admin_acq_common_desc acq_common_desc;
799 struct efa_admin_dealloc_uar_cmd {
800 struct efa_admin_aq_common_desc aq_common_descriptor;
809 struct efa_admin_dealloc_uar_resp {
810 struct efa_admin_acq_common_desc acq_common_desc;
813 /* asynchronous event notification groups */
814 enum efa_admin_aenq_group {
815 EFA_ADMIN_FATAL_ERROR = 1,
816 EFA_ADMIN_WARNING = 2,
817 EFA_ADMIN_NOTIFICATION = 3,
818 EFA_ADMIN_KEEP_ALIVE = 4,
819 EFA_ADMIN_AENQ_GROUPS_NUM = 5,
822 struct efa_admin_mmio_req_read_less_resp {
827 /* value is valid when poll is cleared */
831 enum efa_admin_os_type {
832 EFA_ADMIN_OS_LINUX = 0,
835 struct efa_admin_host_info {
836 /* OS distribution string format */
839 /* Defined in enum efa_admin_os_type */
842 /* Kernel version string format */
843 u8 kernel_ver_str[32];
845 /* Kernel version numeric format */
849 * 7:0 : driver_module_type
850 * 15:8 : driver_sub_minor
851 * 23:16 : driver_minor
852 * 31:24 : driver_major
857 * Device's Bus, Device and Function
872 * 0 : intree - Intree driver
873 * 1 : gdr - GPUDirect RDMA supported
880 #define EFA_ADMIN_CREATE_QP_CMD_SQ_VIRT_MASK BIT(0)
881 #define EFA_ADMIN_CREATE_QP_CMD_RQ_VIRT_MASK BIT(1)
884 #define EFA_ADMIN_MODIFY_QP_CMD_QP_STATE_MASK BIT(0)
885 #define EFA_ADMIN_MODIFY_QP_CMD_CUR_QP_STATE_MASK BIT(1)
886 #define EFA_ADMIN_MODIFY_QP_CMD_QKEY_MASK BIT(2)
887 #define EFA_ADMIN_MODIFY_QP_CMD_SQ_PSN_MASK BIT(3)
888 #define EFA_ADMIN_MODIFY_QP_CMD_SQ_DRAINED_ASYNC_NOTIFY_MASK BIT(4)
889 #define EFA_ADMIN_MODIFY_QP_CMD_RNR_RETRY_MASK BIT(5)
892 #define EFA_ADMIN_REG_MR_CMD_PHYS_PAGE_SIZE_SHIFT_MASK GENMASK(4, 0)
893 #define EFA_ADMIN_REG_MR_CMD_MEM_ADDR_PHY_MODE_EN_MASK BIT(7)
894 #define EFA_ADMIN_REG_MR_CMD_LOCAL_WRITE_ENABLE_MASK BIT(0)
895 #define EFA_ADMIN_REG_MR_CMD_REMOTE_READ_ENABLE_MASK BIT(2)
898 #define EFA_ADMIN_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
899 #define EFA_ADMIN_CREATE_CQ_CMD_VIRT_MASK BIT(6)
900 #define EFA_ADMIN_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
902 /* feature_device_attr_desc */
903 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RDMA_READ_MASK BIT(0)
904 #define EFA_ADMIN_FEATURE_DEVICE_ATTR_DESC_RNR_RETRY_MASK BIT(1)
907 #define EFA_ADMIN_HOST_INFO_DRIVER_MODULE_TYPE_MASK GENMASK(7, 0)
908 #define EFA_ADMIN_HOST_INFO_DRIVER_SUB_MINOR_MASK GENMASK(15, 8)
909 #define EFA_ADMIN_HOST_INFO_DRIVER_MINOR_MASK GENMASK(23, 16)
910 #define EFA_ADMIN_HOST_INFO_DRIVER_MAJOR_MASK GENMASK(31, 24)
911 #define EFA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
912 #define EFA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
913 #define EFA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
914 #define EFA_ADMIN_HOST_INFO_SPEC_MINOR_MASK GENMASK(7, 0)
915 #define EFA_ADMIN_HOST_INFO_SPEC_MAJOR_MASK GENMASK(15, 8)
916 #define EFA_ADMIN_HOST_INFO_INTREE_MASK BIT(0)
917 #define EFA_ADMIN_HOST_INFO_GDR_MASK BIT(1)
919 #endif /* _EFA_ADMIN_CMDS_H_ */