drivers/infiniband/hw/bnxt_re/qplib_res.h

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: QPLib resource manager (header)
  37  */
  38
  39 #ifndef __BNXT_QPLIB_RES_H__
  40 #define __BNXT_QPLIB_RES_H__
  41
  42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
  43
  44 #define CHIP_NUM_57508          0x1750
  45 #define CHIP_NUM_57504          0x1751
  46 #define CHIP_NUM_57502          0x1752
  47
  48 struct bnxt_qplib_drv_modes {
  49         u8      wqe_mode;
  50         /* Other modes to follow here */
  51 };
  52
  53 struct bnxt_qplib_chip_ctx {
  54         u16     chip_num;
  55         u8      chip_rev;
  56         u8      chip_metal;
  57         struct bnxt_qplib_drv_modes modes;
  58 };
  59
  60 #define PTR_CNT_PER_PG          (PAGE_SIZE / sizeof(void *))
  61 #define PTR_MAX_IDX_PER_PG      (PTR_CNT_PER_PG - 1)
  62 #define PTR_PG(x)               (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
  63 #define PTR_IDX(x)              ((x) & PTR_MAX_IDX_PER_PG)
  64
  65 #define HWQ_CMP(idx, hwq)       ((idx) & ((hwq)->max_elements - 1))
  66
  67 #define HWQ_FREE_SLOTS(hwq)     (hwq->max_elements - \
  68                                 ((HWQ_CMP(hwq->prod, hwq)\
  69                                 - HWQ_CMP(hwq->cons, hwq))\
  70                                 & (hwq->max_elements - 1)))
  71 enum bnxt_qplib_hwq_type {
  72         HWQ_TYPE_CTX,
  73         HWQ_TYPE_QUEUE,
  74         HWQ_TYPE_L2_CMPL,
  75         HWQ_TYPE_MR
  76 };
  77
  78 #define MAX_PBL_LVL_0_PGS               1
  79 #define MAX_PBL_LVL_1_PGS               512
  80 #define MAX_PBL_LVL_1_PGS_SHIFT         9
  81 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2     256
  82 #define MAX_PBL_LVL_2_PGS               (256 * 512)
  83 #define MAX_PDL_LVL_SHIFT               9
  84
  85 enum bnxt_qplib_pbl_lvl {
  86         PBL_LVL_0,
  87         PBL_LVL_1,
  88         PBL_LVL_2,
  89         PBL_LVL_MAX
  90 };
  91
  92 #define ROCE_PG_SIZE_4K         (4 * 1024)
  93 #define ROCE_PG_SIZE_8K         (8 * 1024)
  94 #define ROCE_PG_SIZE_64K        (64 * 1024)
  95 #define ROCE_PG_SIZE_2M         (2 * 1024 * 1024)
  96 #define ROCE_PG_SIZE_8M         (8 * 1024 * 1024)
  97 #define ROCE_PG_SIZE_1G         (1024 * 1024 * 1024)
  98
  99 enum bnxt_qplib_hwrm_pg_size {
 100         BNXT_QPLIB_HWRM_PG_SIZE_4K      = 0,
 101         BNXT_QPLIB_HWRM_PG_SIZE_8K      = 1,
 102         BNXT_QPLIB_HWRM_PG_SIZE_64K     = 2,
 103         BNXT_QPLIB_HWRM_PG_SIZE_2M      = 3,
 104         BNXT_QPLIB_HWRM_PG_SIZE_8M      = 4,
 105         BNXT_QPLIB_HWRM_PG_SIZE_1G      = 5,
 106 };
 107
 108 struct bnxt_qplib_reg_desc {
 109         u8              bar_id;
 110         resource_size_t bar_base;
 111         void __iomem    *bar_reg;
 112         size_t          len;
 113 };
 114
 115 struct bnxt_qplib_pbl {
 116         u32                             pg_count;
 117         u32                             pg_size;
 118         void                            **pg_arr;
 119         dma_addr_t                      *pg_map_arr;
 120 };
 121
 122 struct bnxt_qplib_sg_info {
 123         struct ib_umem                  *umem;
 124         u32                             npages;
 125         u32                             pgshft;
 126         u32                             pgsize;
 127         bool                            nopte;
 128 };
 129
 130 struct bnxt_qplib_hwq_attr {
 131         struct bnxt_qplib_res           *res;
 132         struct bnxt_qplib_sg_info       *sginfo;
 133         enum bnxt_qplib_hwq_type        type;
 134         u32                             depth;
 135         u32                             stride;
 136         u32                             aux_stride;
 137         u32                             aux_depth;
 138 };
 139
 140 struct bnxt_qplib_hwq {
 141         struct pci_dev                  *pdev;
 142         /* lock to protect qplib_hwq */
 143         spinlock_t                      lock;
 144         struct bnxt_qplib_pbl           pbl[PBL_LVL_MAX + 1];
 145         enum bnxt_qplib_pbl_lvl         level;          /* 0, 1, or 2 */
 146         /* ptr for easy access to the PBL entries */
 147         void                            **pbl_ptr;
 148         /* ptr for easy access to the dma_addr */
 149         dma_addr_t                      *pbl_dma_ptr;
 150         u32                             max_elements;
 151         u32                             depth;
 152         u16                             element_size;   /* Size of each entry */
 153         u16                             qe_ppg; /* queue entry per page */
 154
 155         u32                             prod;           /* raw */
 156         u32                             cons;           /* raw */
 157         u8                              cp_bit;
 158         u8                              is_user;
 159         u64                             *pad_pg;
 160         u32                             pad_stride;
 161         u32                             pad_pgofft;
 162 };
 163
 164 struct bnxt_qplib_db_info {
 165         void __iomem            *db;
 166         void __iomem            *priv_db;
 167         struct bnxt_qplib_hwq   *hwq;
 168         u32                     xid;
 169         u32                     max_slot;
 170 };
 171
 172 /* Tables */
 173 struct bnxt_qplib_pd_tbl {
 174         unsigned long                   *tbl;
 175         u32                             max;
 176 };
 177
 178 struct bnxt_qplib_sgid_tbl {
 179         struct bnxt_qplib_gid_info      *tbl;
 180         u16                             *hw_id;
 181         u16                             max;
 182         u16                             active;
 183         void                            *ctx;
 184         u8                              *vlan;
 185 };
 186
 187 struct bnxt_qplib_pkey_tbl {
 188         u16                             *tbl;
 189         u16                             max;
 190         u16                             active;
 191 };
 192
 193 struct bnxt_qplib_dpi {
 194         u32                             dpi;
 195         void __iomem                    *dbr;
 196         u64                             umdbr;
 197 };
 198
 199 struct bnxt_qplib_dpi_tbl {
 200         void                            **app_tbl;
 201         unsigned long                   *tbl;
 202         u16                             max;
 203         void __iomem                    *dbr_bar_reg_iomem;
 204         u64                             unmapped_dbr;
 205 };
 206
 207 struct bnxt_qplib_stats {
 208         dma_addr_t                      dma_map;
 209         void                            *dma;
 210         u32                             size;
 211         u32                             fw_id;
 212 };
 213
 214 struct bnxt_qplib_vf_res {
 215         u32 max_qp_per_vf;
 216         u32 max_mrw_per_vf;
 217         u32 max_srq_per_vf;
 218         u32 max_cq_per_vf;
 219         u32 max_gid_per_vf;
 220 };
 221
 222 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE        448
 223 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE       64
 224 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE        64
 225 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE       128
 226
 227 #define MAX_TQM_ALLOC_REQ               48
 228 #define MAX_TQM_ALLOC_BLK_SIZE          8
 229 struct bnxt_qplib_tqm_ctx {
 230         struct bnxt_qplib_hwq           pde;
 231         u8                              pde_level; /* Original level */
 232         struct bnxt_qplib_hwq           qtbl[MAX_TQM_ALLOC_REQ];
 233         u8                              qcount[MAX_TQM_ALLOC_REQ];
 234 };
 235
 236 struct bnxt_qplib_ctx {
 237         u32                             qpc_count;
 238         struct bnxt_qplib_hwq           qpc_tbl;
 239         u32                             mrw_count;
 240         struct bnxt_qplib_hwq           mrw_tbl;
 241         u32                             srqc_count;
 242         struct bnxt_qplib_hwq           srqc_tbl;
 243         u32                             cq_count;
 244         struct bnxt_qplib_hwq           cq_tbl;
 245         struct bnxt_qplib_hwq           tim_tbl;
 246         struct bnxt_qplib_tqm_ctx       tqm_ctx;
 247         struct bnxt_qplib_stats         stats;
 248         struct bnxt_qplib_vf_res        vf_res;
 249         u64                             hwrm_intf_ver;
 250 };
 251
 252 struct bnxt_qplib_res {
 253         struct pci_dev                  *pdev;
 254         struct bnxt_qplib_chip_ctx      *cctx;
 255         struct net_device               *netdev;
 256
 257         struct bnxt_qplib_rcfw          *rcfw;
 258         struct bnxt_qplib_pd_tbl        pd_tbl;
 259         struct bnxt_qplib_sgid_tbl      sgid_tbl;
 260         struct bnxt_qplib_pkey_tbl      pkey_tbl;
 261         struct bnxt_qplib_dpi_tbl       dpi_tbl;
 262         bool                            prio;
 263 };
 264
 265 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
 266 {
 267         return (cctx->chip_num == CHIP_NUM_57508 ||
 268                 cctx->chip_num == CHIP_NUM_57504 ||
 269                 cctx->chip_num == CHIP_NUM_57502);
 270 }
 271
 272 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
 273 {
 274         return bnxt_qplib_is_chip_gen_p5(res->cctx) ?
 275                                         HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
 276 }
 277
 278 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
 279 {
 280         return bnxt_qplib_is_chip_gen_p5(cctx) ?
 281                RING_ALLOC_REQ_RING_TYPE_NQ :
 282                RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
 283 }
 284
 285 static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq)
 286 {
 287         u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
 288         struct bnxt_qplib_pbl *pbl;
 289
 290         pbl = &hwq->pbl[PBL_LVL_0];
 291         switch (pbl->pg_size) {
 292         case ROCE_PG_SIZE_4K:
 293                 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
 294                 break;
 295         case ROCE_PG_SIZE_8K:
 296                 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K;
 297                 break;
 298         case ROCE_PG_SIZE_64K:
 299                 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K;
 300                 break;
 301         case ROCE_PG_SIZE_2M:
 302                 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M;
 303                 break;
 304         case ROCE_PG_SIZE_8M:
 305                 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M;
 306                 break;
 307         case ROCE_PG_SIZE_1G:
 308                 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G;
 309                 break;
 310         default:
 311                 break;
 312         }
 313
 314         return pg_size;
 315 }
 316
 317 static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq,
 318                                       u32 indx, u64 *pg)
 319 {
 320         u32 pg_num, pg_idx;
 321
 322         pg_num = (indx / hwq->qe_ppg);
 323         pg_idx = (indx % hwq->qe_ppg);
 324         if (pg)
 325                 *pg = (u64)&hwq->pbl_ptr[pg_num];
 326         return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx);
 327 }
 328
 329 static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx)
 330 {
 331         idx += hwq->prod;
 332         if (idx >= hwq->depth)
 333                 idx -= hwq->depth;
 334         return bnxt_qplib_get_qe(hwq, idx, NULL);
 335 }
 336
 337 #define to_bnxt_qplib(ptr, type, member)        \
 338         container_of(ptr, type, member)
 339
 340 struct bnxt_qplib_pd;
 341 struct bnxt_qplib_dev_attr;
 342
 343 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res,
 344                          struct bnxt_qplib_hwq *hwq);
 345 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
 346                               struct bnxt_qplib_hwq_attr *hwq_attr);
 347 void bnxt_qplib_get_guid(u8 *dev_addr, u8 *guid);
 348 int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl,
 349                         struct bnxt_qplib_pd *pd);
 350 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
 351                           struct bnxt_qplib_pd_tbl *pd_tbl,
 352                           struct bnxt_qplib_pd *pd);
 353 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit,
 354                          struct bnxt_qplib_dpi     *dpi,
 355                          void                      *app);
 356 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
 357                            struct bnxt_qplib_dpi_tbl *dpi_tbl,
 358                            struct bnxt_qplib_dpi *dpi);
 359 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
 360 int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
 361 void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
 362 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
 363                          struct net_device *netdev,
 364                          struct bnxt_qplib_dev_attr *dev_attr);
 365 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res,
 366                          struct bnxt_qplib_ctx *ctx);
 367 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
 368                          struct bnxt_qplib_ctx *ctx,
 369                          bool virt_fn, bool is_p5);
 370 int bnxt_qplib_determine_atomics(struct pci_dev *dev);
 371
 372 static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt)
 373 {
 374         hwq->prod = (hwq->prod + cnt) % hwq->depth;
 375 }
 376
 377 static inline void bnxt_qplib_hwq_incr_cons(struct bnxt_qplib_hwq *hwq,
 378                                             u32 cnt)
 379 {
 380         hwq->cons = (hwq->cons + cnt) % hwq->depth;
 381 }
 382
 383 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info,
 384                                         bool arm)
 385 {
 386         u32 key;
 387
 388         key = info->hwq->cons & (info->hwq->max_elements - 1);
 389         key |= (CMPL_DOORBELL_IDX_VALID |
 390                 (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK));
 391         if (!arm)
 392                 key |= CMPL_DOORBELL_MASK;
 393         writel(key, info->db);
 394 }
 395
 396 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info,
 397                                       u32 type)
 398 {
 399         u64 key = 0;
 400
 401         key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
 402         key <<= 32;
 403         key |= (info->hwq->cons & (info->hwq->max_elements - 1)) &
 404                 DBC_DBC_INDEX_MASK;
 405         writeq(key, info->db);
 406 }
 407
 408 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info,
 409                                            u32 type)
 410 {
 411         u64 key = 0;
 412
 413         key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
 414         key <<= 32;
 415         key |= ((info->hwq->prod / info->max_slot)) & DBC_DBC_INDEX_MASK;
 416         writeq(key, info->db);
 417 }
 418
 419 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info,
 420                                        u32 type)
 421 {
 422         u64 key = 0;
 423
 424         key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
 425         key <<= 32;
 426         writeq(key, info->priv_db);
 427 }
 428
 429 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info,
 430                                          u32 th)
 431 {
 432         u64 key = 0;
 433
 434         key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th;
 435         key <<= 32;
 436         key |=  th & DBC_DBC_INDEX_MASK;
 437         writeq(key, info->priv_db);
 438 }
 439
 440 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info,
 441                                          struct bnxt_qplib_chip_ctx *cctx,
 442                                          bool arm)
 443 {
 444         u32 type;
 445
 446         type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
 447         if (bnxt_qplib_is_chip_gen_p5(cctx))
 448                 bnxt_qplib_ring_db(info, type);
 449         else
 450                 bnxt_qplib_ring_db32(info, arm);
 451 }
 452 #endif /* __BNXT_QPLIB_RES_H__ */