2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
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14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
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34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Description: QPLib resource manager (header)
39 #ifndef __BNXT_QPLIB_RES_H__
40 #define __BNXT_QPLIB_RES_H__
42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
44 #define CHIP_NUM_57508 0x1750
45 #define CHIP_NUM_57504 0x1751
46 #define CHIP_NUM_57502 0x1752
48 enum bnxt_qplib_wqe_mode {
49 BNXT_QPLIB_WQE_MODE_STATIC = 0x00,
50 BNXT_QPLIB_WQE_MODE_VARIABLE = 0x01,
51 BNXT_QPLIB_WQE_MODE_INVALID = 0x02
54 struct bnxt_qplib_drv_modes {
56 /* Other modes to follow here */
59 struct bnxt_qplib_chip_ctx {
63 struct bnxt_qplib_drv_modes modes;
66 #define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *))
67 #define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1)
68 #define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
69 #define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG)
71 #define HWQ_CMP(idx, hwq) ((idx) & ((hwq)->max_elements - 1))
73 #define HWQ_FREE_SLOTS(hwq) (hwq->max_elements - \
74 ((HWQ_CMP(hwq->prod, hwq)\
75 - HWQ_CMP(hwq->cons, hwq))\
76 & (hwq->max_elements - 1)))
77 enum bnxt_qplib_hwq_type {
84 #define MAX_PBL_LVL_0_PGS 1
85 #define MAX_PBL_LVL_1_PGS 512
86 #define MAX_PBL_LVL_1_PGS_SHIFT 9
87 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256
88 #define MAX_PBL_LVL_2_PGS (256 * 512)
89 #define MAX_PDL_LVL_SHIFT 9
91 enum bnxt_qplib_pbl_lvl {
98 #define ROCE_PG_SIZE_4K (4 * 1024)
99 #define ROCE_PG_SIZE_8K (8 * 1024)
100 #define ROCE_PG_SIZE_64K (64 * 1024)
101 #define ROCE_PG_SIZE_2M (2 * 1024 * 1024)
102 #define ROCE_PG_SIZE_8M (8 * 1024 * 1024)
103 #define ROCE_PG_SIZE_1G (1024 * 1024 * 1024)
105 enum bnxt_qplib_hwrm_pg_size {
106 BNXT_QPLIB_HWRM_PG_SIZE_4K = 0,
107 BNXT_QPLIB_HWRM_PG_SIZE_8K = 1,
108 BNXT_QPLIB_HWRM_PG_SIZE_64K = 2,
109 BNXT_QPLIB_HWRM_PG_SIZE_2M = 3,
110 BNXT_QPLIB_HWRM_PG_SIZE_8M = 4,
111 BNXT_QPLIB_HWRM_PG_SIZE_1G = 5,
114 struct bnxt_qplib_reg_desc {
116 resource_size_t bar_base;
117 void __iomem *bar_reg;
121 struct bnxt_qplib_pbl {
125 dma_addr_t *pg_map_arr;
128 struct bnxt_qplib_sg_info {
129 struct ib_umem *umem;
136 struct bnxt_qplib_hwq_attr {
137 struct bnxt_qplib_res *res;
138 struct bnxt_qplib_sg_info *sginfo;
139 enum bnxt_qplib_hwq_type type;
146 struct bnxt_qplib_hwq {
147 struct pci_dev *pdev;
148 /* lock to protect qplib_hwq */
150 struct bnxt_qplib_pbl pbl[PBL_LVL_MAX + 1];
151 enum bnxt_qplib_pbl_lvl level; /* 0, 1, or 2 */
152 /* ptr for easy access to the PBL entries */
154 /* ptr for easy access to the dma_addr */
155 dma_addr_t *pbl_dma_ptr;
158 u16 element_size; /* Size of each entry */
159 u16 qe_ppg; /* queue entry per page */
170 struct bnxt_qplib_db_info {
172 void __iomem *priv_db;
173 struct bnxt_qplib_hwq *hwq;
179 struct bnxt_qplib_pd_tbl {
184 struct bnxt_qplib_sgid_tbl {
185 struct bnxt_qplib_gid_info *tbl;
193 struct bnxt_qplib_pkey_tbl {
199 struct bnxt_qplib_dpi {
205 struct bnxt_qplib_dpi_tbl {
209 void __iomem *dbr_bar_reg_iomem;
213 struct bnxt_qplib_stats {
220 struct bnxt_qplib_vf_res {
228 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE 448
229 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE 64
230 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE 64
231 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE 128
233 #define MAX_TQM_ALLOC_REQ 48
234 #define MAX_TQM_ALLOC_BLK_SIZE 8
235 struct bnxt_qplib_tqm_ctx {
236 struct bnxt_qplib_hwq pde;
237 u8 pde_level; /* Original level */
238 struct bnxt_qplib_hwq qtbl[MAX_TQM_ALLOC_REQ];
239 u8 qcount[MAX_TQM_ALLOC_REQ];
242 struct bnxt_qplib_ctx {
244 struct bnxt_qplib_hwq qpc_tbl;
246 struct bnxt_qplib_hwq mrw_tbl;
248 struct bnxt_qplib_hwq srqc_tbl;
250 struct bnxt_qplib_hwq cq_tbl;
251 struct bnxt_qplib_hwq tim_tbl;
252 struct bnxt_qplib_tqm_ctx tqm_ctx;
253 struct bnxt_qplib_stats stats;
254 struct bnxt_qplib_vf_res vf_res;
258 struct bnxt_qplib_res {
259 struct pci_dev *pdev;
260 struct bnxt_qplib_chip_ctx *cctx;
261 struct net_device *netdev;
263 struct bnxt_qplib_rcfw *rcfw;
264 struct bnxt_qplib_pd_tbl pd_tbl;
265 struct bnxt_qplib_sgid_tbl sgid_tbl;
266 struct bnxt_qplib_pkey_tbl pkey_tbl;
267 struct bnxt_qplib_dpi_tbl dpi_tbl;
271 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
273 return (cctx->chip_num == CHIP_NUM_57508 ||
274 cctx->chip_num == CHIP_NUM_57504 ||
275 cctx->chip_num == CHIP_NUM_57502);
278 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
280 return bnxt_qplib_is_chip_gen_p5(res->cctx) ?
281 HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
284 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
286 return bnxt_qplib_is_chip_gen_p5(cctx) ?
287 RING_ALLOC_REQ_RING_TYPE_NQ :
288 RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
291 static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq)
293 u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
294 struct bnxt_qplib_pbl *pbl;
296 pbl = &hwq->pbl[PBL_LVL_0];
297 switch (pbl->pg_size) {
298 case ROCE_PG_SIZE_4K:
299 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
301 case ROCE_PG_SIZE_8K:
302 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K;
304 case ROCE_PG_SIZE_64K:
305 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K;
307 case ROCE_PG_SIZE_2M:
308 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M;
310 case ROCE_PG_SIZE_8M:
311 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M;
313 case ROCE_PG_SIZE_1G:
314 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G;
323 static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq,
328 pg_num = (indx / hwq->qe_ppg);
329 pg_idx = (indx % hwq->qe_ppg);
331 *pg = (u64)&hwq->pbl_ptr[pg_num];
332 return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx);
335 static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx)
338 if (idx >= hwq->depth)
340 return bnxt_qplib_get_qe(hwq, idx, NULL);
343 #define to_bnxt_qplib(ptr, type, member) \
344 container_of(ptr, type, member)
346 struct bnxt_qplib_pd;
347 struct bnxt_qplib_dev_attr;
349 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res,
350 struct bnxt_qplib_hwq *hwq);
351 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
352 struct bnxt_qplib_hwq_attr *hwq_attr);
353 void bnxt_qplib_get_guid(u8 *dev_addr, u8 *guid);
354 int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl,
355 struct bnxt_qplib_pd *pd);
356 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
357 struct bnxt_qplib_pd_tbl *pd_tbl,
358 struct bnxt_qplib_pd *pd);
359 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit,
360 struct bnxt_qplib_dpi *dpi,
362 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
363 struct bnxt_qplib_dpi_tbl *dpi_tbl,
364 struct bnxt_qplib_dpi *dpi);
365 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
366 int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
367 void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
368 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
369 struct net_device *netdev,
370 struct bnxt_qplib_dev_attr *dev_attr);
371 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res,
372 struct bnxt_qplib_ctx *ctx);
373 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
374 struct bnxt_qplib_ctx *ctx,
375 bool virt_fn, bool is_p5);
377 static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt)
379 hwq->prod = (hwq->prod + cnt) % hwq->depth;
382 static inline void bnxt_qplib_hwq_incr_cons(struct bnxt_qplib_hwq *hwq,
385 hwq->cons = (hwq->cons + cnt) % hwq->depth;
388 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info,
393 key = info->hwq->cons & (info->hwq->max_elements - 1);
394 key |= (CMPL_DOORBELL_IDX_VALID |
395 (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK));
397 key |= CMPL_DOORBELL_MASK;
398 writel(key, info->db);
401 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info,
406 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
408 key |= (info->hwq->cons & (info->hwq->max_elements - 1)) &
410 writeq(key, info->db);
413 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info,
418 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
420 key |= ((info->hwq->prod / info->max_slot)) & DBC_DBC_INDEX_MASK;
421 writeq(key, info->db);
424 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info,
429 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
431 writeq(key, info->priv_db);
434 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info,
439 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th;
441 key |= th & DBC_DBC_INDEX_MASK;
442 writeq(key, info->priv_db);
445 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info,
446 struct bnxt_qplib_chip_ctx *cctx,
451 type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
452 if (bnxt_qplib_is_chip_gen_p5(cctx))
453 bnxt_qplib_ring_db(info, type);
455 bnxt_qplib_ring_db32(info, arm);
457 #endif /* __BNXT_QPLIB_RES_H__ */