2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
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14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
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34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Description: QPLib resource manager (header)
39 #ifndef __BNXT_QPLIB_RES_H__
40 #define __BNXT_QPLIB_RES_H__
42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
44 #define CHIP_NUM_57508 0x1750
45 #define CHIP_NUM_57504 0x1751
46 #define CHIP_NUM_57502 0x1752
48 struct bnxt_qplib_drv_modes {
50 /* Other modes to follow here */
53 struct bnxt_qplib_chip_ctx {
57 struct bnxt_qplib_drv_modes modes;
60 #define PTR_CNT_PER_PG (PAGE_SIZE / sizeof(void *))
61 #define PTR_MAX_IDX_PER_PG (PTR_CNT_PER_PG - 1)
62 #define PTR_PG(x) (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
63 #define PTR_IDX(x) ((x) & PTR_MAX_IDX_PER_PG)
65 #define HWQ_CMP(idx, hwq) ((idx) & ((hwq)->max_elements - 1))
67 #define HWQ_FREE_SLOTS(hwq) (hwq->max_elements - \
68 ((HWQ_CMP(hwq->prod, hwq)\
69 - HWQ_CMP(hwq->cons, hwq))\
70 & (hwq->max_elements - 1)))
71 enum bnxt_qplib_hwq_type {
78 #define MAX_PBL_LVL_0_PGS 1
79 #define MAX_PBL_LVL_1_PGS 512
80 #define MAX_PBL_LVL_1_PGS_SHIFT 9
81 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2 256
82 #define MAX_PBL_LVL_2_PGS (256 * 512)
83 #define MAX_PDL_LVL_SHIFT 9
85 enum bnxt_qplib_pbl_lvl {
92 #define ROCE_PG_SIZE_4K (4 * 1024)
93 #define ROCE_PG_SIZE_8K (8 * 1024)
94 #define ROCE_PG_SIZE_64K (64 * 1024)
95 #define ROCE_PG_SIZE_2M (2 * 1024 * 1024)
96 #define ROCE_PG_SIZE_8M (8 * 1024 * 1024)
97 #define ROCE_PG_SIZE_1G (1024 * 1024 * 1024)
99 enum bnxt_qplib_hwrm_pg_size {
100 BNXT_QPLIB_HWRM_PG_SIZE_4K = 0,
101 BNXT_QPLIB_HWRM_PG_SIZE_8K = 1,
102 BNXT_QPLIB_HWRM_PG_SIZE_64K = 2,
103 BNXT_QPLIB_HWRM_PG_SIZE_2M = 3,
104 BNXT_QPLIB_HWRM_PG_SIZE_8M = 4,
105 BNXT_QPLIB_HWRM_PG_SIZE_1G = 5,
108 struct bnxt_qplib_reg_desc {
110 resource_size_t bar_base;
111 void __iomem *bar_reg;
115 struct bnxt_qplib_pbl {
119 dma_addr_t *pg_map_arr;
122 struct bnxt_qplib_sg_info {
123 struct ib_umem *umem;
130 struct bnxt_qplib_hwq_attr {
131 struct bnxt_qplib_res *res;
132 struct bnxt_qplib_sg_info *sginfo;
133 enum bnxt_qplib_hwq_type type;
140 struct bnxt_qplib_hwq {
141 struct pci_dev *pdev;
142 /* lock to protect qplib_hwq */
144 struct bnxt_qplib_pbl pbl[PBL_LVL_MAX + 1];
145 enum bnxt_qplib_pbl_lvl level; /* 0, 1, or 2 */
146 /* ptr for easy access to the PBL entries */
148 /* ptr for easy access to the dma_addr */
149 dma_addr_t *pbl_dma_ptr;
152 u16 element_size; /* Size of each entry */
153 u16 qe_ppg; /* queue entry per page */
164 struct bnxt_qplib_db_info {
166 void __iomem *priv_db;
167 struct bnxt_qplib_hwq *hwq;
173 struct bnxt_qplib_pd_tbl {
178 struct bnxt_qplib_sgid_tbl {
179 struct bnxt_qplib_gid_info *tbl;
187 struct bnxt_qplib_pkey_tbl {
193 struct bnxt_qplib_dpi {
199 struct bnxt_qplib_dpi_tbl {
203 void __iomem *dbr_bar_reg_iomem;
207 struct bnxt_qplib_stats {
214 struct bnxt_qplib_vf_res {
222 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE 448
223 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE 64
224 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE 64
225 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE 128
227 #define MAX_TQM_ALLOC_REQ 48
228 #define MAX_TQM_ALLOC_BLK_SIZE 8
229 struct bnxt_qplib_tqm_ctx {
230 struct bnxt_qplib_hwq pde;
231 u8 pde_level; /* Original level */
232 struct bnxt_qplib_hwq qtbl[MAX_TQM_ALLOC_REQ];
233 u8 qcount[MAX_TQM_ALLOC_REQ];
236 struct bnxt_qplib_ctx {
238 struct bnxt_qplib_hwq qpc_tbl;
240 struct bnxt_qplib_hwq mrw_tbl;
242 struct bnxt_qplib_hwq srqc_tbl;
244 struct bnxt_qplib_hwq cq_tbl;
245 struct bnxt_qplib_hwq tim_tbl;
246 struct bnxt_qplib_tqm_ctx tqm_ctx;
247 struct bnxt_qplib_stats stats;
248 struct bnxt_qplib_vf_res vf_res;
252 struct bnxt_qplib_res {
253 struct pci_dev *pdev;
254 struct bnxt_qplib_chip_ctx *cctx;
255 struct net_device *netdev;
257 struct bnxt_qplib_rcfw *rcfw;
258 struct bnxt_qplib_pd_tbl pd_tbl;
259 struct bnxt_qplib_sgid_tbl sgid_tbl;
260 struct bnxt_qplib_pkey_tbl pkey_tbl;
261 struct bnxt_qplib_dpi_tbl dpi_tbl;
265 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
267 return (cctx->chip_num == CHIP_NUM_57508 ||
268 cctx->chip_num == CHIP_NUM_57504 ||
269 cctx->chip_num == CHIP_NUM_57502);
272 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
274 return bnxt_qplib_is_chip_gen_p5(res->cctx) ?
275 HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
278 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
280 return bnxt_qplib_is_chip_gen_p5(cctx) ?
281 RING_ALLOC_REQ_RING_TYPE_NQ :
282 RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
285 static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq)
287 u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
288 struct bnxt_qplib_pbl *pbl;
290 pbl = &hwq->pbl[PBL_LVL_0];
291 switch (pbl->pg_size) {
292 case ROCE_PG_SIZE_4K:
293 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
295 case ROCE_PG_SIZE_8K:
296 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K;
298 case ROCE_PG_SIZE_64K:
299 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K;
301 case ROCE_PG_SIZE_2M:
302 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M;
304 case ROCE_PG_SIZE_8M:
305 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M;
307 case ROCE_PG_SIZE_1G:
308 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G;
317 static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq,
322 pg_num = (indx / hwq->qe_ppg);
323 pg_idx = (indx % hwq->qe_ppg);
325 *pg = (u64)&hwq->pbl_ptr[pg_num];
326 return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx);
329 static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx)
332 if (idx >= hwq->depth)
334 return bnxt_qplib_get_qe(hwq, idx, NULL);
337 #define to_bnxt_qplib(ptr, type, member) \
338 container_of(ptr, type, member)
340 struct bnxt_qplib_pd;
341 struct bnxt_qplib_dev_attr;
343 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res,
344 struct bnxt_qplib_hwq *hwq);
345 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
346 struct bnxt_qplib_hwq_attr *hwq_attr);
347 void bnxt_qplib_get_guid(u8 *dev_addr, u8 *guid);
348 int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl,
349 struct bnxt_qplib_pd *pd);
350 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
351 struct bnxt_qplib_pd_tbl *pd_tbl,
352 struct bnxt_qplib_pd *pd);
353 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit,
354 struct bnxt_qplib_dpi *dpi,
356 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
357 struct bnxt_qplib_dpi_tbl *dpi_tbl,
358 struct bnxt_qplib_dpi *dpi);
359 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
360 int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
361 void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
362 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
363 struct net_device *netdev,
364 struct bnxt_qplib_dev_attr *dev_attr);
365 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res,
366 struct bnxt_qplib_ctx *ctx);
367 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
368 struct bnxt_qplib_ctx *ctx,
369 bool virt_fn, bool is_p5);
370 int bnxt_qplib_determine_atomics(struct pci_dev *dev);
372 static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt)
374 hwq->prod = (hwq->prod + cnt) % hwq->depth;
377 static inline void bnxt_qplib_hwq_incr_cons(struct bnxt_qplib_hwq *hwq,
380 hwq->cons = (hwq->cons + cnt) % hwq->depth;
383 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info,
388 key = info->hwq->cons & (info->hwq->max_elements - 1);
389 key |= (CMPL_DOORBELL_IDX_VALID |
390 (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK));
392 key |= CMPL_DOORBELL_MASK;
393 writel(key, info->db);
396 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info,
401 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
403 key |= (info->hwq->cons & (info->hwq->max_elements - 1)) &
405 writeq(key, info->db);
408 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info,
413 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
415 key |= ((info->hwq->prod / info->max_slot)) & DBC_DBC_INDEX_MASK;
416 writeq(key, info->db);
419 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info,
424 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
426 writeq(key, info->priv_db);
429 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info,
434 key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th;
436 key |= th & DBC_DBC_INDEX_MASK;
437 writeq(key, info->priv_db);
440 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info,
441 struct bnxt_qplib_chip_ctx *cctx,
446 type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
447 if (bnxt_qplib_is_chip_gen_p5(cctx))
448 bnxt_qplib_ring_db(info, type);
450 bnxt_qplib_ring_db32(info, arm);
452 #endif /* __BNXT_QPLIB_RES_H__ */