drivers/infiniband/hw/bnxt_re/qplib_res.h

   1 /*
   2  * Broadcom NetXtreme-E RoCE driver.
   3  *
   4  * Copyright (c) 2016 - 2017, Broadcom. All rights reserved.  The term
   5  * Broadcom refers to Broadcom Limited and/or its subsidiaries.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * BSD license below:
  12  *
  13  * Redistribution and use in source and binary forms, with or without
  14  * modification, are permitted provided that the following conditions
  15  * are met:
  16  *
  17  * 1. Redistributions of source code must retain the above copyright
  18  *    notice, this list of conditions and the following disclaimer.
  19  * 2. Redistributions in binary form must reproduce the above copyright
  20  *    notice, this list of conditions and the following disclaimer in
  21  *    the documentation and/or other materials provided with the
  22  *    distribution.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  25  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
  28  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  29  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  31  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  33  * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  34  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  *
  36  * Description: QPLib resource manager (header)
  37  */
  38
  39 #ifndef __BNXT_QPLIB_RES_H__
  40 #define __BNXT_QPLIB_RES_H__
  41
  42 extern const struct bnxt_qplib_gid bnxt_qplib_gid_zero;
  43
  44 #define CHIP_NUM_57508          0x1750
  45 #define CHIP_NUM_57504          0x1751
  46 #define CHIP_NUM_57502          0x1752
  47
  48 enum bnxt_qplib_wqe_mode {
  49         BNXT_QPLIB_WQE_MODE_STATIC      = 0x00,
  50         BNXT_QPLIB_WQE_MODE_VARIABLE    = 0x01,
  51         BNXT_QPLIB_WQE_MODE_INVALID     = 0x02
  52 };
  53
  54 struct bnxt_qplib_drv_modes {
  55         u8      wqe_mode;
  56         /* Other modes to follow here */
  57 };
  58
  59 struct bnxt_qplib_chip_ctx {
  60         u16     chip_num;
  61         u8      chip_rev;
  62         u8      chip_metal;
  63         struct bnxt_qplib_drv_modes modes;
  64 };
  65
  66 #define PTR_CNT_PER_PG          (PAGE_SIZE / sizeof(void *))
  67 #define PTR_MAX_IDX_PER_PG      (PTR_CNT_PER_PG - 1)
  68 #define PTR_PG(x)               (((x) & ~PTR_MAX_IDX_PER_PG) / PTR_CNT_PER_PG)
  69 #define PTR_IDX(x)              ((x) & PTR_MAX_IDX_PER_PG)
  70
  71 #define HWQ_CMP(idx, hwq)       ((idx) & ((hwq)->max_elements - 1))
  72
  73 #define HWQ_FREE_SLOTS(hwq)     (hwq->max_elements - \
  74                                 ((HWQ_CMP(hwq->prod, hwq)\
  75                                 - HWQ_CMP(hwq->cons, hwq))\
  76                                 & (hwq->max_elements - 1)))
  77 enum bnxt_qplib_hwq_type {
  78         HWQ_TYPE_CTX,
  79         HWQ_TYPE_QUEUE,
  80         HWQ_TYPE_L2_CMPL,
  81         HWQ_TYPE_MR
  82 };
  83
  84 #define MAX_PBL_LVL_0_PGS               1
  85 #define MAX_PBL_LVL_1_PGS               512
  86 #define MAX_PBL_LVL_1_PGS_SHIFT         9
  87 #define MAX_PBL_LVL_1_PGS_FOR_LVL_2     256
  88 #define MAX_PBL_LVL_2_PGS               (256 * 512)
  89 #define MAX_PDL_LVL_SHIFT               9
  90
  91 enum bnxt_qplib_pbl_lvl {
  92         PBL_LVL_0,
  93         PBL_LVL_1,
  94         PBL_LVL_2,
  95         PBL_LVL_MAX
  96 };
  97
  98 #define ROCE_PG_SIZE_4K         (4 * 1024)
  99 #define ROCE_PG_SIZE_8K         (8 * 1024)
 100 #define ROCE_PG_SIZE_64K        (64 * 1024)
 101 #define ROCE_PG_SIZE_2M         (2 * 1024 * 1024)
 102 #define ROCE_PG_SIZE_8M         (8 * 1024 * 1024)
 103 #define ROCE_PG_SIZE_1G         (1024 * 1024 * 1024)
 104
 105 enum bnxt_qplib_hwrm_pg_size {
 106         BNXT_QPLIB_HWRM_PG_SIZE_4K      = 0,
 107         BNXT_QPLIB_HWRM_PG_SIZE_8K      = 1,
 108         BNXT_QPLIB_HWRM_PG_SIZE_64K     = 2,
 109         BNXT_QPLIB_HWRM_PG_SIZE_2M      = 3,
 110         BNXT_QPLIB_HWRM_PG_SIZE_8M      = 4,
 111         BNXT_QPLIB_HWRM_PG_SIZE_1G      = 5,
 112 };
 113
 114 struct bnxt_qplib_reg_desc {
 115         u8              bar_id;
 116         resource_size_t bar_base;
 117         void __iomem    *bar_reg;
 118         size_t          len;
 119 };
 120
 121 struct bnxt_qplib_pbl {
 122         u32                             pg_count;
 123         u32                             pg_size;
 124         void                            **pg_arr;
 125         dma_addr_t                      *pg_map_arr;
 126 };
 127
 128 struct bnxt_qplib_sg_info {
 129         struct ib_umem                  *umem;
 130         u32                             npages;
 131         u32                             pgshft;
 132         u32                             pgsize;
 133         bool                            nopte;
 134 };
 135
 136 struct bnxt_qplib_hwq_attr {
 137         struct bnxt_qplib_res           *res;
 138         struct bnxt_qplib_sg_info       *sginfo;
 139         enum bnxt_qplib_hwq_type        type;
 140         u32                             depth;
 141         u32                             stride;
 142         u32                             aux_stride;
 143         u32                             aux_depth;
 144 };
 145
 146 struct bnxt_qplib_hwq {
 147         struct pci_dev                  *pdev;
 148         /* lock to protect qplib_hwq */
 149         spinlock_t                      lock;
 150         struct bnxt_qplib_pbl           pbl[PBL_LVL_MAX + 1];
 151         enum bnxt_qplib_pbl_lvl         level;          /* 0, 1, or 2 */
 152         /* ptr for easy access to the PBL entries */
 153         void                            **pbl_ptr;
 154         /* ptr for easy access to the dma_addr */
 155         dma_addr_t                      *pbl_dma_ptr;
 156         u32                             max_elements;
 157         u32                             depth;
 158         u16                             element_size;   /* Size of each entry */
 159         u16                             qe_ppg; /* queue entry per page */
 160
 161         u32                             prod;           /* raw */
 162         u32                             cons;           /* raw */
 163         u8                              cp_bit;
 164         u8                              is_user;
 165         u64                             *pad_pg;
 166         u32                             pad_stride;
 167         u32                             pad_pgofft;
 168 };
 169
 170 struct bnxt_qplib_db_info {
 171         void __iomem            *db;
 172         void __iomem            *priv_db;
 173         struct bnxt_qplib_hwq   *hwq;
 174         u32                     xid;
 175         u32                     max_slot;
 176 };
 177
 178 /* Tables */
 179 struct bnxt_qplib_pd_tbl {
 180         unsigned long                   *tbl;
 181         u32                             max;
 182 };
 183
 184 struct bnxt_qplib_sgid_tbl {
 185         struct bnxt_qplib_gid_info      *tbl;
 186         u16                             *hw_id;
 187         u16                             max;
 188         u16                             active;
 189         void                            *ctx;
 190         u8                              *vlan;
 191 };
 192
 193 struct bnxt_qplib_pkey_tbl {
 194         u16                             *tbl;
 195         u16                             max;
 196         u16                             active;
 197 };
 198
 199 struct bnxt_qplib_dpi {
 200         u32                             dpi;
 201         void __iomem                    *dbr;
 202         u64                             umdbr;
 203 };
 204
 205 struct bnxt_qplib_dpi_tbl {
 206         void                            **app_tbl;
 207         unsigned long                   *tbl;
 208         u16                             max;
 209         void __iomem                    *dbr_bar_reg_iomem;
 210         u64                             unmapped_dbr;
 211 };
 212
 213 struct bnxt_qplib_stats {
 214         dma_addr_t                      dma_map;
 215         void                            *dma;
 216         u32                             size;
 217         u32                             fw_id;
 218 };
 219
 220 struct bnxt_qplib_vf_res {
 221         u32 max_qp_per_vf;
 222         u32 max_mrw_per_vf;
 223         u32 max_srq_per_vf;
 224         u32 max_cq_per_vf;
 225         u32 max_gid_per_vf;
 226 };
 227
 228 #define BNXT_QPLIB_MAX_QP_CTX_ENTRY_SIZE        448
 229 #define BNXT_QPLIB_MAX_SRQ_CTX_ENTRY_SIZE       64
 230 #define BNXT_QPLIB_MAX_CQ_CTX_ENTRY_SIZE        64
 231 #define BNXT_QPLIB_MAX_MRW_CTX_ENTRY_SIZE       128
 232
 233 #define MAX_TQM_ALLOC_REQ               48
 234 #define MAX_TQM_ALLOC_BLK_SIZE          8
 235 struct bnxt_qplib_tqm_ctx {
 236         struct bnxt_qplib_hwq           pde;
 237         u8                              pde_level; /* Original level */
 238         struct bnxt_qplib_hwq           qtbl[MAX_TQM_ALLOC_REQ];
 239         u8                              qcount[MAX_TQM_ALLOC_REQ];
 240 };
 241
 242 struct bnxt_qplib_ctx {
 243         u32                             qpc_count;
 244         struct bnxt_qplib_hwq           qpc_tbl;
 245         u32                             mrw_count;
 246         struct bnxt_qplib_hwq           mrw_tbl;
 247         u32                             srqc_count;
 248         struct bnxt_qplib_hwq           srqc_tbl;
 249         u32                             cq_count;
 250         struct bnxt_qplib_hwq           cq_tbl;
 251         struct bnxt_qplib_hwq           tim_tbl;
 252         struct bnxt_qplib_tqm_ctx       tqm_ctx;
 253         struct bnxt_qplib_stats         stats;
 254         struct bnxt_qplib_vf_res        vf_res;
 255         u64                             hwrm_intf_ver;
 256 };
 257
 258 struct bnxt_qplib_res {
 259         struct pci_dev                  *pdev;
 260         struct bnxt_qplib_chip_ctx      *cctx;
 261         struct net_device               *netdev;
 262
 263         struct bnxt_qplib_rcfw          *rcfw;
 264         struct bnxt_qplib_pd_tbl        pd_tbl;
 265         struct bnxt_qplib_sgid_tbl      sgid_tbl;
 266         struct bnxt_qplib_pkey_tbl      pkey_tbl;
 267         struct bnxt_qplib_dpi_tbl       dpi_tbl;
 268         bool                            prio;
 269 };
 270
 271 static inline bool bnxt_qplib_is_chip_gen_p5(struct bnxt_qplib_chip_ctx *cctx)
 272 {
 273         return (cctx->chip_num == CHIP_NUM_57508 ||
 274                 cctx->chip_num == CHIP_NUM_57504 ||
 275                 cctx->chip_num == CHIP_NUM_57502);
 276 }
 277
 278 static inline u8 bnxt_qplib_get_hwq_type(struct bnxt_qplib_res *res)
 279 {
 280         return bnxt_qplib_is_chip_gen_p5(res->cctx) ?
 281                                         HWQ_TYPE_QUEUE : HWQ_TYPE_L2_CMPL;
 282 }
 283
 284 static inline u8 bnxt_qplib_get_ring_type(struct bnxt_qplib_chip_ctx *cctx)
 285 {
 286         return bnxt_qplib_is_chip_gen_p5(cctx) ?
 287                RING_ALLOC_REQ_RING_TYPE_NQ :
 288                RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL;
 289 }
 290
 291 static inline u8 bnxt_qplib_base_pg_size(struct bnxt_qplib_hwq *hwq)
 292 {
 293         u8 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
 294         struct bnxt_qplib_pbl *pbl;
 295
 296         pbl = &hwq->pbl[PBL_LVL_0];
 297         switch (pbl->pg_size) {
 298         case ROCE_PG_SIZE_4K:
 299                 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_4K;
 300                 break;
 301         case ROCE_PG_SIZE_8K:
 302                 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8K;
 303                 break;
 304         case ROCE_PG_SIZE_64K:
 305                 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_64K;
 306                 break;
 307         case ROCE_PG_SIZE_2M:
 308                 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_2M;
 309                 break;
 310         case ROCE_PG_SIZE_8M:
 311                 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_8M;
 312                 break;
 313         case ROCE_PG_SIZE_1G:
 314                 pg_size = BNXT_QPLIB_HWRM_PG_SIZE_1G;
 315                 break;
 316         default:
 317                 break;
 318         }
 319
 320         return pg_size;
 321 }
 322
 323 static inline void *bnxt_qplib_get_qe(struct bnxt_qplib_hwq *hwq,
 324                                       u32 indx, u64 *pg)
 325 {
 326         u32 pg_num, pg_idx;
 327
 328         pg_num = (indx / hwq->qe_ppg);
 329         pg_idx = (indx % hwq->qe_ppg);
 330         if (pg)
 331                 *pg = (u64)&hwq->pbl_ptr[pg_num];
 332         return (void *)(hwq->pbl_ptr[pg_num] + hwq->element_size * pg_idx);
 333 }
 334
 335 static inline void *bnxt_qplib_get_prod_qe(struct bnxt_qplib_hwq *hwq, u32 idx)
 336 {
 337         idx += hwq->prod;
 338         if (idx >= hwq->depth)
 339                 idx -= hwq->depth;
 340         return bnxt_qplib_get_qe(hwq, idx, NULL);
 341 }
 342
 343 #define to_bnxt_qplib(ptr, type, member)        \
 344         container_of(ptr, type, member)
 345
 346 struct bnxt_qplib_pd;
 347 struct bnxt_qplib_dev_attr;
 348
 349 void bnxt_qplib_free_hwq(struct bnxt_qplib_res *res,
 350                          struct bnxt_qplib_hwq *hwq);
 351 int bnxt_qplib_alloc_init_hwq(struct bnxt_qplib_hwq *hwq,
 352                               struct bnxt_qplib_hwq_attr *hwq_attr);
 353 void bnxt_qplib_get_guid(u8 *dev_addr, u8 *guid);
 354 int bnxt_qplib_alloc_pd(struct bnxt_qplib_pd_tbl *pd_tbl,
 355                         struct bnxt_qplib_pd *pd);
 356 int bnxt_qplib_dealloc_pd(struct bnxt_qplib_res *res,
 357                           struct bnxt_qplib_pd_tbl *pd_tbl,
 358                           struct bnxt_qplib_pd *pd);
 359 int bnxt_qplib_alloc_dpi(struct bnxt_qplib_dpi_tbl *dpit,
 360                          struct bnxt_qplib_dpi     *dpi,
 361                          void                      *app);
 362 int bnxt_qplib_dealloc_dpi(struct bnxt_qplib_res *res,
 363                            struct bnxt_qplib_dpi_tbl *dpi_tbl,
 364                            struct bnxt_qplib_dpi *dpi);
 365 void bnxt_qplib_cleanup_res(struct bnxt_qplib_res *res);
 366 int bnxt_qplib_init_res(struct bnxt_qplib_res *res);
 367 void bnxt_qplib_free_res(struct bnxt_qplib_res *res);
 368 int bnxt_qplib_alloc_res(struct bnxt_qplib_res *res, struct pci_dev *pdev,
 369                          struct net_device *netdev,
 370                          struct bnxt_qplib_dev_attr *dev_attr);
 371 void bnxt_qplib_free_ctx(struct bnxt_qplib_res *res,
 372                          struct bnxt_qplib_ctx *ctx);
 373 int bnxt_qplib_alloc_ctx(struct bnxt_qplib_res *res,
 374                          struct bnxt_qplib_ctx *ctx,
 375                          bool virt_fn, bool is_p5);
 376
 377 static inline void bnxt_qplib_hwq_incr_prod(struct bnxt_qplib_hwq *hwq, u32 cnt)
 378 {
 379         hwq->prod = (hwq->prod + cnt) % hwq->depth;
 380 }
 381
 382 static inline void bnxt_qplib_hwq_incr_cons(struct bnxt_qplib_hwq *hwq,
 383                                             u32 cnt)
 384 {
 385         hwq->cons = (hwq->cons + cnt) % hwq->depth;
 386 }
 387
 388 static inline void bnxt_qplib_ring_db32(struct bnxt_qplib_db_info *info,
 389                                         bool arm)
 390 {
 391         u32 key;
 392
 393         key = info->hwq->cons & (info->hwq->max_elements - 1);
 394         key |= (CMPL_DOORBELL_IDX_VALID |
 395                 (CMPL_DOORBELL_KEY_CMPL & CMPL_DOORBELL_KEY_MASK));
 396         if (!arm)
 397                 key |= CMPL_DOORBELL_MASK;
 398         writel(key, info->db);
 399 }
 400
 401 static inline void bnxt_qplib_ring_db(struct bnxt_qplib_db_info *info,
 402                                       u32 type)
 403 {
 404         u64 key = 0;
 405
 406         key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
 407         key <<= 32;
 408         key |= (info->hwq->cons & (info->hwq->max_elements - 1)) &
 409                 DBC_DBC_INDEX_MASK;
 410         writeq(key, info->db);
 411 }
 412
 413 static inline void bnxt_qplib_ring_prod_db(struct bnxt_qplib_db_info *info,
 414                                            u32 type)
 415 {
 416         u64 key = 0;
 417
 418         key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
 419         key <<= 32;
 420         key |= ((info->hwq->prod / info->max_slot)) & DBC_DBC_INDEX_MASK;
 421         writeq(key, info->db);
 422 }
 423
 424 static inline void bnxt_qplib_armen_db(struct bnxt_qplib_db_info *info,
 425                                        u32 type)
 426 {
 427         u64 key = 0;
 428
 429         key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | type;
 430         key <<= 32;
 431         writeq(key, info->priv_db);
 432 }
 433
 434 static inline void bnxt_qplib_srq_arm_db(struct bnxt_qplib_db_info *info,
 435                                          u32 th)
 436 {
 437         u64 key = 0;
 438
 439         key = (info->xid & DBC_DBC_XID_MASK) | DBC_DBC_PATH_ROCE | th;
 440         key <<= 32;
 441         key |=  th & DBC_DBC_INDEX_MASK;
 442         writeq(key, info->priv_db);
 443 }
 444
 445 static inline void bnxt_qplib_ring_nq_db(struct bnxt_qplib_db_info *info,
 446                                          struct bnxt_qplib_chip_ctx *cctx,
 447                                          bool arm)
 448 {
 449         u32 type;
 450
 451         type = arm ? DBC_DBC_TYPE_NQ_ARM : DBC_DBC_TYPE_NQ;
 452         if (bnxt_qplib_is_chip_gen_p5(cctx))
 453                 bnxt_qplib_ring_db(info, type);
 454         else
 455                 bnxt_qplib_ring_db32(info, arm);
 456 }
 457 #endif /* __BNXT_QPLIB_RES_H__ */