2 * Broadcom NetXtreme-E RoCE driver.
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Description: IB Verbs interpreter
39 #include <linux/interrupt.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_ether.h>
45 #include <rdma/ib_verbs.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/ib_umem.h>
48 #include <rdma/ib_addr.h>
49 #include <rdma/ib_mad.h>
50 #include <rdma/ib_cache.h>
51 #include <rdma/uverbs_ioctl.h>
56 #include "qplib_res.h"
59 #include "qplib_rcfw.h"
63 #include <rdma/bnxt_re-abi.h>
65 static int __from_ib_access_flags(int iflags)
69 if (iflags & IB_ACCESS_LOCAL_WRITE)
70 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
71 if (iflags & IB_ACCESS_REMOTE_READ)
72 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
73 if (iflags & IB_ACCESS_REMOTE_WRITE)
74 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
75 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
76 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
77 if (iflags & IB_ACCESS_MW_BIND)
78 qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
79 if (iflags & IB_ZERO_BASED)
80 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
81 if (iflags & IB_ACCESS_ON_DEMAND)
82 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
86 static enum ib_access_flags __to_ib_access_flags(int qflags)
88 enum ib_access_flags iflags = 0;
90 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
91 iflags |= IB_ACCESS_LOCAL_WRITE;
92 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
93 iflags |= IB_ACCESS_REMOTE_WRITE;
94 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
95 iflags |= IB_ACCESS_REMOTE_READ;
96 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
97 iflags |= IB_ACCESS_REMOTE_ATOMIC;
98 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
99 iflags |= IB_ACCESS_MW_BIND;
100 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
101 iflags |= IB_ZERO_BASED;
102 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
103 iflags |= IB_ACCESS_ON_DEMAND;
107 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
108 struct bnxt_qplib_sge *sg_list, int num)
112 for (i = 0; i < num; i++) {
113 sg_list[i].addr = ib_sg_list[i].addr;
114 sg_list[i].lkey = ib_sg_list[i].lkey;
115 sg_list[i].size = ib_sg_list[i].length;
116 total += sg_list[i].size;
122 int bnxt_re_query_device(struct ib_device *ibdev,
123 struct ib_device_attr *ib_attr,
124 struct ib_udata *udata)
126 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
127 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
129 memset(ib_attr, 0, sizeof(*ib_attr));
130 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver,
131 min(sizeof(dev_attr->fw_ver),
132 sizeof(ib_attr->fw_ver)));
133 bnxt_qplib_get_guid(rdev->netdev->dev_addr,
134 (u8 *)&ib_attr->sys_image_guid);
135 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
136 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M;
138 ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
139 ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
140 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
141 ib_attr->max_qp = dev_attr->max_qp;
142 ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
143 ib_attr->device_cap_flags =
144 IB_DEVICE_CURR_QP_STATE_MOD
145 | IB_DEVICE_RC_RNR_NAK_GEN
146 | IB_DEVICE_SHUTDOWN_PORT
147 | IB_DEVICE_SYS_IMAGE_GUID
148 | IB_DEVICE_LOCAL_DMA_LKEY
149 | IB_DEVICE_RESIZE_MAX_WR
150 | IB_DEVICE_PORT_ACTIVE_EVENT
151 | IB_DEVICE_N_NOTIFY_CQ
152 | IB_DEVICE_MEM_WINDOW
153 | IB_DEVICE_MEM_WINDOW_TYPE_2B
154 | IB_DEVICE_MEM_MGT_EXTENSIONS;
155 ib_attr->max_send_sge = dev_attr->max_qp_sges;
156 ib_attr->max_recv_sge = dev_attr->max_qp_sges;
157 ib_attr->max_sge_rd = dev_attr->max_qp_sges;
158 ib_attr->max_cq = dev_attr->max_cq;
159 ib_attr->max_cqe = dev_attr->max_cq_wqes;
160 ib_attr->max_mr = dev_attr->max_mr;
161 ib_attr->max_pd = dev_attr->max_pd;
162 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
163 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
164 ib_attr->atomic_cap = IB_ATOMIC_NONE;
165 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE;
166 if (dev_attr->is_atomic) {
167 ib_attr->atomic_cap = IB_ATOMIC_GLOB;
168 ib_attr->masked_atomic_cap = IB_ATOMIC_GLOB;
171 ib_attr->max_ee_rd_atom = 0;
172 ib_attr->max_res_rd_atom = 0;
173 ib_attr->max_ee_init_rd_atom = 0;
175 ib_attr->max_rdd = 0;
176 ib_attr->max_mw = dev_attr->max_mw;
177 ib_attr->max_raw_ipv6_qp = 0;
178 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
179 ib_attr->max_mcast_grp = 0;
180 ib_attr->max_mcast_qp_attach = 0;
181 ib_attr->max_total_mcast_qp_attach = 0;
182 ib_attr->max_ah = dev_attr->max_ah;
184 ib_attr->max_srq = dev_attr->max_srq;
185 ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
186 ib_attr->max_srq_sge = dev_attr->max_srq_sges;
188 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
190 ib_attr->max_pkeys = 1;
191 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
196 int bnxt_re_query_port(struct ib_device *ibdev, u32 port_num,
197 struct ib_port_attr *port_attr)
199 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
200 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
202 memset(port_attr, 0, sizeof(*port_attr));
204 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
205 port_attr->state = IB_PORT_ACTIVE;
206 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP;
208 port_attr->state = IB_PORT_DOWN;
209 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED;
211 port_attr->max_mtu = IB_MTU_4096;
212 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
213 port_attr->gid_tbl_len = dev_attr->max_sgid;
214 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
215 IB_PORT_DEVICE_MGMT_SUP |
216 IB_PORT_VENDOR_CLASS_SUP;
217 port_attr->ip_gids = true;
219 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW;
220 port_attr->bad_pkey_cntr = 0;
221 port_attr->qkey_viol_cntr = 0;
222 port_attr->pkey_tbl_len = dev_attr->max_pkey;
224 port_attr->sm_lid = 0;
226 port_attr->max_vl_num = 4;
227 port_attr->sm_sl = 0;
228 port_attr->subnet_timeout = 0;
229 port_attr->init_type_reply = 0;
230 port_attr->active_speed = rdev->active_speed;
231 port_attr->active_width = rdev->active_width;
236 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u32 port_num,
237 struct ib_port_immutable *immutable)
239 struct ib_port_attr port_attr;
241 if (bnxt_re_query_port(ibdev, port_num, &port_attr))
244 immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
245 immutable->gid_tbl_len = port_attr.gid_tbl_len;
246 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
247 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
248 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
252 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str)
254 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
256 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d",
257 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1],
258 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]);
261 int bnxt_re_query_pkey(struct ib_device *ibdev, u32 port_num,
262 u16 index, u16 *pkey)
264 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
266 /* Ignore port_num */
268 memset(pkey, 0, sizeof(*pkey));
269 return bnxt_qplib_get_pkey(&rdev->qplib_res,
270 &rdev->qplib_res.pkey_tbl, index, pkey);
273 int bnxt_re_query_gid(struct ib_device *ibdev, u32 port_num,
274 int index, union ib_gid *gid)
276 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
279 /* Ignore port_num */
280 memset(gid, 0, sizeof(*gid));
281 rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
282 &rdev->qplib_res.sgid_tbl, index,
283 (struct bnxt_qplib_gid *)gid);
287 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context)
290 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
291 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
292 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
293 struct bnxt_qplib_gid *gid_to_del;
294 u16 vlan_id = 0xFFFF;
296 /* Delete the entry from the hardware */
301 if (sgid_tbl && sgid_tbl->active) {
302 if (ctx->idx >= sgid_tbl->max)
304 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid;
305 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id;
306 /* DEL_GID is called in WQ context(netdevice_event_work_handler)
307 * or via the ib_unregister_device path. In the former case QP1
308 * may not be destroyed yet, in which case just return as FW
309 * needs that entry to be present and will fail it's deletion.
310 * We could get invoked again after QP1 is destroyed OR get an
311 * ADD_GID call with a different GID value for the same index
312 * where we issue MODIFY_GID cmd to update the GID entry -- TBD
315 rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
316 ctx->refcnt == 1 && rdev->gsi_ctx.gsi_sqp) {
317 ibdev_dbg(&rdev->ibdev,
318 "Trying to delete GID0 while QP1 is alive\n");
323 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del,
326 ibdev_err(&rdev->ibdev,
327 "Failed to remove GID: %#x", rc);
329 ctx_tbl = sgid_tbl->ctx;
330 ctx_tbl[ctx->idx] = NULL;
340 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context)
344 u16 vlan_id = 0xFFFF;
345 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
346 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev);
347 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
349 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL);
353 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid,
354 rdev->qplib_res.netdev->dev_addr,
355 vlan_id, true, &tbl_idx);
356 if (rc == -EALREADY) {
357 ctx_tbl = sgid_tbl->ctx;
358 ctx_tbl[tbl_idx]->refcnt++;
359 *context = ctx_tbl[tbl_idx];
364 ibdev_err(&rdev->ibdev, "Failed to add GID: %#x", rc);
368 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
371 ctx_tbl = sgid_tbl->ctx;
374 ctx_tbl[tbl_idx] = ctx;
380 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
383 return IB_LINK_LAYER_ETHERNET;
386 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
388 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
390 struct bnxt_re_fence_data *fence = &pd->fence;
391 struct ib_mr *ib_mr = &fence->mr->ib_mr;
392 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
394 memset(wqe, 0, sizeof(*wqe));
395 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
396 wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
397 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
398 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
399 wqe->bind.zero_based = false;
400 wqe->bind.parent_l_key = ib_mr->lkey;
401 wqe->bind.va = (u64)(unsigned long)fence->va;
402 wqe->bind.length = fence->size;
403 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
404 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
406 /* Save the initial rkey in fence structure for now;
407 * wqe->bind.r_key will be set at (re)bind time.
409 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
412 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
414 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
416 struct ib_pd *ib_pd = qp->ib_qp.pd;
417 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
418 struct bnxt_re_fence_data *fence = &pd->fence;
419 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
420 struct bnxt_qplib_swqe wqe;
423 memcpy(&wqe, fence_wqe, sizeof(wqe));
424 wqe.bind.r_key = fence->bind_rkey;
425 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
427 ibdev_dbg(&qp->rdev->ibdev,
428 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
429 wqe.bind.r_key, qp->qplib_qp.id, pd);
430 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
432 ibdev_err(&qp->rdev->ibdev, "Failed to bind fence-WQE\n");
435 bnxt_qplib_post_send_db(&qp->qplib_qp);
440 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
442 struct bnxt_re_fence_data *fence = &pd->fence;
443 struct bnxt_re_dev *rdev = pd->rdev;
444 struct device *dev = &rdev->en_dev->pdev->dev;
445 struct bnxt_re_mr *mr = fence->mr;
448 bnxt_re_dealloc_mw(fence->mw);
453 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
456 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
460 if (fence->dma_addr) {
461 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
467 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
469 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
470 struct bnxt_re_fence_data *fence = &pd->fence;
471 struct bnxt_re_dev *rdev = pd->rdev;
472 struct device *dev = &rdev->en_dev->pdev->dev;
473 struct bnxt_re_mr *mr = NULL;
474 dma_addr_t dma_addr = 0;
478 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
480 rc = dma_mapping_error(dev, dma_addr);
482 ibdev_err(&rdev->ibdev, "Failed to dma-map fence-MR-mem\n");
487 fence->dma_addr = dma_addr;
490 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
497 mr->qplib_mr.pd = &pd->qplib_pd;
498 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
499 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
500 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
502 ibdev_err(&rdev->ibdev, "Failed to alloc fence-HW-MR\n");
507 mr->ib_mr.lkey = mr->qplib_mr.lkey;
508 mr->qplib_mr.va = (u64)(unsigned long)fence->va;
509 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
510 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL,
511 BNXT_RE_FENCE_PBL_SIZE, PAGE_SIZE);
513 ibdev_err(&rdev->ibdev, "Failed to register fence-MR\n");
516 mr->ib_mr.rkey = mr->qplib_mr.rkey;
518 /* Create a fence MW only for kernel consumers */
519 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
521 ibdev_err(&rdev->ibdev,
522 "Failed to create fence-MW for PD: %p\n", pd);
528 bnxt_re_create_fence_wqe(pd);
532 bnxt_re_destroy_fence_mr(pd);
536 /* Protection Domains */
537 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata)
539 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
540 struct bnxt_re_dev *rdev = pd->rdev;
542 bnxt_re_destroy_fence_mr(pd);
545 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
550 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
552 struct ib_device *ibdev = ibpd->device;
553 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
554 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context(
555 udata, struct bnxt_re_ucontext, ib_uctx);
556 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd);
560 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) {
561 ibdev_err(&rdev->ibdev, "Failed to allocate HW PD");
567 struct bnxt_re_pd_resp resp;
569 if (!ucntx->dpi.dbr) {
570 /* Allocate DPI in alloc_pd to avoid failing of
571 * ibv_devinfo and family of application when DPIs
574 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
575 &ucntx->dpi, ucntx)) {
581 resp.pdid = pd->qplib_pd.id;
582 /* Still allow mapping this DBR to the new user PD. */
583 resp.dpi = ucntx->dpi.dpi;
584 resp.dbr = (u64)ucntx->dpi.umdbr;
586 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
588 ibdev_err(&rdev->ibdev,
589 "Failed to copy user response\n");
595 if (bnxt_re_create_fence_mr(pd))
596 ibdev_warn(&rdev->ibdev,
597 "Failed to create Fence-MR\n");
600 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
606 /* Address Handles */
607 int bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags)
609 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
610 struct bnxt_re_dev *rdev = ah->rdev;
612 bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah,
613 !(flags & RDMA_DESTROY_AH_SLEEPABLE));
617 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype)
622 case RDMA_NETWORK_IPV4:
623 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
625 case RDMA_NETWORK_IPV6:
626 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
629 nw_type = CMDQ_CREATE_AH_TYPE_V1;
635 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_init_attr *init_attr,
636 struct ib_udata *udata)
638 struct ib_pd *ib_pd = ib_ah->pd;
639 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
640 struct rdma_ah_attr *ah_attr = init_attr->ah_attr;
641 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
642 struct bnxt_re_dev *rdev = pd->rdev;
643 const struct ib_gid_attr *sgid_attr;
644 struct bnxt_re_gid_ctx *ctx;
645 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
649 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
650 ibdev_err(&rdev->ibdev, "Failed to alloc AH: GRH not set");
655 ah->qplib_ah.pd = &pd->qplib_pd;
657 /* Supply the configuration for the HW */
658 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
659 sizeof(union ib_gid));
660 sgid_attr = grh->sgid_attr;
661 /* Get the HW context of the GID. The reference
662 * of GID table entry is already taken by the caller.
664 ctx = rdma_read_gid_hw_context(sgid_attr);
665 ah->qplib_ah.sgid_index = ctx->idx;
666 ah->qplib_ah.host_sgid_index = grh->sgid_index;
667 ah->qplib_ah.traffic_class = grh->traffic_class;
668 ah->qplib_ah.flow_label = grh->flow_label;
669 ah->qplib_ah.hop_limit = grh->hop_limit;
670 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
672 /* Get network header type for this GID */
673 nw_type = rdma_gid_attr_network_type(sgid_attr);
674 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type);
676 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
677 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah,
679 RDMA_CREATE_AH_SLEEPABLE));
681 ibdev_err(&rdev->ibdev, "Failed to allocate HW AH");
685 /* Write AVID to shared page. */
687 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
688 udata, struct bnxt_re_ucontext, ib_uctx);
692 spin_lock_irqsave(&uctx->sh_lock, flag);
693 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
694 *wrptr = ah->qplib_ah.id;
695 wmb(); /* make sure cache is updated. */
696 spin_unlock_irqrestore(&uctx->sh_lock, flag);
702 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
707 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
709 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
711 ah_attr->type = ib_ah->type;
712 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
713 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
714 rdma_ah_set_grh(ah_attr, NULL, 0,
715 ah->qplib_ah.host_sgid_index,
716 0, ah->qplib_ah.traffic_class);
717 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
718 rdma_ah_set_port_num(ah_attr, 1);
719 rdma_ah_set_static_rate(ah_attr, 0);
723 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp)
724 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock)
728 spin_lock_irqsave(&qp->scq->cq_lock, flags);
729 if (qp->rcq != qp->scq)
730 spin_lock(&qp->rcq->cq_lock);
732 __acquire(&qp->rcq->cq_lock);
737 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp,
739 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock)
741 if (qp->rcq != qp->scq)
742 spin_unlock(&qp->rcq->cq_lock);
744 __release(&qp->rcq->cq_lock);
745 spin_unlock_irqrestore(&qp->scq->cq_lock, flags);
748 static int bnxt_re_destroy_gsi_sqp(struct bnxt_re_qp *qp)
750 struct bnxt_re_qp *gsi_sqp;
751 struct bnxt_re_ah *gsi_sah;
752 struct bnxt_re_dev *rdev;
756 gsi_sqp = rdev->gsi_ctx.gsi_sqp;
757 gsi_sah = rdev->gsi_ctx.gsi_sah;
759 ibdev_dbg(&rdev->ibdev, "Destroy the shadow AH\n");
760 bnxt_qplib_destroy_ah(&rdev->qplib_res,
763 bnxt_qplib_clean_qp(&qp->qplib_qp);
765 ibdev_dbg(&rdev->ibdev, "Destroy the shadow QP\n");
766 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &gsi_sqp->qplib_qp);
768 ibdev_err(&rdev->ibdev, "Destroy Shadow QP failed");
771 bnxt_qplib_free_qp_res(&rdev->qplib_res, &gsi_sqp->qplib_qp);
773 /* remove from active qp list */
774 mutex_lock(&rdev->qp_lock);
775 list_del(&gsi_sqp->list);
776 mutex_unlock(&rdev->qp_lock);
777 atomic_dec(&rdev->qp_count);
779 kfree(rdev->gsi_ctx.sqp_tbl);
782 rdev->gsi_ctx.gsi_sqp = NULL;
783 rdev->gsi_ctx.gsi_sah = NULL;
784 rdev->gsi_ctx.sqp_tbl = NULL;
792 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata)
794 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
795 struct bnxt_re_dev *rdev = qp->rdev;
799 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
801 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
803 ibdev_err(&rdev->ibdev, "Failed to destroy HW QP");
807 if (rdma_is_kernel_res(&qp->ib_qp.res)) {
808 flags = bnxt_re_lock_cqs(qp);
809 bnxt_qplib_clean_qp(&qp->qplib_qp);
810 bnxt_re_unlock_cqs(qp, flags);
813 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp);
815 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp) {
816 rc = bnxt_re_destroy_gsi_sqp(qp);
821 mutex_lock(&rdev->qp_lock);
823 mutex_unlock(&rdev->qp_lock);
824 atomic_dec(&rdev->qp_count);
826 ib_umem_release(qp->rumem);
827 ib_umem_release(qp->sumem);
835 static u8 __from_ib_qp_type(enum ib_qp_type type)
839 return CMDQ_CREATE_QP1_TYPE_GSI;
841 return CMDQ_CREATE_QP_TYPE_RC;
843 return CMDQ_CREATE_QP_TYPE_UD;
849 static u16 bnxt_re_setup_rwqe_size(struct bnxt_qplib_qp *qplqp,
852 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
854 return bnxt_re_get_rwqe_size(rsge);
857 static u16 bnxt_re_get_wqe_size(int ilsize, int nsge)
859 u16 wqe_size, calc_ils;
861 wqe_size = bnxt_re_get_swqe_size(nsge);
863 calc_ils = sizeof(struct sq_send_hdr) + ilsize;
864 wqe_size = max_t(u16, calc_ils, wqe_size);
865 wqe_size = ALIGN(wqe_size, sizeof(struct sq_send_hdr));
870 static int bnxt_re_setup_swqe_size(struct bnxt_re_qp *qp,
871 struct ib_qp_init_attr *init_attr)
873 struct bnxt_qplib_dev_attr *dev_attr;
874 struct bnxt_qplib_qp *qplqp;
875 struct bnxt_re_dev *rdev;
876 struct bnxt_qplib_q *sq;
880 qplqp = &qp->qplib_qp;
882 dev_attr = &rdev->dev_attr;
884 align = sizeof(struct sq_send_hdr);
885 ilsize = ALIGN(init_attr->cap.max_inline_data, align);
887 sq->wqe_size = bnxt_re_get_wqe_size(ilsize, sq->max_sge);
888 if (sq->wqe_size > bnxt_re_get_swqe_size(dev_attr->max_qp_sges))
890 /* For gen p4 and gen p5 backward compatibility mode
891 * wqe size is fixed to 128 bytes
893 if (sq->wqe_size < bnxt_re_get_swqe_size(dev_attr->max_qp_sges) &&
894 qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
895 sq->wqe_size = bnxt_re_get_swqe_size(dev_attr->max_qp_sges);
897 if (init_attr->cap.max_inline_data) {
898 qplqp->max_inline_data = sq->wqe_size -
899 sizeof(struct sq_send_hdr);
900 init_attr->cap.max_inline_data = qplqp->max_inline_data;
901 if (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC)
902 sq->max_sge = qplqp->max_inline_data /
903 sizeof(struct sq_sge);
909 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
910 struct bnxt_re_qp *qp, struct ib_udata *udata)
912 struct bnxt_qplib_qp *qplib_qp;
913 struct bnxt_re_ucontext *cntx;
914 struct bnxt_re_qp_req ureq;
915 int bytes = 0, psn_sz;
916 struct ib_umem *umem;
919 qplib_qp = &qp->qplib_qp;
920 cntx = rdma_udata_to_drv_context(udata, struct bnxt_re_ucontext,
922 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
925 bytes = (qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size);
926 /* Consider mapping PSN search memory only for RC QPs. */
927 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) {
928 psn_sz = bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx) ?
929 sizeof(struct sq_psn_search_ext) :
930 sizeof(struct sq_psn_search);
931 psn_nume = (qplib_qp->wqe_mode == BNXT_QPLIB_WQE_MODE_STATIC) ?
932 qplib_qp->sq.max_wqe :
933 ((qplib_qp->sq.max_wqe * qplib_qp->sq.wqe_size) /
934 sizeof(struct bnxt_qplib_sge));
935 bytes += (psn_nume * psn_sz);
938 bytes = PAGE_ALIGN(bytes);
939 umem = ib_umem_get(&rdev->ibdev, ureq.qpsva, bytes,
940 IB_ACCESS_LOCAL_WRITE);
942 return PTR_ERR(umem);
945 qplib_qp->sq.sg_info.umem = umem;
946 qplib_qp->sq.sg_info.pgsize = PAGE_SIZE;
947 qplib_qp->sq.sg_info.pgshft = PAGE_SHIFT;
948 qplib_qp->qp_handle = ureq.qp_handle;
950 if (!qp->qplib_qp.srq) {
951 bytes = (qplib_qp->rq.max_wqe * qplib_qp->rq.wqe_size);
952 bytes = PAGE_ALIGN(bytes);
953 umem = ib_umem_get(&rdev->ibdev, ureq.qprva, bytes,
954 IB_ACCESS_LOCAL_WRITE);
958 qplib_qp->rq.sg_info.umem = umem;
959 qplib_qp->rq.sg_info.pgsize = PAGE_SIZE;
960 qplib_qp->rq.sg_info.pgshft = PAGE_SHIFT;
963 qplib_qp->dpi = &cntx->dpi;
966 ib_umem_release(qp->sumem);
968 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info));
970 return PTR_ERR(umem);
973 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
974 (struct bnxt_re_pd *pd,
975 struct bnxt_qplib_res *qp1_res,
976 struct bnxt_qplib_qp *qp1_qp)
978 struct bnxt_re_dev *rdev = pd->rdev;
979 struct bnxt_re_ah *ah;
983 ah = kzalloc(sizeof(*ah), GFP_KERNEL);
988 ah->qplib_ah.pd = &pd->qplib_pd;
990 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
994 /* supply the dgid data same as sgid */
995 memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
996 sizeof(union ib_gid));
997 ah->qplib_ah.sgid_index = 0;
999 ah->qplib_ah.traffic_class = 0;
1000 ah->qplib_ah.flow_label = 0;
1001 ah->qplib_ah.hop_limit = 1;
1002 ah->qplib_ah.sl = 0;
1003 /* Have DMAC same as SMAC */
1004 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
1006 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false);
1008 ibdev_err(&rdev->ibdev,
1009 "Failed to allocate HW AH for Shadow QP");
1020 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
1021 (struct bnxt_re_pd *pd,
1022 struct bnxt_qplib_res *qp1_res,
1023 struct bnxt_qplib_qp *qp1_qp)
1025 struct bnxt_re_dev *rdev = pd->rdev;
1026 struct bnxt_re_qp *qp;
1029 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1035 /* Initialize the shadow QP structure from the QP1 values */
1036 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1038 qp->qplib_qp.pd = &pd->qplib_pd;
1039 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1040 qp->qplib_qp.type = IB_QPT_UD;
1042 qp->qplib_qp.max_inline_data = 0;
1043 qp->qplib_qp.sig_type = true;
1045 /* Shadow QP SQ depth should be same as QP1 RQ depth */
1046 qp->qplib_qp.sq.wqe_size = bnxt_re_get_wqe_size(0, 6);
1047 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
1048 qp->qplib_qp.sq.max_sge = 2;
1049 /* Q full delta can be 1 since it is internal QP */
1050 qp->qplib_qp.sq.q_full_delta = 1;
1051 qp->qplib_qp.sq.sg_info.pgsize = PAGE_SIZE;
1052 qp->qplib_qp.sq.sg_info.pgshft = PAGE_SHIFT;
1054 qp->qplib_qp.scq = qp1_qp->scq;
1055 qp->qplib_qp.rcq = qp1_qp->rcq;
1057 qp->qplib_qp.rq.wqe_size = bnxt_re_get_rwqe_size(6);
1058 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
1059 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
1060 /* Q full delta can be 1 since it is internal QP */
1061 qp->qplib_qp.rq.q_full_delta = 1;
1062 qp->qplib_qp.rq.sg_info.pgsize = PAGE_SIZE;
1063 qp->qplib_qp.rq.sg_info.pgshft = PAGE_SHIFT;
1065 qp->qplib_qp.mtu = qp1_qp->mtu;
1067 qp->qplib_qp.sq_hdr_buf_size = 0;
1068 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
1069 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1071 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
1075 spin_lock_init(&qp->sq_lock);
1076 INIT_LIST_HEAD(&qp->list);
1077 mutex_lock(&rdev->qp_lock);
1078 list_add_tail(&qp->list, &rdev->qp_list);
1079 atomic_inc(&rdev->qp_count);
1080 mutex_unlock(&rdev->qp_lock);
1087 static int bnxt_re_init_rq_attr(struct bnxt_re_qp *qp,
1088 struct ib_qp_init_attr *init_attr)
1090 struct bnxt_qplib_dev_attr *dev_attr;
1091 struct bnxt_qplib_qp *qplqp;
1092 struct bnxt_re_dev *rdev;
1093 struct bnxt_qplib_q *rq;
1097 qplqp = &qp->qplib_qp;
1099 dev_attr = &rdev->dev_attr;
1101 if (init_attr->srq) {
1102 struct bnxt_re_srq *srq;
1104 srq = container_of(init_attr->srq, struct bnxt_re_srq, ib_srq);
1105 qplqp->srq = &srq->qplib_srq;
1108 rq->max_sge = init_attr->cap.max_recv_sge;
1109 if (rq->max_sge > dev_attr->max_qp_sges)
1110 rq->max_sge = dev_attr->max_qp_sges;
1111 init_attr->cap.max_recv_sge = rq->max_sge;
1112 rq->wqe_size = bnxt_re_setup_rwqe_size(qplqp, rq->max_sge,
1113 dev_attr->max_qp_sges);
1114 /* Allocate 1 more than what's provided so posting max doesn't
1117 entries = roundup_pow_of_two(init_attr->cap.max_recv_wr + 1);
1118 rq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1119 rq->q_full_delta = 0;
1120 rq->sg_info.pgsize = PAGE_SIZE;
1121 rq->sg_info.pgshft = PAGE_SHIFT;
1127 static void bnxt_re_adjust_gsi_rq_attr(struct bnxt_re_qp *qp)
1129 struct bnxt_qplib_dev_attr *dev_attr;
1130 struct bnxt_qplib_qp *qplqp;
1131 struct bnxt_re_dev *rdev;
1134 qplqp = &qp->qplib_qp;
1135 dev_attr = &rdev->dev_attr;
1137 if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {
1138 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1139 if (qplqp->rq.max_sge > dev_attr->max_qp_sges)
1140 qplqp->rq.max_sge = dev_attr->max_qp_sges;
1141 qplqp->rq.max_sge = 6;
1145 static int bnxt_re_init_sq_attr(struct bnxt_re_qp *qp,
1146 struct ib_qp_init_attr *init_attr,
1147 struct ib_udata *udata)
1149 struct bnxt_qplib_dev_attr *dev_attr;
1150 struct bnxt_qplib_qp *qplqp;
1151 struct bnxt_re_dev *rdev;
1152 struct bnxt_qplib_q *sq;
1158 qplqp = &qp->qplib_qp;
1160 dev_attr = &rdev->dev_attr;
1162 sq->max_sge = init_attr->cap.max_send_sge;
1163 if (sq->max_sge > dev_attr->max_qp_sges) {
1164 sq->max_sge = dev_attr->max_qp_sges;
1165 init_attr->cap.max_send_sge = sq->max_sge;
1168 rc = bnxt_re_setup_swqe_size(qp, init_attr);
1172 entries = init_attr->cap.max_send_wr;
1173 /* Allocate 128 + 1 more than what's provided */
1174 diff = (qplqp->wqe_mode == BNXT_QPLIB_WQE_MODE_VARIABLE) ?
1175 0 : BNXT_QPLIB_RESERVED_QP_WRS;
1176 entries = roundup_pow_of_two(entries + diff + 1);
1177 sq->max_wqe = min_t(u32, entries, dev_attr->max_qp_wqes + diff + 1);
1178 sq->q_full_delta = diff + 1;
1180 * Reserving one slot for Phantom WQE. Application can
1181 * post one extra entry in this case. But allowing this to avoid
1182 * unexpected Queue full condition
1184 qplqp->sq.q_full_delta -= 1;
1185 qplqp->sq.sg_info.pgsize = PAGE_SIZE;
1186 qplqp->sq.sg_info.pgshft = PAGE_SHIFT;
1191 static void bnxt_re_adjust_gsi_sq_attr(struct bnxt_re_qp *qp,
1192 struct ib_qp_init_attr *init_attr)
1194 struct bnxt_qplib_dev_attr *dev_attr;
1195 struct bnxt_qplib_qp *qplqp;
1196 struct bnxt_re_dev *rdev;
1200 qplqp = &qp->qplib_qp;
1201 dev_attr = &rdev->dev_attr;
1203 if (!bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx)) {
1204 entries = roundup_pow_of_two(init_attr->cap.max_send_wr + 1);
1205 qplqp->sq.max_wqe = min_t(u32, entries,
1206 dev_attr->max_qp_wqes + 1);
1207 qplqp->sq.q_full_delta = qplqp->sq.max_wqe -
1208 init_attr->cap.max_send_wr;
1209 qplqp->sq.max_sge++; /* Need one extra sge to put UD header */
1210 if (qplqp->sq.max_sge > dev_attr->max_qp_sges)
1211 qplqp->sq.max_sge = dev_attr->max_qp_sges;
1215 static int bnxt_re_init_qp_type(struct bnxt_re_dev *rdev,
1216 struct ib_qp_init_attr *init_attr)
1218 struct bnxt_qplib_chip_ctx *chip_ctx;
1221 chip_ctx = rdev->chip_ctx;
1223 qptype = __from_ib_qp_type(init_attr->qp_type);
1224 if (qptype == IB_QPT_MAX) {
1225 ibdev_err(&rdev->ibdev, "QP type 0x%x not supported", qptype);
1226 qptype = -EOPNOTSUPP;
1230 if (bnxt_qplib_is_chip_gen_p5(chip_ctx) &&
1231 init_attr->qp_type == IB_QPT_GSI)
1232 qptype = CMDQ_CREATE_QP_TYPE_GSI;
1237 static int bnxt_re_init_qp_attr(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1238 struct ib_qp_init_attr *init_attr,
1239 struct ib_udata *udata)
1241 struct bnxt_qplib_dev_attr *dev_attr;
1242 struct bnxt_qplib_qp *qplqp;
1243 struct bnxt_re_dev *rdev;
1244 struct bnxt_re_cq *cq;
1248 qplqp = &qp->qplib_qp;
1249 dev_attr = &rdev->dev_attr;
1251 /* Setup misc params */
1252 ether_addr_copy(qplqp->smac, rdev->netdev->dev_addr);
1253 qplqp->pd = &pd->qplib_pd;
1254 qplqp->qp_handle = (u64)qplqp;
1255 qplqp->max_inline_data = init_attr->cap.max_inline_data;
1256 qplqp->sig_type = ((init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ?
1258 qptype = bnxt_re_init_qp_type(rdev, init_attr);
1263 qplqp->type = (u8)qptype;
1264 qplqp->wqe_mode = rdev->chip_ctx->modes.wqe_mode;
1266 if (init_attr->qp_type == IB_QPT_RC) {
1267 qplqp->max_rd_atomic = dev_attr->max_qp_rd_atom;
1268 qplqp->max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1270 qplqp->mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1271 qplqp->dpi = &rdev->dpi_privileged; /* Doorbell page */
1272 if (init_attr->create_flags) {
1273 ibdev_dbg(&rdev->ibdev,
1274 "QP create flags 0x%x not supported",
1275 init_attr->create_flags);
1280 if (init_attr->send_cq) {
1281 cq = container_of(init_attr->send_cq, struct bnxt_re_cq, ib_cq);
1282 qplqp->scq = &cq->qplib_cq;
1286 if (init_attr->recv_cq) {
1287 cq = container_of(init_attr->recv_cq, struct bnxt_re_cq, ib_cq);
1288 qplqp->rcq = &cq->qplib_cq;
1293 rc = bnxt_re_init_rq_attr(qp, init_attr);
1296 if (init_attr->qp_type == IB_QPT_GSI)
1297 bnxt_re_adjust_gsi_rq_attr(qp);
1300 rc = bnxt_re_init_sq_attr(qp, init_attr, udata);
1303 if (init_attr->qp_type == IB_QPT_GSI)
1304 bnxt_re_adjust_gsi_sq_attr(qp, init_attr);
1306 if (udata) /* This will update DPI and qp_handle */
1307 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
1312 static int bnxt_re_create_shadow_gsi(struct bnxt_re_qp *qp,
1313 struct bnxt_re_pd *pd)
1315 struct bnxt_re_sqp_entries *sqp_tbl = NULL;
1316 struct bnxt_re_dev *rdev;
1317 struct bnxt_re_qp *sqp;
1318 struct bnxt_re_ah *sah;
1322 /* Create a shadow QP to handle the QP1 traffic */
1323 sqp_tbl = kzalloc(sizeof(*sqp_tbl) * BNXT_RE_MAX_GSI_SQP_ENTRIES,
1327 rdev->gsi_ctx.sqp_tbl = sqp_tbl;
1329 sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, &qp->qplib_qp);
1332 ibdev_err(&rdev->ibdev, "Failed to create Shadow QP for QP1");
1335 rdev->gsi_ctx.gsi_sqp = sqp;
1339 sah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1342 bnxt_qplib_destroy_qp(&rdev->qplib_res,
1345 ibdev_err(&rdev->ibdev,
1346 "Failed to create AH entry for ShadowQP");
1349 rdev->gsi_ctx.gsi_sah = sah;
1357 static int bnxt_re_create_gsi_qp(struct bnxt_re_qp *qp, struct bnxt_re_pd *pd,
1358 struct ib_qp_init_attr *init_attr)
1360 struct bnxt_re_dev *rdev;
1361 struct bnxt_qplib_qp *qplqp;
1365 qplqp = &qp->qplib_qp;
1367 qplqp->rq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1368 qplqp->sq_hdr_buf_size = BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1370 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, qplqp);
1372 ibdev_err(&rdev->ibdev, "create HW QP1 failed!");
1376 rc = bnxt_re_create_shadow_gsi(qp, pd);
1381 static bool bnxt_re_test_qp_limits(struct bnxt_re_dev *rdev,
1382 struct ib_qp_init_attr *init_attr,
1383 struct bnxt_qplib_dev_attr *dev_attr)
1387 if (init_attr->cap.max_send_wr > dev_attr->max_qp_wqes ||
1388 init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes ||
1389 init_attr->cap.max_send_sge > dev_attr->max_qp_sges ||
1390 init_attr->cap.max_recv_sge > dev_attr->max_qp_sges ||
1391 init_attr->cap.max_inline_data > dev_attr->max_inline_data) {
1392 ibdev_err(&rdev->ibdev,
1393 "Create QP failed - max exceeded! 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x 0x%x/0x%x",
1394 init_attr->cap.max_send_wr, dev_attr->max_qp_wqes,
1395 init_attr->cap.max_recv_wr, dev_attr->max_qp_wqes,
1396 init_attr->cap.max_send_sge, dev_attr->max_qp_sges,
1397 init_attr->cap.max_recv_sge, dev_attr->max_qp_sges,
1398 init_attr->cap.max_inline_data,
1399 dev_attr->max_inline_data);
1405 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
1406 struct ib_qp_init_attr *qp_init_attr,
1407 struct ib_udata *udata)
1409 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1410 struct bnxt_re_dev *rdev = pd->rdev;
1411 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1412 struct bnxt_re_qp *qp;
1415 rc = bnxt_re_test_qp_limits(rdev, qp_init_attr, dev_attr);
1421 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1427 rc = bnxt_re_init_qp_attr(qp, pd, qp_init_attr, udata);
1431 if (qp_init_attr->qp_type == IB_QPT_GSI &&
1432 !(bnxt_qplib_is_chip_gen_p5(rdev->chip_ctx))) {
1433 rc = bnxt_re_create_gsi_qp(qp, pd, qp_init_attr);
1439 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1441 ibdev_err(&rdev->ibdev, "Failed to create HW QP");
1445 struct bnxt_re_qp_resp resp;
1447 resp.qpid = qp->qplib_qp.id;
1449 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1451 ibdev_err(&rdev->ibdev, "Failed to copy QP udata");
1457 qp->ib_qp.qp_num = qp->qplib_qp.id;
1458 if (qp_init_attr->qp_type == IB_QPT_GSI)
1459 rdev->gsi_ctx.gsi_qp = qp;
1460 spin_lock_init(&qp->sq_lock);
1461 spin_lock_init(&qp->rq_lock);
1462 INIT_LIST_HEAD(&qp->list);
1463 mutex_lock(&rdev->qp_lock);
1464 list_add_tail(&qp->list, &rdev->qp_list);
1465 mutex_unlock(&rdev->qp_lock);
1466 atomic_inc(&rdev->qp_count);
1470 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1472 ib_umem_release(qp->rumem);
1473 ib_umem_release(qp->sumem);
1480 static u8 __from_ib_qp_state(enum ib_qp_state state)
1484 return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1486 return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1488 return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1490 return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1492 return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1494 return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1497 return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1501 static enum ib_qp_state __to_ib_qp_state(u8 state)
1504 case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1505 return IB_QPS_RESET;
1506 case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1508 case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1510 case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1512 case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1514 case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1516 case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1522 static u32 __from_ib_mtu(enum ib_mtu mtu)
1526 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1528 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1530 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1532 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1534 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1536 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1540 static enum ib_mtu __to_ib_mtu(u32 mtu)
1542 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1543 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1545 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1547 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1549 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1551 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1558 /* Shared Receive Queues */
1559 int bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata)
1561 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1563 struct bnxt_re_dev *rdev = srq->rdev;
1564 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1565 struct bnxt_qplib_nq *nq = NULL;
1568 nq = qplib_srq->cq->nq;
1569 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq);
1570 ib_umem_release(srq->umem);
1571 atomic_dec(&rdev->srq_count);
1577 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev,
1578 struct bnxt_re_pd *pd,
1579 struct bnxt_re_srq *srq,
1580 struct ib_udata *udata)
1582 struct bnxt_re_srq_req ureq;
1583 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq;
1584 struct ib_umem *umem;
1586 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context(
1587 udata, struct bnxt_re_ucontext, ib_uctx);
1589 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
1592 bytes = (qplib_srq->max_wqe * qplib_srq->wqe_size);
1593 bytes = PAGE_ALIGN(bytes);
1594 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes,
1595 IB_ACCESS_LOCAL_WRITE);
1597 return PTR_ERR(umem);
1600 qplib_srq->sg_info.umem = umem;
1601 qplib_srq->sg_info.pgsize = PAGE_SIZE;
1602 qplib_srq->sg_info.pgshft = PAGE_SHIFT;
1603 qplib_srq->srq_handle = ureq.srq_handle;
1604 qplib_srq->dpi = &cntx->dpi;
1609 int bnxt_re_create_srq(struct ib_srq *ib_srq,
1610 struct ib_srq_init_attr *srq_init_attr,
1611 struct ib_udata *udata)
1613 struct bnxt_qplib_dev_attr *dev_attr;
1614 struct bnxt_qplib_nq *nq = NULL;
1615 struct bnxt_re_dev *rdev;
1616 struct bnxt_re_srq *srq;
1617 struct bnxt_re_pd *pd;
1618 struct ib_pd *ib_pd;
1622 pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1624 dev_attr = &rdev->dev_attr;
1625 srq = container_of(ib_srq, struct bnxt_re_srq, ib_srq);
1627 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) {
1628 ibdev_err(&rdev->ibdev, "Create CQ failed - max exceeded");
1633 if (srq_init_attr->srq_type != IB_SRQT_BASIC) {
1639 srq->qplib_srq.pd = &pd->qplib_pd;
1640 srq->qplib_srq.dpi = &rdev->dpi_privileged;
1641 /* Allocate 1 more than what's provided so posting max doesn't
1644 entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1);
1645 if (entries > dev_attr->max_srq_wqes + 1)
1646 entries = dev_attr->max_srq_wqes + 1;
1647 srq->qplib_srq.max_wqe = entries;
1649 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge;
1650 /* 128 byte wqe size for SRQ . So use max sges */
1651 srq->qplib_srq.wqe_size = bnxt_re_get_rwqe_size(dev_attr->max_srq_sges);
1652 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit;
1653 srq->srq_limit = srq_init_attr->attr.srq_limit;
1654 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id;
1658 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata);
1663 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq);
1665 ibdev_err(&rdev->ibdev, "Create HW SRQ failed!");
1670 struct bnxt_re_srq_resp resp;
1672 resp.srqid = srq->qplib_srq.id;
1673 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1675 ibdev_err(&rdev->ibdev, "SRQ copy to udata failed!");
1676 bnxt_qplib_destroy_srq(&rdev->qplib_res,
1683 atomic_inc(&rdev->srq_count);
1688 ib_umem_release(srq->umem);
1693 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr,
1694 enum ib_srq_attr_mask srq_attr_mask,
1695 struct ib_udata *udata)
1697 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1699 struct bnxt_re_dev *rdev = srq->rdev;
1702 switch (srq_attr_mask) {
1704 /* SRQ resize is not supported */
1707 /* Change the SRQ threshold */
1708 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe)
1711 srq->qplib_srq.threshold = srq_attr->srq_limit;
1712 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq);
1714 ibdev_err(&rdev->ibdev, "Modify HW SRQ failed!");
1717 /* On success, update the shadow */
1718 srq->srq_limit = srq_attr->srq_limit;
1719 /* No need to Build and send response back to udata */
1722 ibdev_err(&rdev->ibdev,
1723 "Unsupported srq_attr_mask 0x%x", srq_attr_mask);
1729 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr)
1731 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1733 struct bnxt_re_srq tsrq;
1734 struct bnxt_re_dev *rdev = srq->rdev;
1737 /* Get live SRQ attr */
1738 tsrq.qplib_srq.id = srq->qplib_srq.id;
1739 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq);
1741 ibdev_err(&rdev->ibdev, "Query HW SRQ failed!");
1744 srq_attr->max_wr = srq->qplib_srq.max_wqe;
1745 srq_attr->max_sge = srq->qplib_srq.max_sge;
1746 srq_attr->srq_limit = tsrq.qplib_srq.threshold;
1751 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr,
1752 const struct ib_recv_wr **bad_wr)
1754 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq,
1756 struct bnxt_qplib_swqe wqe;
1757 unsigned long flags;
1760 spin_lock_irqsave(&srq->lock, flags);
1762 /* Transcribe each ib_recv_wr to qplib_swqe */
1763 wqe.num_sge = wr->num_sge;
1764 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
1765 wqe.wr_id = wr->wr_id;
1766 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
1768 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe);
1775 spin_unlock_irqrestore(&srq->lock, flags);
1779 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1780 struct bnxt_re_qp *qp1_qp,
1783 struct bnxt_re_qp *qp = rdev->gsi_ctx.gsi_sqp;
1786 if (qp_attr_mask & IB_QP_STATE) {
1787 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1788 qp->qplib_qp.state = qp1_qp->qplib_qp.state;
1790 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1791 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1792 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
1795 if (qp_attr_mask & IB_QP_QKEY) {
1796 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1797 /* Using a Random QKEY */
1798 qp->qplib_qp.qkey = 0x81818181;
1800 if (qp_attr_mask & IB_QP_SQ_PSN) {
1801 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1802 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
1805 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1807 ibdev_err(&rdev->ibdev, "Failed to modify Shadow QP for QP1");
1811 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1812 int qp_attr_mask, struct ib_udata *udata)
1814 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1815 struct bnxt_re_dev *rdev = qp->rdev;
1816 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1817 enum ib_qp_state curr_qp_state, new_qp_state;
1822 if (qp_attr_mask & ~IB_QP_ATTR_STANDARD_BITS)
1825 qp->qplib_qp.modify_flags = 0;
1826 if (qp_attr_mask & IB_QP_STATE) {
1827 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
1828 new_qp_state = qp_attr->qp_state;
1829 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
1830 ib_qp->qp_type, qp_attr_mask)) {
1831 ibdev_err(&rdev->ibdev,
1832 "Invalid attribute mask: %#x specified ",
1834 ibdev_err(&rdev->ibdev,
1835 "for qpn: %#x type: %#x",
1836 ib_qp->qp_num, ib_qp->qp_type);
1837 ibdev_err(&rdev->ibdev,
1838 "curr_qp_state=0x%x, new_qp_state=0x%x\n",
1839 curr_qp_state, new_qp_state);
1842 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1843 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
1846 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1847 ibdev_dbg(&rdev->ibdev,
1848 "Move QP = %p to flush list\n", qp);
1849 flags = bnxt_re_lock_cqs(qp);
1850 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1851 bnxt_re_unlock_cqs(qp, flags);
1854 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
1855 ibdev_dbg(&rdev->ibdev,
1856 "Move QP = %p out of flush list\n", qp);
1857 flags = bnxt_re_lock_cqs(qp);
1858 bnxt_qplib_clean_qp(&qp->qplib_qp);
1859 bnxt_re_unlock_cqs(qp, flags);
1862 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
1863 qp->qplib_qp.modify_flags |=
1864 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
1865 qp->qplib_qp.en_sqd_async_notify = true;
1867 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
1868 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
1869 qp->qplib_qp.access =
1870 __from_ib_access_flags(qp_attr->qp_access_flags);
1871 /* LOCAL_WRITE access must be set to allow RC receive */
1872 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
1873 /* Temp: Set all params on QP as of now */
1874 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE;
1875 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ;
1877 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1878 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1879 qp->qplib_qp.pkey_index = qp_attr->pkey_index;
1881 if (qp_attr_mask & IB_QP_QKEY) {
1882 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1883 qp->qplib_qp.qkey = qp_attr->qkey;
1885 if (qp_attr_mask & IB_QP_AV) {
1886 const struct ib_global_route *grh =
1887 rdma_ah_read_grh(&qp_attr->ah_attr);
1888 const struct ib_gid_attr *sgid_attr;
1889 struct bnxt_re_gid_ctx *ctx;
1891 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
1892 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
1893 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
1894 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
1895 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
1896 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
1897 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
1898 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
1899 sizeof(qp->qplib_qp.ah.dgid.data));
1900 qp->qplib_qp.ah.flow_label = grh->flow_label;
1901 sgid_attr = grh->sgid_attr;
1902 /* Get the HW context of the GID. The reference
1903 * of GID table entry is already taken by the caller.
1905 ctx = rdma_read_gid_hw_context(sgid_attr);
1906 qp->qplib_qp.ah.sgid_index = ctx->idx;
1907 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
1908 qp->qplib_qp.ah.hop_limit = grh->hop_limit;
1909 qp->qplib_qp.ah.traffic_class = grh->traffic_class;
1910 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
1911 ether_addr_copy(qp->qplib_qp.ah.dmac,
1912 qp_attr->ah_attr.roce.dmac);
1914 rc = rdma_read_gid_l2_fields(sgid_attr, NULL,
1915 &qp->qplib_qp.smac[0]);
1919 nw_type = rdma_gid_attr_network_type(sgid_attr);
1921 case RDMA_NETWORK_IPV4:
1922 qp->qplib_qp.nw_type =
1923 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
1925 case RDMA_NETWORK_IPV6:
1926 qp->qplib_qp.nw_type =
1927 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
1930 qp->qplib_qp.nw_type =
1931 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
1936 if (qp_attr_mask & IB_QP_PATH_MTU) {
1937 qp->qplib_qp.modify_flags |=
1938 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1939 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
1940 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
1941 } else if (qp_attr->qp_state == IB_QPS_RTR) {
1942 qp->qplib_qp.modify_flags |=
1943 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1944 qp->qplib_qp.path_mtu =
1945 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
1947 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1950 if (qp_attr_mask & IB_QP_TIMEOUT) {
1951 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
1952 qp->qplib_qp.timeout = qp_attr->timeout;
1954 if (qp_attr_mask & IB_QP_RETRY_CNT) {
1955 qp->qplib_qp.modify_flags |=
1956 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
1957 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
1959 if (qp_attr_mask & IB_QP_RNR_RETRY) {
1960 qp->qplib_qp.modify_flags |=
1961 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
1962 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
1964 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
1965 qp->qplib_qp.modify_flags |=
1966 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
1967 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
1969 if (qp_attr_mask & IB_QP_RQ_PSN) {
1970 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
1971 qp->qplib_qp.rq.psn = qp_attr->rq_psn;
1973 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1974 qp->qplib_qp.modify_flags |=
1975 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
1976 /* Cap the max_rd_atomic to device max */
1977 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
1978 dev_attr->max_qp_rd_atom);
1980 if (qp_attr_mask & IB_QP_SQ_PSN) {
1981 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1982 qp->qplib_qp.sq.psn = qp_attr->sq_psn;
1984 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1985 if (qp_attr->max_dest_rd_atomic >
1986 dev_attr->max_qp_init_rd_atom) {
1987 ibdev_err(&rdev->ibdev,
1988 "max_dest_rd_atomic requested%d is > dev_max%d",
1989 qp_attr->max_dest_rd_atomic,
1990 dev_attr->max_qp_init_rd_atom);
1994 qp->qplib_qp.modify_flags |=
1995 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
1996 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
1998 if (qp_attr_mask & IB_QP_CAP) {
1999 qp->qplib_qp.modify_flags |=
2000 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
2001 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
2002 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
2003 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
2004 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
2005 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
2006 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
2007 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
2008 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
2009 (qp_attr->cap.max_inline_data >=
2010 dev_attr->max_inline_data)) {
2011 ibdev_err(&rdev->ibdev,
2012 "Create QP failed - max exceeded");
2015 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
2016 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
2017 dev_attr->max_qp_wqes + 1);
2018 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
2019 qp_attr->cap.max_send_wr;
2021 * Reserving one slot for Phantom WQE. Some application can
2022 * post one extra entry in this case. Allowing this to avoid
2023 * unexpected Queue full condition
2025 qp->qplib_qp.sq.q_full_delta -= 1;
2026 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
2027 if (qp->qplib_qp.rq.max_wqe) {
2028 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
2029 qp->qplib_qp.rq.max_wqe =
2030 min_t(u32, entries, dev_attr->max_qp_wqes + 1);
2031 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
2032 qp_attr->cap.max_recv_wr;
2033 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
2035 /* SRQ was used prior, just ignore the RQ caps */
2038 if (qp_attr_mask & IB_QP_DEST_QPN) {
2039 qp->qplib_qp.modify_flags |=
2040 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
2041 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
2043 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
2045 ibdev_err(&rdev->ibdev, "Failed to modify HW QP");
2048 if (ib_qp->qp_type == IB_QPT_GSI && rdev->gsi_ctx.gsi_sqp)
2049 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
2053 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
2054 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
2056 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2057 struct bnxt_re_dev *rdev = qp->rdev;
2058 struct bnxt_qplib_qp *qplib_qp;
2061 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
2065 qplib_qp->id = qp->qplib_qp.id;
2066 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
2068 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
2070 ibdev_err(&rdev->ibdev, "Failed to query HW QP");
2073 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
2074 qp_attr->cur_qp_state = __to_ib_qp_state(qplib_qp->cur_qp_state);
2075 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
2076 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access);
2077 qp_attr->pkey_index = qplib_qp->pkey_index;
2078 qp_attr->qkey = qplib_qp->qkey;
2079 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
2080 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
2081 qplib_qp->ah.host_sgid_index,
2082 qplib_qp->ah.hop_limit,
2083 qplib_qp->ah.traffic_class);
2084 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
2085 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
2086 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
2087 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
2088 qp_attr->timeout = qplib_qp->timeout;
2089 qp_attr->retry_cnt = qplib_qp->retry_cnt;
2090 qp_attr->rnr_retry = qplib_qp->rnr_retry;
2091 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
2092 qp_attr->rq_psn = qplib_qp->rq.psn;
2093 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
2094 qp_attr->sq_psn = qplib_qp->sq.psn;
2095 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
2096 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
2098 qp_attr->dest_qp_num = qplib_qp->dest_qpn;
2100 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
2101 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
2102 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
2103 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
2104 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
2105 qp_init_attr->cap = qp_attr->cap;
2112 /* Routine for sending QP1 packets for RoCE V1 an V2
2114 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
2115 const struct ib_send_wr *wr,
2116 struct bnxt_qplib_swqe *wqe,
2119 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
2121 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
2122 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr;
2123 struct bnxt_qplib_sge sge;
2127 bool is_eth = false;
2128 bool is_vlan = false;
2129 bool is_grh = false;
2130 bool is_udp = false;
2132 u16 vlan_id = 0xFFFF;
2136 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
2138 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL);
2142 /* Get network header type for this GID */
2143 nw_type = rdma_gid_attr_network_type(sgid_attr);
2145 case RDMA_NETWORK_IPV4:
2146 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
2148 case RDMA_NETWORK_IPV6:
2149 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
2152 nw_type = BNXT_RE_ROCE_V1_PACKET;
2155 memcpy(&dgid.raw, &qplib_ah->dgid, 16);
2156 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2158 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) {
2160 ether_type = ETH_P_IP;
2163 ether_type = ETH_P_IPV6;
2167 ether_type = ETH_P_IBOE;
2172 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false;
2174 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
2175 ip_version, is_udp, 0, &qp->qp1_hdr);
2178 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
2179 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
2181 /* For vlan, check the sgid for vlan existence */
2184 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
2186 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
2187 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
2190 if (is_grh || (ip_version == 6)) {
2191 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw,
2192 sizeof(sgid_attr->gid));
2193 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
2194 sizeof(sgid_attr->gid));
2195 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit;
2198 if (ip_version == 4) {
2199 qp->qp1_hdr.ip4.tos = 0;
2200 qp->qp1_hdr.ip4.id = 0;
2201 qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
2202 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
2204 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4);
2205 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
2206 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
2210 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
2211 qp->qp1_hdr.udp.sport = htons(0x8CD1);
2212 qp->qp1_hdr.udp.csum = 0;
2216 if (wr->opcode == IB_WR_SEND_WITH_IMM) {
2217 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
2218 qp->qp1_hdr.immediate_present = 1;
2220 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2222 if (wr->send_flags & IB_SEND_SOLICITED)
2223 qp->qp1_hdr.bth.solicited_event = 1;
2225 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
2227 /* P_key for QP1 is for all members */
2228 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
2229 qp->qp1_hdr.bth.destination_qpn = IB_QP1;
2230 qp->qp1_hdr.bth.ack_req = 0;
2232 qp->send_psn &= BTH_PSN_MASK;
2233 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
2235 /* Use the priviledged Q_Key for QP1 */
2236 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
2237 qp->qp1_hdr.deth.source_qpn = IB_QP1;
2239 /* Pack the QP1 to the transmit buffer */
2240 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
2242 ib_ud_header_pack(&qp->qp1_hdr, buf);
2243 for (i = wqe->num_sge; i; i--) {
2244 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
2245 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
2246 wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
2250 * Max Header buf size for IPV6 RoCE V2 is 86,
2251 * which is same as the QP1 SQ header buffer.
2252 * Header buf size for IPV4 RoCE V2 can be 66.
2253 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
2254 * Subtract 20 bytes from QP1 SQ header buf size
2256 if (is_udp && ip_version == 4)
2259 * Max Header buf size for RoCE V1 is 78.
2260 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
2261 * Subtract 8 bytes from QP1 SQ header buf size
2266 /* Subtract 4 bytes for non vlan packets */
2270 wqe->sg_list[0].addr = sge.addr;
2271 wqe->sg_list[0].lkey = sge.lkey;
2272 wqe->sg_list[0].size = sge.size;
2276 ibdev_err(&qp->rdev->ibdev, "QP1 buffer is empty!");
2282 /* For the MAD layer, it only provides the recv SGE the size of
2283 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH,
2284 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire
2285 * receive packet (334 bytes) with no VLAN and then copy the GRH
2286 * and the MAD datagram out to the provided SGE.
2288 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
2289 const struct ib_recv_wr *wr,
2290 struct bnxt_qplib_swqe *wqe,
2293 struct bnxt_re_sqp_entries *sqp_entry;
2294 struct bnxt_qplib_sge ref, sge;
2295 struct bnxt_re_dev *rdev;
2300 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
2302 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
2305 /* Create 1 SGE to receive the entire
2308 /* Save the reference from ULP */
2309 ref.addr = wqe->sg_list[0].addr;
2310 ref.lkey = wqe->sg_list[0].lkey;
2311 ref.size = wqe->sg_list[0].size;
2313 sqp_entry = &rdev->gsi_ctx.sqp_tbl[rq_prod_index];
2316 wqe->sg_list[0].addr = sge.addr;
2317 wqe->sg_list[0].lkey = sge.lkey;
2318 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
2319 sge.size -= wqe->sg_list[0].size;
2321 sqp_entry->sge.addr = ref.addr;
2322 sqp_entry->sge.lkey = ref.lkey;
2323 sqp_entry->sge.size = ref.size;
2324 /* Store the wrid for reporting completion */
2325 sqp_entry->wrid = wqe->wr_id;
2326 /* change the wqe->wrid to table index */
2327 wqe->wr_id = rq_prod_index;
2331 static int is_ud_qp(struct bnxt_re_qp *qp)
2333 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD ||
2334 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI);
2337 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
2338 const struct ib_send_wr *wr,
2339 struct bnxt_qplib_swqe *wqe)
2341 struct bnxt_re_ah *ah = NULL;
2344 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
2345 wqe->send.q_key = ud_wr(wr)->remote_qkey;
2346 wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
2347 wqe->send.avid = ah->qplib_ah.id;
2349 switch (wr->opcode) {
2351 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
2353 case IB_WR_SEND_WITH_IMM:
2354 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
2355 wqe->send.imm_data = wr->ex.imm_data;
2357 case IB_WR_SEND_WITH_INV:
2358 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
2359 wqe->send.inv_key = wr->ex.invalidate_rkey;
2364 if (wr->send_flags & IB_SEND_SIGNALED)
2365 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2366 if (wr->send_flags & IB_SEND_FENCE)
2367 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2368 if (wr->send_flags & IB_SEND_SOLICITED)
2369 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2370 if (wr->send_flags & IB_SEND_INLINE)
2371 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2376 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr,
2377 struct bnxt_qplib_swqe *wqe)
2379 switch (wr->opcode) {
2380 case IB_WR_RDMA_WRITE:
2381 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
2383 case IB_WR_RDMA_WRITE_WITH_IMM:
2384 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
2385 wqe->rdma.imm_data = wr->ex.imm_data;
2387 case IB_WR_RDMA_READ:
2388 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
2389 wqe->rdma.inv_key = wr->ex.invalidate_rkey;
2394 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
2395 wqe->rdma.r_key = rdma_wr(wr)->rkey;
2396 if (wr->send_flags & IB_SEND_SIGNALED)
2397 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2398 if (wr->send_flags & IB_SEND_FENCE)
2399 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2400 if (wr->send_flags & IB_SEND_SOLICITED)
2401 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2402 if (wr->send_flags & IB_SEND_INLINE)
2403 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
2408 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr,
2409 struct bnxt_qplib_swqe *wqe)
2411 switch (wr->opcode) {
2412 case IB_WR_ATOMIC_CMP_AND_SWP:
2413 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
2414 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2415 wqe->atomic.swap_data = atomic_wr(wr)->swap;
2417 case IB_WR_ATOMIC_FETCH_AND_ADD:
2418 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
2419 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
2424 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
2425 wqe->atomic.r_key = atomic_wr(wr)->rkey;
2426 if (wr->send_flags & IB_SEND_SIGNALED)
2427 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2428 if (wr->send_flags & IB_SEND_FENCE)
2429 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2430 if (wr->send_flags & IB_SEND_SOLICITED)
2431 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2435 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr,
2436 struct bnxt_qplib_swqe *wqe)
2438 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
2439 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
2441 /* Need unconditional fence for local invalidate
2442 * opcode to work as expected.
2444 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2446 if (wr->send_flags & IB_SEND_SIGNALED)
2447 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2448 if (wr->send_flags & IB_SEND_SOLICITED)
2449 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
2454 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr,
2455 struct bnxt_qplib_swqe *wqe)
2457 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
2458 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
2459 int access = wr->access;
2461 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
2462 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
2463 wqe->frmr.page_list = mr->pages;
2464 wqe->frmr.page_list_len = mr->npages;
2465 wqe->frmr.levels = qplib_frpl->hwq.level;
2466 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
2468 /* Need unconditional fence for reg_mr
2469 * opcode to function as expected.
2472 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
2474 if (wr->wr.send_flags & IB_SEND_SIGNALED)
2475 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
2477 if (access & IB_ACCESS_LOCAL_WRITE)
2478 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
2479 if (access & IB_ACCESS_REMOTE_READ)
2480 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
2481 if (access & IB_ACCESS_REMOTE_WRITE)
2482 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
2483 if (access & IB_ACCESS_REMOTE_ATOMIC)
2484 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
2485 if (access & IB_ACCESS_MW_BIND)
2486 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2488 wqe->frmr.l_key = wr->key;
2489 wqe->frmr.length = wr->mr->length;
2490 wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1;
2491 wqe->frmr.va = wr->mr->iova;
2495 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2496 const struct ib_send_wr *wr,
2497 struct bnxt_qplib_swqe *wqe)
2499 /* Copy the inline data to the data field */
2504 in_data = wqe->inline_data;
2505 for (i = 0; i < wr->num_sge; i++) {
2506 sge_addr = (void *)(unsigned long)
2507 wr->sg_list[i].addr;
2508 sge_len = wr->sg_list[i].length;
2510 if ((sge_len + wqe->inline_len) >
2511 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2512 ibdev_err(&rdev->ibdev,
2513 "Inline data size requested > supported value");
2516 sge_len = wr->sg_list[i].length;
2518 memcpy(in_data, sge_addr, sge_len);
2519 in_data += wr->sg_list[i].length;
2520 wqe->inline_len += wr->sg_list[i].length;
2522 return wqe->inline_len;
2525 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2526 const struct ib_send_wr *wr,
2527 struct bnxt_qplib_swqe *wqe)
2531 if (wr->send_flags & IB_SEND_INLINE)
2532 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2534 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2540 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2542 if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2543 qp->ib_qp.qp_type == IB_QPT_GSI ||
2544 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2545 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2547 struct ib_qp_attr qp_attr;
2549 qp_attr_mask = IB_QP_STATE;
2550 qp_attr.qp_state = IB_QPS_RTS;
2551 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2552 qp->qplib_qp.wqe_cnt = 0;
2556 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2557 struct bnxt_re_qp *qp,
2558 const struct ib_send_wr *wr)
2560 int rc = 0, payload_sz = 0;
2561 unsigned long flags;
2563 spin_lock_irqsave(&qp->sq_lock, flags);
2565 struct bnxt_qplib_swqe wqe = {};
2568 wqe.num_sge = wr->num_sge;
2569 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2570 ibdev_err(&rdev->ibdev,
2571 "Limit exceeded for Send SGEs");
2576 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2577 if (payload_sz < 0) {
2581 wqe.wr_id = wr->wr_id;
2583 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2585 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2587 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2590 ibdev_err(&rdev->ibdev,
2591 "Post send failed opcode = %#x rc = %d",
2597 bnxt_qplib_post_send_db(&qp->qplib_qp);
2598 bnxt_ud_qp_hw_stall_workaround(qp);
2599 spin_unlock_irqrestore(&qp->sq_lock, flags);
2603 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr,
2604 const struct ib_send_wr **bad_wr)
2606 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2607 struct bnxt_qplib_swqe wqe;
2608 int rc = 0, payload_sz = 0;
2609 unsigned long flags;
2611 spin_lock_irqsave(&qp->sq_lock, flags);
2614 memset(&wqe, 0, sizeof(wqe));
2617 wqe.num_sge = wr->num_sge;
2618 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2619 ibdev_err(&qp->rdev->ibdev,
2620 "Limit exceeded for Send SGEs");
2625 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2626 if (payload_sz < 0) {
2630 wqe.wr_id = wr->wr_id;
2632 switch (wr->opcode) {
2634 case IB_WR_SEND_WITH_IMM:
2635 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) {
2636 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2640 wqe.rawqp1.lflags |=
2641 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2643 switch (wr->send_flags) {
2644 case IB_SEND_IP_CSUM:
2645 wqe.rawqp1.lflags |=
2646 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2652 case IB_WR_SEND_WITH_INV:
2653 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2655 case IB_WR_RDMA_WRITE:
2656 case IB_WR_RDMA_WRITE_WITH_IMM:
2657 case IB_WR_RDMA_READ:
2658 rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2660 case IB_WR_ATOMIC_CMP_AND_SWP:
2661 case IB_WR_ATOMIC_FETCH_AND_ADD:
2662 rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2664 case IB_WR_RDMA_READ_WITH_INV:
2665 ibdev_err(&qp->rdev->ibdev,
2666 "RDMA Read with Invalidate is not supported");
2669 case IB_WR_LOCAL_INV:
2670 rc = bnxt_re_build_inv_wqe(wr, &wqe);
2673 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2676 /* Unsupported WRs */
2677 ibdev_err(&qp->rdev->ibdev,
2678 "WR (%#x) is not supported", wr->opcode);
2683 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2686 ibdev_err(&qp->rdev->ibdev,
2687 "post_send failed op:%#x qps = %#x rc = %d\n",
2688 wr->opcode, qp->qplib_qp.state, rc);
2694 bnxt_qplib_post_send_db(&qp->qplib_qp);
2695 bnxt_ud_qp_hw_stall_workaround(qp);
2696 spin_unlock_irqrestore(&qp->sq_lock, flags);
2701 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2702 struct bnxt_re_qp *qp,
2703 const struct ib_recv_wr *wr)
2705 struct bnxt_qplib_swqe wqe;
2708 memset(&wqe, 0, sizeof(wqe));
2711 memset(&wqe, 0, sizeof(wqe));
2714 wqe.num_sge = wr->num_sge;
2715 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2716 ibdev_err(&rdev->ibdev,
2717 "Limit exceeded for Receive SGEs");
2721 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2722 wqe.wr_id = wr->wr_id;
2723 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2725 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2732 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2736 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr,
2737 const struct ib_recv_wr **bad_wr)
2739 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2740 struct bnxt_qplib_swqe wqe;
2741 int rc = 0, payload_sz = 0;
2742 unsigned long flags;
2745 spin_lock_irqsave(&qp->rq_lock, flags);
2748 memset(&wqe, 0, sizeof(wqe));
2751 wqe.num_sge = wr->num_sge;
2752 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2753 ibdev_err(&qp->rdev->ibdev,
2754 "Limit exceeded for Receive SGEs");
2760 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2762 wqe.wr_id = wr->wr_id;
2763 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2765 if (ib_qp->qp_type == IB_QPT_GSI &&
2766 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI)
2767 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
2770 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2776 /* Ring DB if the RQEs posted reaches a threshold value */
2777 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
2778 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2786 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2788 spin_unlock_irqrestore(&qp->rq_lock, flags);
2793 /* Completion Queues */
2794 int bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata)
2796 struct bnxt_re_cq *cq;
2797 struct bnxt_qplib_nq *nq;
2798 struct bnxt_re_dev *rdev;
2800 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2802 nq = cq->qplib_cq.nq;
2804 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2805 ib_umem_release(cq->umem);
2807 atomic_dec(&rdev->cq_count);
2813 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
2814 struct ib_udata *udata)
2816 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev);
2817 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
2818 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq);
2820 int cqe = attr->cqe;
2821 struct bnxt_qplib_nq *nq = NULL;
2822 unsigned int nq_alloc_cnt;
2827 /* Validate CQ fields */
2828 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
2829 ibdev_err(&rdev->ibdev, "Failed to create CQ -max exceeded");
2834 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
2836 entries = roundup_pow_of_two(cqe + 1);
2837 if (entries > dev_attr->max_cq_wqes + 1)
2838 entries = dev_attr->max_cq_wqes + 1;
2840 cq->qplib_cq.sg_info.pgsize = PAGE_SIZE;
2841 cq->qplib_cq.sg_info.pgshft = PAGE_SHIFT;
2843 struct bnxt_re_cq_req req;
2844 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context(
2845 udata, struct bnxt_re_ucontext, ib_uctx);
2846 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
2851 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va,
2852 entries * sizeof(struct cq_base),
2853 IB_ACCESS_LOCAL_WRITE);
2854 if (IS_ERR(cq->umem)) {
2855 rc = PTR_ERR(cq->umem);
2858 cq->qplib_cq.sg_info.umem = cq->umem;
2859 cq->qplib_cq.dpi = &uctx->dpi;
2861 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
2862 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
2869 cq->qplib_cq.dpi = &rdev->dpi_privileged;
2872 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a
2873 * used for getting the NQ index.
2875 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt);
2876 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)];
2877 cq->qplib_cq.max_wqe = entries;
2878 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id;
2879 cq->qplib_cq.nq = nq;
2881 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
2883 ibdev_err(&rdev->ibdev, "Failed to create HW CQ");
2887 cq->ib_cq.cqe = entries;
2888 cq->cq_period = cq->qplib_cq.period;
2891 atomic_inc(&rdev->cq_count);
2892 spin_lock_init(&cq->cq_lock);
2895 struct bnxt_re_cq_resp resp;
2897 resp.cqid = cq->qplib_cq.id;
2898 resp.tail = cq->qplib_cq.hwq.cons;
2899 resp.phase = cq->qplib_cq.period;
2901 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
2903 ibdev_err(&rdev->ibdev, "Failed to copy CQ udata");
2904 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2912 ib_umem_release(cq->umem);
2918 static u8 __req_to_ib_wc_status(u8 qstatus)
2921 case CQ_REQ_STATUS_OK:
2922 return IB_WC_SUCCESS;
2923 case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
2924 return IB_WC_BAD_RESP_ERR;
2925 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
2926 return IB_WC_LOC_LEN_ERR;
2927 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
2928 return IB_WC_LOC_QP_OP_ERR;
2929 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
2930 return IB_WC_LOC_PROT_ERR;
2931 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
2932 return IB_WC_GENERAL_ERR;
2933 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
2934 return IB_WC_REM_INV_REQ_ERR;
2935 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
2936 return IB_WC_REM_ACCESS_ERR;
2937 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
2938 return IB_WC_REM_OP_ERR;
2939 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
2940 return IB_WC_RNR_RETRY_EXC_ERR;
2941 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
2942 return IB_WC_RETRY_EXC_ERR;
2943 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
2944 return IB_WC_WR_FLUSH_ERR;
2946 return IB_WC_GENERAL_ERR;
2951 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
2954 case CQ_RES_RAWETH_QP1_STATUS_OK:
2955 return IB_WC_SUCCESS;
2956 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
2957 return IB_WC_LOC_ACCESS_ERR;
2958 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
2959 return IB_WC_LOC_LEN_ERR;
2960 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
2961 return IB_WC_LOC_PROT_ERR;
2962 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
2963 return IB_WC_LOC_QP_OP_ERR;
2964 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
2965 return IB_WC_GENERAL_ERR;
2966 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
2967 return IB_WC_WR_FLUSH_ERR;
2968 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
2969 return IB_WC_WR_FLUSH_ERR;
2971 return IB_WC_GENERAL_ERR;
2975 static u8 __rc_to_ib_wc_status(u8 qstatus)
2978 case CQ_RES_RC_STATUS_OK:
2979 return IB_WC_SUCCESS;
2980 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
2981 return IB_WC_LOC_ACCESS_ERR;
2982 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
2983 return IB_WC_LOC_LEN_ERR;
2984 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
2985 return IB_WC_LOC_PROT_ERR;
2986 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
2987 return IB_WC_LOC_QP_OP_ERR;
2988 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
2989 return IB_WC_GENERAL_ERR;
2990 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
2991 return IB_WC_REM_INV_REQ_ERR;
2992 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
2993 return IB_WC_WR_FLUSH_ERR;
2994 case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
2995 return IB_WC_WR_FLUSH_ERR;
2997 return IB_WC_GENERAL_ERR;
3001 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
3003 switch (cqe->type) {
3004 case BNXT_QPLIB_SWQE_TYPE_SEND:
3005 wc->opcode = IB_WC_SEND;
3007 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
3008 wc->opcode = IB_WC_SEND;
3009 wc->wc_flags |= IB_WC_WITH_IMM;
3011 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
3012 wc->opcode = IB_WC_SEND;
3013 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3015 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
3016 wc->opcode = IB_WC_RDMA_WRITE;
3018 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
3019 wc->opcode = IB_WC_RDMA_WRITE;
3020 wc->wc_flags |= IB_WC_WITH_IMM;
3022 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
3023 wc->opcode = IB_WC_RDMA_READ;
3025 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
3026 wc->opcode = IB_WC_COMP_SWAP;
3028 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
3029 wc->opcode = IB_WC_FETCH_ADD;
3031 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
3032 wc->opcode = IB_WC_LOCAL_INV;
3034 case BNXT_QPLIB_SWQE_TYPE_REG_MR:
3035 wc->opcode = IB_WC_REG_MR;
3038 wc->opcode = IB_WC_SEND;
3042 wc->status = __req_to_ib_wc_status(cqe->status);
3045 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
3046 u16 raweth_qp1_flags2)
3048 bool is_ipv6 = false, is_ipv4 = false;
3050 /* raweth_qp1_flags Bit 9-6 indicates itype */
3051 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3052 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
3055 if (raweth_qp1_flags2 &
3056 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
3058 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
3059 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
3060 (raweth_qp1_flags2 &
3061 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
3062 (is_ipv6 = true) : (is_ipv4 = true);
3064 BNXT_RE_ROCEV2_IPV6_PACKET :
3065 BNXT_RE_ROCEV2_IPV4_PACKET);
3067 return BNXT_RE_ROCE_V1_PACKET;
3071 static int bnxt_re_to_ib_nw_type(int nw_type)
3073 u8 nw_hdr_type = 0xFF;
3076 case BNXT_RE_ROCE_V1_PACKET:
3077 nw_hdr_type = RDMA_NETWORK_ROCE_V1;
3079 case BNXT_RE_ROCEV2_IPV4_PACKET:
3080 nw_hdr_type = RDMA_NETWORK_IPV4;
3082 case BNXT_RE_ROCEV2_IPV6_PACKET:
3083 nw_hdr_type = RDMA_NETWORK_IPV6;
3089 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
3093 struct ethhdr *eth_hdr;
3097 tmp_buf = (u8 *)rq_hdr_buf;
3099 * If dest mac is not same as I/F mac, this could be a
3100 * loopback address or multicast address, check whether
3101 * it is a loopback packet
3103 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
3105 /* Check the ether type */
3106 eth_hdr = (struct ethhdr *)tmp_buf;
3107 eth_type = ntohs(eth_hdr->h_proto);
3115 struct udphdr *udp_hdr;
3117 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
3118 sizeof(struct ipv6hdr));
3119 tmp_buf += sizeof(struct ethhdr) + len;
3120 udp_hdr = (struct udphdr *)tmp_buf;
3121 if (ntohs(udp_hdr->dest) ==
3134 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *gsi_qp,
3135 struct bnxt_qplib_cqe *cqe)
3137 struct bnxt_re_dev *rdev = gsi_qp->rdev;
3138 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3139 struct bnxt_re_qp *gsi_sqp = rdev->gsi_ctx.gsi_sqp;
3140 struct bnxt_re_ah *gsi_sah;
3141 struct ib_send_wr *swr;
3142 struct ib_ud_wr udwr;
3143 struct ib_recv_wr rwr;
3147 dma_addr_t rq_hdr_buf_map;
3148 dma_addr_t shrq_hdr_buf_map;
3151 struct ib_sge s_sge[2];
3152 struct ib_sge r_sge[2];
3155 memset(&udwr, 0, sizeof(udwr));
3156 memset(&rwr, 0, sizeof(rwr));
3157 memset(&s_sge, 0, sizeof(s_sge));
3158 memset(&r_sge, 0, sizeof(r_sge));
3161 tbl_idx = cqe->wr_id;
3163 rq_hdr_buf = gsi_qp->qplib_qp.rq_hdr_buf +
3164 (tbl_idx * gsi_qp->qplib_qp.rq_hdr_buf_size);
3165 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3168 /* Shadow QP header buffer */
3169 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&gsi_qp->qplib_qp,
3171 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3173 /* Store this cqe */
3174 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
3175 sqp_entry->qp1_qp = gsi_qp;
3177 /* Find packet type from the cqe */
3179 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
3180 cqe->raweth_qp1_flags2);
3182 ibdev_err(&rdev->ibdev, "Invalid packet\n");
3186 /* Adjust the offset for the user buffer and post in the rq */
3188 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
3192 * QP1 loopback packet has 4 bytes of internal header before
3193 * ether header. Skip these four bytes.
3195 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
3198 /* First send SGE . Skip the ether header*/
3199 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
3201 s_sge[0].lkey = 0xFFFFFFFF;
3202 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
3203 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
3205 /* Second Send SGE */
3206 s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
3207 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
3208 if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
3210 s_sge[1].lkey = 0xFFFFFFFF;
3211 s_sge[1].length = 256;
3213 /* First recv SGE */
3215 r_sge[0].addr = shrq_hdr_buf_map;
3216 r_sge[0].lkey = 0xFFFFFFFF;
3217 r_sge[0].length = 40;
3219 r_sge[1].addr = sqp_entry->sge.addr + offset;
3220 r_sge[1].lkey = sqp_entry->sge.lkey;
3221 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
3223 /* Create receive work request */
3225 rwr.sg_list = r_sge;
3226 rwr.wr_id = tbl_idx;
3229 rc = bnxt_re_post_recv_shadow_qp(rdev, gsi_sqp, &rwr);
3231 ibdev_err(&rdev->ibdev,
3232 "Failed to post Rx buffers to shadow QP");
3237 swr->sg_list = s_sge;
3238 swr->wr_id = tbl_idx;
3239 swr->opcode = IB_WR_SEND;
3241 gsi_sah = rdev->gsi_ctx.gsi_sah;
3242 udwr.ah = &gsi_sah->ib_ah;
3243 udwr.remote_qpn = gsi_sqp->qplib_qp.id;
3244 udwr.remote_qkey = gsi_sqp->qplib_qp.qkey;
3246 /* post data received in the send queue */
3247 rc = bnxt_re_post_send_shadow_qp(rdev, gsi_sqp, swr);
3252 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
3253 struct bnxt_qplib_cqe *cqe)
3255 wc->opcode = IB_WC_RECV;
3256 wc->status = __rawqp1_to_ib_wc_status(cqe->status);
3257 wc->wc_flags |= IB_WC_GRH;
3260 static bool bnxt_re_check_if_vlan_valid(struct bnxt_re_dev *rdev,
3264 * Check if the vlan is configured in the host. If not configured, it
3265 * can be a transparent VLAN. So dont report the vlan id.
3267 if (!__vlan_find_dev_deep_rcu(rdev->netdev,
3268 htons(ETH_P_8021Q), vlan_id))
3273 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
3280 metadata = orig_cqe->raweth_qp1_metadata;
3281 if (orig_cqe->raweth_qp1_flags2 &
3282 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
3284 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
3285 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
3286 if (tpid == ETH_P_8021Q) {
3288 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
3290 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
3291 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
3299 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
3300 struct bnxt_qplib_cqe *cqe)
3302 wc->opcode = IB_WC_RECV;
3303 wc->status = __rc_to_ib_wc_status(cqe->status);
3305 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
3306 wc->wc_flags |= IB_WC_WITH_IMM;
3307 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
3308 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
3309 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
3310 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
3311 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
3314 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *gsi_sqp,
3316 struct bnxt_qplib_cqe *cqe)
3318 struct bnxt_re_dev *rdev = gsi_sqp->rdev;
3319 struct bnxt_re_qp *gsi_qp = NULL;
3320 struct bnxt_qplib_cqe *orig_cqe = NULL;
3321 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3327 tbl_idx = cqe->wr_id;
3329 sqp_entry = &rdev->gsi_ctx.sqp_tbl[tbl_idx];
3330 gsi_qp = sqp_entry->qp1_qp;
3331 orig_cqe = &sqp_entry->cqe;
3333 wc->wr_id = sqp_entry->wrid;
3334 wc->byte_len = orig_cqe->length;
3335 wc->qp = &gsi_qp->ib_qp;
3337 wc->ex.imm_data = orig_cqe->immdata;
3338 wc->src_qp = orig_cqe->src_qp;
3339 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
3340 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
3341 if (bnxt_re_check_if_vlan_valid(rdev, vlan_id)) {
3342 wc->vlan_id = vlan_id;
3344 wc->wc_flags |= IB_WC_WITH_VLAN;
3348 wc->vendor_err = orig_cqe->status;
3350 wc->opcode = IB_WC_RECV;
3351 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
3352 wc->wc_flags |= IB_WC_GRH;
3354 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
3355 orig_cqe->raweth_qp1_flags2);
3357 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3358 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3362 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp,
3364 struct bnxt_qplib_cqe *cqe)
3368 wc->opcode = IB_WC_RECV;
3369 wc->status = __rc_to_ib_wc_status(cqe->status);
3371 if (cqe->flags & CQ_RES_UD_FLAGS_IMM)
3372 wc->wc_flags |= IB_WC_WITH_IMM;
3373 /* report only on GSI QP for Thor */
3374 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) {
3375 wc->wc_flags |= IB_WC_GRH;
3376 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3377 wc->wc_flags |= IB_WC_WITH_SMAC;
3378 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) {
3379 wc->vlan_id = (cqe->cfa_meta & 0xFFF);
3380 if (wc->vlan_id < 0x1000)
3381 wc->wc_flags |= IB_WC_WITH_VLAN;
3383 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >>
3384 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT;
3385 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
3386 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
3391 static int send_phantom_wqe(struct bnxt_re_qp *qp)
3393 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
3394 unsigned long flags;
3397 spin_lock_irqsave(&qp->sq_lock, flags);
3399 rc = bnxt_re_bind_fence_mw(lib_qp);
3401 lib_qp->sq.phantom_wqe_cnt++;
3402 ibdev_dbg(&qp->rdev->ibdev,
3403 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
3404 lib_qp->id, lib_qp->sq.hwq.prod,
3405 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
3406 lib_qp->sq.phantom_wqe_cnt);
3409 spin_unlock_irqrestore(&qp->sq_lock, flags);
3413 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
3415 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3416 struct bnxt_re_qp *qp, *sh_qp;
3417 struct bnxt_qplib_cqe *cqe;
3418 int i, ncqe, budget;
3419 struct bnxt_qplib_q *sq;
3420 struct bnxt_qplib_qp *lib_qp;
3422 struct bnxt_re_sqp_entries *sqp_entry = NULL;
3423 unsigned long flags;
3425 spin_lock_irqsave(&cq->cq_lock, flags);
3426 budget = min_t(u32, num_entries, cq->max_cql);
3427 num_entries = budget;
3429 ibdev_err(&cq->rdev->ibdev, "POLL CQ : no CQL to use");
3435 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
3438 if (sq->send_phantom) {
3439 qp = container_of(lib_qp,
3440 struct bnxt_re_qp, qplib_qp);
3441 if (send_phantom_wqe(qp) == -ENOMEM)
3442 ibdev_err(&cq->rdev->ibdev,
3443 "Phantom failed! Scheduled to send again\n");
3445 sq->send_phantom = false;
3449 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
3456 for (i = 0; i < ncqe; i++, cqe++) {
3457 /* Transcribe each qplib_wqe back to ib_wc */
3458 memset(wc, 0, sizeof(*wc));
3460 wc->wr_id = cqe->wr_id;
3461 wc->byte_len = cqe->length;
3463 ((struct bnxt_qplib_qp *)
3464 (unsigned long)(cqe->qp_handle),
3465 struct bnxt_re_qp, qplib_qp);
3466 wc->qp = &qp->ib_qp;
3467 wc->ex.imm_data = cqe->immdata;
3468 wc->src_qp = cqe->src_qp;
3469 memcpy(wc->smac, cqe->smac, ETH_ALEN);
3471 wc->vendor_err = cqe->status;
3473 switch (cqe->opcode) {
3474 case CQ_BASE_CQE_TYPE_REQ:
3475 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3477 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3478 /* Handle this completion with
3479 * the stored completion
3481 memset(wc, 0, sizeof(*wc));
3484 bnxt_re_process_req_wc(wc, cqe);
3486 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
3490 rc = bnxt_re_process_raw_qp_pkt_rx
3493 memset(wc, 0, sizeof(*wc));
3498 /* Errors need not be looped back.
3499 * But change the wr_id to the one
3500 * stored in the table
3502 tbl_idx = cqe->wr_id;
3503 sqp_entry = &cq->rdev->gsi_ctx.sqp_tbl[tbl_idx];
3504 wc->wr_id = sqp_entry->wrid;
3505 bnxt_re_process_res_rawqp1_wc(wc, cqe);
3507 case CQ_BASE_CQE_TYPE_RES_RC:
3508 bnxt_re_process_res_rc_wc(wc, cqe);
3510 case CQ_BASE_CQE_TYPE_RES_UD:
3511 sh_qp = qp->rdev->gsi_ctx.gsi_sqp;
3513 qp->qplib_qp.id == sh_qp->qplib_qp.id) {
3514 /* Handle this completion with
3515 * the stored completion
3520 bnxt_re_process_res_shadow_qp_wc
3525 bnxt_re_process_res_ud_wc(qp, wc, cqe);
3528 ibdev_err(&cq->rdev->ibdev,
3529 "POLL CQ : type 0x%x not handled",
3538 spin_unlock_irqrestore(&cq->cq_lock, flags);
3539 return num_entries - budget;
3542 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3543 enum ib_cq_notify_flags ib_cqn_flags)
3545 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3546 int type = 0, rc = 0;
3547 unsigned long flags;
3549 spin_lock_irqsave(&cq->cq_lock, flags);
3550 /* Trigger on the very next completion */
3551 if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3552 type = DBC_DBC_TYPE_CQ_ARMALL;
3553 /* Trigger on the next solicited completion */
3554 else if (ib_cqn_flags & IB_CQ_SOLICITED)
3555 type = DBC_DBC_TYPE_CQ_ARMSE;
3557 /* Poll to see if there are missed events */
3558 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3559 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3563 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3566 spin_unlock_irqrestore(&cq->cq_lock, flags);
3570 /* Memory Regions */
3571 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3573 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3574 struct bnxt_re_dev *rdev = pd->rdev;
3575 struct bnxt_re_mr *mr;
3578 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3580 return ERR_PTR(-ENOMEM);
3583 mr->qplib_mr.pd = &pd->qplib_pd;
3584 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3585 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3587 /* Allocate and register 0 as the address */
3588 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3592 mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3593 mr->qplib_mr.total_size = -1; /* Infinte length */
3594 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, NULL, 0,
3599 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3600 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3601 IB_ACCESS_REMOTE_ATOMIC))
3602 mr->ib_mr.rkey = mr->ib_mr.lkey;
3603 atomic_inc(&rdev->mr_count);
3608 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3614 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata)
3616 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3617 struct bnxt_re_dev *rdev = mr->rdev;
3620 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3622 ibdev_err(&rdev->ibdev, "Dereg MR failed: %#x\n", rc);
3627 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
3633 ib_umem_release(mr->ib_umem);
3636 atomic_dec(&rdev->mr_count);
3640 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
3642 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3644 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
3647 mr->pages[mr->npages++] = addr;
3651 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
3652 unsigned int *sg_offset)
3654 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3657 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
3660 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
3663 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3664 struct bnxt_re_dev *rdev = pd->rdev;
3665 struct bnxt_re_mr *mr = NULL;
3668 if (type != IB_MR_TYPE_MEM_REG) {
3669 ibdev_dbg(&rdev->ibdev, "MR type 0x%x not supported", type);
3670 return ERR_PTR(-EINVAL);
3672 if (max_num_sg > MAX_PBL_LVL_1_PGS)
3673 return ERR_PTR(-EINVAL);
3675 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3677 return ERR_PTR(-ENOMEM);
3680 mr->qplib_mr.pd = &pd->qplib_pd;
3681 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
3682 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3684 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3688 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3689 mr->ib_mr.rkey = mr->ib_mr.lkey;
3691 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
3696 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
3697 &mr->qplib_frpl, max_num_sg);
3699 ibdev_err(&rdev->ibdev,
3700 "Failed to allocate HW FR page list");
3704 atomic_inc(&rdev->mr_count);
3710 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3716 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
3717 struct ib_udata *udata)
3719 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3720 struct bnxt_re_dev *rdev = pd->rdev;
3721 struct bnxt_re_mw *mw;
3724 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
3726 return ERR_PTR(-ENOMEM);
3728 mw->qplib_mw.pd = &pd->qplib_pd;
3730 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
3731 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
3732 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
3733 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
3735 ibdev_err(&rdev->ibdev, "Allocate MW failed!");
3738 mw->ib_mw.rkey = mw->qplib_mw.rkey;
3740 atomic_inc(&rdev->mw_count);
3748 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
3750 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
3751 struct bnxt_re_dev *rdev = mw->rdev;
3754 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
3756 ibdev_err(&rdev->ibdev, "Free MW failed: %#x\n", rc);
3761 atomic_dec(&rdev->mw_count);
3766 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
3767 u64 virt_addr, int mr_access_flags,
3768 struct ib_udata *udata)
3770 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3771 struct bnxt_re_dev *rdev = pd->rdev;
3772 struct bnxt_re_mr *mr;
3773 struct ib_umem *umem;
3774 unsigned long page_size;
3777 if (length > BNXT_RE_MAX_MR_SIZE) {
3778 ibdev_err(&rdev->ibdev, "MR Size: %lld > Max supported:%lld\n",
3779 length, BNXT_RE_MAX_MR_SIZE);
3780 return ERR_PTR(-ENOMEM);
3783 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3785 return ERR_PTR(-ENOMEM);
3788 mr->qplib_mr.pd = &pd->qplib_pd;
3789 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3790 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
3792 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3794 ibdev_err(&rdev->ibdev, "Failed to allocate MR");
3797 /* The fixed portion of the rkey is the same as the lkey */
3798 mr->ib_mr.rkey = mr->qplib_mr.rkey;
3800 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags);
3802 ibdev_err(&rdev->ibdev, "Failed to get umem");
3808 mr->qplib_mr.va = virt_addr;
3809 page_size = ib_umem_find_best_pgsz(
3810 umem, BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M, virt_addr);
3812 ibdev_err(&rdev->ibdev, "umem page size unsupported!");
3816 mr->qplib_mr.total_size = length;
3818 umem_pgs = ib_umem_num_dma_blocks(umem, page_size);
3819 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, umem,
3820 umem_pgs, page_size);
3822 ibdev_err(&rdev->ibdev, "Failed to register user MR");
3826 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3827 mr->ib_mr.rkey = mr->qplib_mr.lkey;
3828 atomic_inc(&rdev->mr_count);
3832 ib_umem_release(umem);
3834 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3840 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata)
3842 struct ib_device *ibdev = ctx->device;
3843 struct bnxt_re_ucontext *uctx =
3844 container_of(ctx, struct bnxt_re_ucontext, ib_uctx);
3845 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
3846 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
3847 struct bnxt_re_uctx_resp resp = {};
3848 u32 chip_met_rev_num = 0;
3851 ibdev_dbg(ibdev, "ABI version requested %u", ibdev->ops.uverbs_abi_ver);
3853 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
3854 ibdev_dbg(ibdev, " is different from the device %d ",
3855 BNXT_RE_ABI_VERSION);
3861 uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
3866 spin_lock_init(&uctx->sh_lock);
3868 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX;
3869 chip_met_rev_num = rdev->chip_ctx->chip_num;
3870 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_rev & 0xFF) <<
3871 BNXT_RE_CHIP_ID0_CHIP_REV_SFT;
3872 chip_met_rev_num |= ((u32)rdev->chip_ctx->chip_metal & 0xFF) <<
3873 BNXT_RE_CHIP_ID0_CHIP_MET_SFT;
3874 resp.chip_id0 = chip_met_rev_num;
3875 /*Temp, Use xa_alloc instead */
3876 resp.dev_id = rdev->en_dev->pdev->devfn;
3877 resp.max_qp = rdev->qplib_ctx.qpc_count;
3878 resp.pg_size = PAGE_SIZE;
3879 resp.cqe_sz = sizeof(struct cq_base);
3880 resp.max_cqd = dev_attr->max_cq_wqes;
3882 resp.comp_mask |= BNXT_RE_UCNTX_CMASK_HAVE_MODE;
3883 resp.mode = rdev->chip_ctx->modes.wqe_mode;
3885 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
3887 ibdev_err(ibdev, "Failed to copy user context");
3894 free_page((unsigned long)uctx->shpg);
3900 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
3902 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3903 struct bnxt_re_ucontext,
3906 struct bnxt_re_dev *rdev = uctx->rdev;
3909 free_page((unsigned long)uctx->shpg);
3911 if (uctx->dpi.dbr) {
3912 /* Free DPI only if this is the first PD allocated by the
3913 * application and mark the context dpi as NULL
3915 bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
3916 &rdev->qplib_res.dpi_tbl, &uctx->dpi);
3917 uctx->dpi.dbr = NULL;
3921 /* Helper function to mmap the virtual memory from user app */
3922 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
3924 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3925 struct bnxt_re_ucontext,
3927 struct bnxt_re_dev *rdev = uctx->rdev;
3930 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3933 if (vma->vm_pgoff) {
3934 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3935 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
3936 PAGE_SIZE, vma->vm_page_prot)) {
3937 ibdev_err(&rdev->ibdev, "Failed to map DPI");
3941 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT;
3942 if (remap_pfn_range(vma, vma->vm_start,
3943 pfn, PAGE_SIZE, vma->vm_page_prot)) {
3944 ibdev_err(&rdev->ibdev, "Failed to map shared page");