2 * Copyright (C) STMicroelectronics 2016
4 * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
6 * License terms: GNU General Public License (GPL), version 2
9 #include <linux/iio/iio.h>
10 #include <linux/iio/sysfs.h>
11 #include <linux/iio/timer/stm32-timer-trigger.h>
12 #include <linux/iio/trigger.h>
13 #include <linux/mfd/stm32-timers.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/of_device.h>
18 #define MAX_TRIGGERS 7
21 /* List the triggers created by each timer */
22 static const void *triggers_table[][MAX_TRIGGERS] = {
23 { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
24 { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
25 { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
26 { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
27 { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
30 { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
31 { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
34 { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
42 /* List the triggers accepted by each timer */
43 static const void *valids_table[][MAX_VALIDS] = {
44 { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
45 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
46 { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,},
47 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
48 { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
51 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
52 { TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,},
55 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
58 static const void *stm32h7_valids_table[][MAX_VALIDS] = {
59 { TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
60 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
61 { TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,},
62 { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
63 { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
66 { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
70 { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
73 { TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,},
78 struct stm32_timer_trigger {
80 struct regmap *regmap;
88 struct stm32_timer_trigger_cfg {
89 const void *(*valids_table)[MAX_VALIDS];
90 const unsigned int num_valids_table;
93 static bool stm32_timer_is_trgo2_name(const char *name)
95 return !!strstr(name, "trgo2");
98 static bool stm32_timer_is_trgo_name(const char *name)
100 return (!!strstr(name, "trgo") && !strstr(name, "trgo2"));
103 static int stm32_timer_start(struct stm32_timer_trigger *priv,
104 struct iio_trigger *trig,
105 unsigned int frequency)
107 unsigned long long prd, div;
111 /* Period and prescaler values depends of clock rate */
112 div = (unsigned long long)clk_get_rate(priv->clk);
114 do_div(div, frequency);
119 * Increase prescaler value until we get a result that fit
120 * with auto reload register maximum value.
122 while (div > priv->max_arr) {
125 do_div(div, (prescaler + 1));
129 if (prescaler > MAX_TIM_PSC) {
130 dev_err(priv->dev, "prescaler exceeds the maximum value\n");
134 /* Check if nobody else use the timer */
135 regmap_read(priv->regmap, TIM_CCER, &ccer);
136 if (ccer & TIM_CCER_CCXE)
139 regmap_read(priv->regmap, TIM_CR1, &cr1);
140 if (!(cr1 & TIM_CR1_CEN))
141 clk_enable(priv->clk);
143 regmap_write(priv->regmap, TIM_PSC, prescaler);
144 regmap_write(priv->regmap, TIM_ARR, prd - 1);
145 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
147 /* Force master mode to update mode */
148 if (stm32_timer_is_trgo2_name(trig->name))
149 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
150 0x2 << TIM_CR2_MMS2_SHIFT);
152 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
153 0x2 << TIM_CR2_MMS_SHIFT);
155 /* Make sure that registers are updated */
156 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
158 /* Enable controller */
159 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
164 static void stm32_timer_stop(struct stm32_timer_trigger *priv)
168 regmap_read(priv->regmap, TIM_CCER, &ccer);
169 if (ccer & TIM_CCER_CCXE)
172 regmap_read(priv->regmap, TIM_CR1, &cr1);
173 if (cr1 & TIM_CR1_CEN)
174 clk_disable(priv->clk);
177 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
178 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
179 regmap_write(priv->regmap, TIM_PSC, 0);
180 regmap_write(priv->regmap, TIM_ARR, 0);
182 /* Make sure that registers are updated */
183 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
186 static ssize_t stm32_tt_store_frequency(struct device *dev,
187 struct device_attribute *attr,
188 const char *buf, size_t len)
190 struct iio_trigger *trig = to_iio_trigger(dev);
191 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
195 ret = kstrtouint(buf, 10, &freq);
200 stm32_timer_stop(priv);
202 ret = stm32_timer_start(priv, trig, freq);
210 static ssize_t stm32_tt_read_frequency(struct device *dev,
211 struct device_attribute *attr, char *buf)
213 struct iio_trigger *trig = to_iio_trigger(dev);
214 struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
216 unsigned long long freq = 0;
218 regmap_read(priv->regmap, TIM_CR1, &cr1);
219 regmap_read(priv->regmap, TIM_PSC, &psc);
220 regmap_read(priv->regmap, TIM_ARR, &arr);
222 if (cr1 & TIM_CR1_CEN) {
223 freq = (unsigned long long)clk_get_rate(priv->clk);
224 do_div(freq, psc + 1);
225 do_div(freq, arr + 1);
228 return sprintf(buf, "%d\n", (unsigned int)freq);
231 static IIO_DEV_ATTR_SAMP_FREQ(0660,
232 stm32_tt_read_frequency,
233 stm32_tt_store_frequency);
235 #define MASTER_MODE_MAX 7
236 #define MASTER_MODE2_MAX 15
238 static char *master_mode_table[] = {
247 /* Master mode selection 2 only */
250 "compare_pulse_OC4REF",
251 "compare_pulse_OC6REF",
252 "compare_pulse_OC4REF_r_or_OC6REF_r",
253 "compare_pulse_OC4REF_r_or_OC6REF_f",
254 "compare_pulse_OC5REF_r_or_OC6REF_r",
255 "compare_pulse_OC5REF_r_or_OC6REF_f",
258 static ssize_t stm32_tt_show_master_mode(struct device *dev,
259 struct device_attribute *attr,
262 struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
263 struct iio_trigger *trig = to_iio_trigger(dev);
266 regmap_read(priv->regmap, TIM_CR2, &cr2);
268 if (stm32_timer_is_trgo2_name(trig->name))
269 cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
271 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
273 return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
276 static ssize_t stm32_tt_store_master_mode(struct device *dev,
277 struct device_attribute *attr,
278 const char *buf, size_t len)
280 struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
281 struct iio_trigger *trig = to_iio_trigger(dev);
282 u32 mask, shift, master_mode_max;
285 if (stm32_timer_is_trgo2_name(trig->name)) {
287 shift = TIM_CR2_MMS2_SHIFT;
288 master_mode_max = MASTER_MODE2_MAX;
291 shift = TIM_CR2_MMS_SHIFT;
292 master_mode_max = MASTER_MODE_MAX;
295 for (i = 0; i <= master_mode_max; i++) {
296 if (!strncmp(master_mode_table[i], buf,
297 strlen(master_mode_table[i]))) {
298 regmap_update_bits(priv->regmap, TIM_CR2, mask,
300 /* Make sure that registers are updated */
301 regmap_update_bits(priv->regmap, TIM_EGR,
302 TIM_EGR_UG, TIM_EGR_UG);
310 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
311 struct device_attribute *attr,
314 struct iio_trigger *trig = to_iio_trigger(dev);
315 unsigned int i, master_mode_max;
318 if (stm32_timer_is_trgo2_name(trig->name))
319 master_mode_max = MASTER_MODE2_MAX;
321 master_mode_max = MASTER_MODE_MAX;
323 for (i = 0; i <= master_mode_max; i++)
324 len += scnprintf(buf + len, PAGE_SIZE - len,
325 "%s ", master_mode_table[i]);
327 /* replace trailing space by newline */
333 static IIO_DEVICE_ATTR(master_mode_available, 0444,
334 stm32_tt_show_master_mode_avail, NULL, 0);
336 static IIO_DEVICE_ATTR(master_mode, 0660,
337 stm32_tt_show_master_mode,
338 stm32_tt_store_master_mode,
341 static struct attribute *stm32_trigger_attrs[] = {
342 &iio_dev_attr_sampling_frequency.dev_attr.attr,
343 &iio_dev_attr_master_mode.dev_attr.attr,
344 &iio_dev_attr_master_mode_available.dev_attr.attr,
348 static const struct attribute_group stm32_trigger_attr_group = {
349 .attrs = stm32_trigger_attrs,
352 static const struct attribute_group *stm32_trigger_attr_groups[] = {
353 &stm32_trigger_attr_group,
357 static const struct iio_trigger_ops timer_trigger_ops = {
358 .owner = THIS_MODULE,
361 static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
364 const char * const *cur = priv->triggers;
366 while (cur && *cur) {
367 struct iio_trigger *trig;
368 bool cur_is_trgo = stm32_timer_is_trgo_name(*cur);
369 bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
371 if (cur_is_trgo2 && !priv->has_trgo2) {
376 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
380 trig->dev.parent = priv->dev->parent;
381 trig->ops = &timer_trigger_ops;
384 * sampling frequency and master mode attributes
385 * should only be available on trgo/trgo2 triggers
387 if (cur_is_trgo || cur_is_trgo2)
388 trig->dev.groups = stm32_trigger_attr_groups;
390 iio_trigger_set_drvdata(trig, priv);
392 ret = devm_iio_trigger_register(priv->dev, trig);
401 static int stm32_counter_read_raw(struct iio_dev *indio_dev,
402 struct iio_chan_spec const *chan,
403 int *val, int *val2, long mask)
405 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
409 case IIO_CHAN_INFO_RAW:
410 regmap_read(priv->regmap, TIM_CNT, &dat);
414 case IIO_CHAN_INFO_ENABLE:
415 regmap_read(priv->regmap, TIM_CR1, &dat);
416 *val = (dat & TIM_CR1_CEN) ? 1 : 0;
419 case IIO_CHAN_INFO_SCALE:
420 regmap_read(priv->regmap, TIM_SMCR, &dat);
426 /* in quadrature case scale = 0.25 */
430 return IIO_VAL_FRACTIONAL_LOG2;
436 static int stm32_counter_write_raw(struct iio_dev *indio_dev,
437 struct iio_chan_spec const *chan,
438 int val, int val2, long mask)
440 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
444 case IIO_CHAN_INFO_RAW:
445 return regmap_write(priv->regmap, TIM_CNT, val);
447 case IIO_CHAN_INFO_SCALE:
451 case IIO_CHAN_INFO_ENABLE:
453 regmap_read(priv->regmap, TIM_CR1, &dat);
454 if (!(dat & TIM_CR1_CEN))
455 clk_enable(priv->clk);
456 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
459 regmap_read(priv->regmap, TIM_CR1, &dat);
460 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
462 if (dat & TIM_CR1_CEN)
463 clk_disable(priv->clk);
471 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev,
472 struct iio_trigger *trig)
474 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
475 const char * const *cur = priv->valids;
478 if (!is_stm32_timer_trigger(trig))
481 while (cur && *cur) {
482 if (!strncmp(trig->name, *cur, strlen(trig->name))) {
483 regmap_update_bits(priv->regmap,
484 TIM_SMCR, TIM_SMCR_TS,
485 i << TIM_SMCR_TS_SHIFT);
495 static const struct iio_info stm32_trigger_info = {
496 .driver_module = THIS_MODULE,
497 .validate_trigger = stm32_counter_validate_trigger,
498 .read_raw = stm32_counter_read_raw,
499 .write_raw = stm32_counter_write_raw
502 static const char *const stm32_trigger_modes[] = {
506 static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
507 const struct iio_chan_spec *chan,
510 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
512 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
517 static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
518 const struct iio_chan_spec *chan)
520 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
523 regmap_read(priv->regmap, TIM_SMCR, &smcr);
525 return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;
528 static const struct iio_enum stm32_trigger_mode_enum = {
529 .items = stm32_trigger_modes,
530 .num_items = ARRAY_SIZE(stm32_trigger_modes),
531 .set = stm32_set_trigger_mode,
532 .get = stm32_get_trigger_mode
535 static const char *const stm32_enable_modes[] = {
541 static int stm32_enable_mode2sms(int mode)
555 static int stm32_set_enable_mode(struct iio_dev *indio_dev,
556 const struct iio_chan_spec *chan,
559 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
560 int sms = stm32_enable_mode2sms(mode);
566 * Triggered mode sets CEN bit automatically by hardware. So, first
567 * enable counter clock, so it can use it. Keeps it in sync with CEN.
570 regmap_read(priv->regmap, TIM_CR1, &val);
571 if (!(val & TIM_CR1_CEN))
572 clk_enable(priv->clk);
575 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
580 static int stm32_sms2enable_mode(int mode)
594 static int stm32_get_enable_mode(struct iio_dev *indio_dev,
595 const struct iio_chan_spec *chan)
597 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
600 regmap_read(priv->regmap, TIM_SMCR, &smcr);
601 smcr &= TIM_SMCR_SMS;
603 return stm32_sms2enable_mode(smcr);
606 static const struct iio_enum stm32_enable_mode_enum = {
607 .items = stm32_enable_modes,
608 .num_items = ARRAY_SIZE(stm32_enable_modes),
609 .set = stm32_set_enable_mode,
610 .get = stm32_get_enable_mode
613 static const char *const stm32_quadrature_modes[] = {
619 static int stm32_set_quadrature_mode(struct iio_dev *indio_dev,
620 const struct iio_chan_spec *chan,
623 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
625 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, mode + 1);
630 static int stm32_get_quadrature_mode(struct iio_dev *indio_dev,
631 const struct iio_chan_spec *chan)
633 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
637 regmap_read(priv->regmap, TIM_SMCR, &smcr);
638 mode = (smcr & TIM_SMCR_SMS) - 1;
639 if ((mode < 0) || (mode > ARRAY_SIZE(stm32_quadrature_modes)))
645 static const struct iio_enum stm32_quadrature_mode_enum = {
646 .items = stm32_quadrature_modes,
647 .num_items = ARRAY_SIZE(stm32_quadrature_modes),
648 .set = stm32_set_quadrature_mode,
649 .get = stm32_get_quadrature_mode
652 static const char *const stm32_count_direction_states[] = {
657 static int stm32_set_count_direction(struct iio_dev *indio_dev,
658 const struct iio_chan_spec *chan,
661 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
665 /* In encoder mode, direction is RO (given by TI1/TI2 signals) */
666 regmap_read(priv->regmap, TIM_SMCR, &val);
667 mode = (val & TIM_SMCR_SMS) - 1;
668 if ((mode >= 0) || (mode < ARRAY_SIZE(stm32_quadrature_modes)))
671 return regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_DIR,
672 dir ? TIM_CR1_DIR : 0);
675 static int stm32_get_count_direction(struct iio_dev *indio_dev,
676 const struct iio_chan_spec *chan)
678 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
681 regmap_read(priv->regmap, TIM_CR1, &cr1);
683 return ((cr1 & TIM_CR1_DIR) ? 1 : 0);
686 static const struct iio_enum stm32_count_direction_enum = {
687 .items = stm32_count_direction_states,
688 .num_items = ARRAY_SIZE(stm32_count_direction_states),
689 .set = stm32_set_count_direction,
690 .get = stm32_get_count_direction
693 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev,
695 const struct iio_chan_spec *chan,
698 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
701 regmap_read(priv->regmap, TIM_ARR, &arr);
703 return snprintf(buf, PAGE_SIZE, "%u\n", arr);
706 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
708 const struct iio_chan_spec *chan,
709 const char *buf, size_t len)
711 struct stm32_timer_trigger *priv = iio_priv(indio_dev);
715 ret = kstrtouint(buf, 0, &preset);
719 /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
720 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
721 regmap_write(priv->regmap, TIM_ARR, preset);
726 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
729 .shared = IIO_SEPARATE,
730 .read = stm32_count_get_preset,
731 .write = stm32_count_set_preset
733 IIO_ENUM("count_direction", IIO_SEPARATE, &stm32_count_direction_enum),
734 IIO_ENUM_AVAILABLE("count_direction", &stm32_count_direction_enum),
735 IIO_ENUM("quadrature_mode", IIO_SEPARATE, &stm32_quadrature_mode_enum),
736 IIO_ENUM_AVAILABLE("quadrature_mode", &stm32_quadrature_mode_enum),
737 IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum),
738 IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum),
739 IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum),
740 IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum),
744 static const struct iio_chan_spec stm32_trigger_channel = {
747 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
748 BIT(IIO_CHAN_INFO_ENABLE) |
749 BIT(IIO_CHAN_INFO_SCALE),
750 .ext_info = stm32_trigger_count_info,
754 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev)
756 struct iio_dev *indio_dev;
759 indio_dev = devm_iio_device_alloc(dev,
760 sizeof(struct stm32_timer_trigger));
764 indio_dev->name = dev_name(dev);
765 indio_dev->dev.parent = dev;
766 indio_dev->info = &stm32_trigger_info;
767 indio_dev->modes = INDIO_HARDWARE_TRIGGERED;
768 indio_dev->num_channels = 1;
769 indio_dev->channels = &stm32_trigger_channel;
770 indio_dev->dev.of_node = dev->of_node;
772 ret = devm_iio_device_register(dev, indio_dev);
776 return iio_priv(indio_dev);
780 * is_stm32_timer_trigger
781 * @trig: trigger to be checked
783 * return true if the trigger is a valid stm32 iio timer trigger
784 * either return false
786 bool is_stm32_timer_trigger(struct iio_trigger *trig)
788 return (trig->ops == &timer_trigger_ops);
790 EXPORT_SYMBOL(is_stm32_timer_trigger);
792 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
797 * Master mode selection 2 bits can only be written and read back when
800 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
801 regmap_read(priv->regmap, TIM_CR2, &val);
802 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
803 priv->has_trgo2 = !!val;
806 static int stm32_timer_trigger_probe(struct platform_device *pdev)
808 struct device *dev = &pdev->dev;
809 struct stm32_timer_trigger *priv;
810 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
811 const struct stm32_timer_trigger_cfg *cfg;
815 if (of_property_read_u32(dev->of_node, "reg", &index))
818 cfg = (const struct stm32_timer_trigger_cfg *)
819 of_match_device(dev->driver->of_match_table, dev)->data;
821 if (index >= ARRAY_SIZE(triggers_table) ||
822 index >= cfg->num_valids_table)
825 /* Create an IIO device only if we have triggers to be validated */
826 if (*cfg->valids_table[index])
827 priv = stm32_setup_counter_device(dev);
829 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
835 priv->regmap = ddata->regmap;
836 priv->clk = ddata->clk;
837 priv->max_arr = ddata->max_arr;
838 priv->triggers = triggers_table[index];
839 priv->valids = cfg->valids_table[index];
840 stm32_timer_detect_trgo2(priv);
842 ret = stm32_setup_iio_triggers(priv);
846 platform_set_drvdata(pdev, priv);
851 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = {
852 .valids_table = valids_table,
853 .num_valids_table = ARRAY_SIZE(valids_table),
856 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = {
857 .valids_table = stm32h7_valids_table,
858 .num_valids_table = ARRAY_SIZE(stm32h7_valids_table),
861 static const struct of_device_id stm32_trig_of_match[] = {
863 .compatible = "st,stm32-timer-trigger",
864 .data = (void *)&stm32_timer_trg_cfg,
866 .compatible = "st,stm32h7-timer-trigger",
867 .data = (void *)&stm32h7_timer_trg_cfg,
871 MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
873 static struct platform_driver stm32_timer_trigger_driver = {
874 .probe = stm32_timer_trigger_probe,
876 .name = "stm32-timer-trigger",
877 .of_match_table = stm32_trig_of_match,
880 module_platform_driver(stm32_timer_trigger_driver);
882 MODULE_ALIAS("platform: stm32-timer-trigger");
883 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
884 MODULE_LICENSE("GPL v2");