2 * Copyright (C) 2012 Invensense, Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/i2c.h>
17 #include <linux/err.h>
18 #include <linux/delay.h>
19 #include <linux/sysfs.h>
20 #include <linux/jiffies.h>
21 #include <linux/irq.h>
22 #include <linux/interrupt.h>
23 #include <linux/iio/iio.h>
24 #include <linux/acpi.h>
25 #include <linux/platform_device.h>
26 #include <linux/regulator/consumer.h>
27 #include "inv_mpu_iio.h"
30 * this is the gyro scale translated from dynamic range plus/minus
31 * {250, 500, 1000, 2000} to rad/s
33 static const int gyro_scale_6050[] = {133090, 266181, 532362, 1064724};
36 * this is the accel scale translated from dynamic range plus/minus
37 * {2, 4, 8, 16} to m/s^2
39 static const int accel_scale[] = {598, 1196, 2392, 4785};
41 static const struct inv_mpu6050_reg_map reg_set_icm20602 = {
42 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
43 .lpf = INV_MPU6050_REG_CONFIG,
44 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
45 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
46 .fifo_en = INV_MPU6050_REG_FIFO_EN,
47 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
48 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
49 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
50 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
51 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
52 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
53 .temperature = INV_MPU6050_REG_TEMPERATURE,
54 .int_enable = INV_MPU6050_REG_INT_ENABLE,
55 .int_status = INV_MPU6050_REG_INT_STATUS,
56 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
57 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
58 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
59 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
60 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
61 .i2c_if = INV_ICM20602_REG_I2C_IF,
64 static const struct inv_mpu6050_reg_map reg_set_6500 = {
65 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
66 .lpf = INV_MPU6050_REG_CONFIG,
67 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
68 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
69 .fifo_en = INV_MPU6050_REG_FIFO_EN,
70 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
71 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
72 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
73 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
74 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
75 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
76 .temperature = INV_MPU6050_REG_TEMPERATURE,
77 .int_enable = INV_MPU6050_REG_INT_ENABLE,
78 .int_status = INV_MPU6050_REG_INT_STATUS,
79 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
80 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
81 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
82 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
83 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
87 static const struct inv_mpu6050_reg_map reg_set_6050 = {
88 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
89 .lpf = INV_MPU6050_REG_CONFIG,
90 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
91 .fifo_en = INV_MPU6050_REG_FIFO_EN,
92 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
93 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
94 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
95 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
96 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
97 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
98 .temperature = INV_MPU6050_REG_TEMPERATURE,
99 .int_enable = INV_MPU6050_REG_INT_ENABLE,
100 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
101 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
102 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
103 .accl_offset = INV_MPU6050_REG_ACCEL_OFFSET,
104 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
108 static const struct inv_mpu6050_chip_config chip_config_6050 = {
109 .fsr = INV_MPU6050_FSR_2000DPS,
110 .lpf = INV_MPU6050_FILTER_20HZ,
111 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(INV_MPU6050_INIT_FIFO_RATE),
112 .gyro_fifo_enable = false,
113 .accl_fifo_enable = false,
114 .accl_fs = INV_MPU6050_FS_02G,
118 /* Indexed by enum inv_devices */
119 static const struct inv_mpu6050_hw hw_info[] = {
121 .whoami = INV_MPU6050_WHOAMI_VALUE,
123 .reg = ®_set_6050,
124 .config = &chip_config_6050,
127 .whoami = INV_MPU6500_WHOAMI_VALUE,
129 .reg = ®_set_6500,
130 .config = &chip_config_6050,
133 .whoami = INV_MPU6515_WHOAMI_VALUE,
135 .reg = ®_set_6500,
136 .config = &chip_config_6050,
139 .whoami = INV_MPU6000_WHOAMI_VALUE,
141 .reg = ®_set_6050,
142 .config = &chip_config_6050,
145 .whoami = INV_MPU9150_WHOAMI_VALUE,
147 .reg = ®_set_6050,
148 .config = &chip_config_6050,
151 .whoami = INV_MPU9250_WHOAMI_VALUE,
153 .reg = ®_set_6500,
154 .config = &chip_config_6050,
157 .whoami = INV_MPU9255_WHOAMI_VALUE,
159 .reg = ®_set_6500,
160 .config = &chip_config_6050,
163 .whoami = INV_ICM20608_WHOAMI_VALUE,
165 .reg = ®_set_6500,
166 .config = &chip_config_6050,
169 .whoami = INV_ICM20602_WHOAMI_VALUE,
171 .reg = ®_set_icm20602,
172 .config = &chip_config_6050,
176 int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask)
178 unsigned int d, mgmt_1;
181 * switch clock needs to be careful. Only when gyro is on, can
182 * clock source be switched to gyro. Otherwise, it must be set to
185 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
186 result = regmap_read(st->map, st->reg->pwr_mgmt_1, &mgmt_1);
190 mgmt_1 &= ~INV_MPU6050_BIT_CLK_MASK;
193 if ((mask == INV_MPU6050_BIT_PWR_GYRO_STBY) && (!en)) {
195 * turning off gyro requires switch to internal clock first.
196 * Then turn off gyro engine
198 mgmt_1 |= INV_CLK_INTERNAL;
199 result = regmap_write(st->map, st->reg->pwr_mgmt_1, mgmt_1);
204 result = regmap_read(st->map, st->reg->pwr_mgmt_2, &d);
211 result = regmap_write(st->map, st->reg->pwr_mgmt_2, d);
216 /* Wait for output to stabilize */
217 msleep(INV_MPU6050_TEMP_UP_TIME);
218 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
219 /* switch internal clock to PLL */
220 mgmt_1 |= INV_CLK_PLL;
221 result = regmap_write(st->map,
222 st->reg->pwr_mgmt_1, mgmt_1);
231 int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on)
236 if (!st->powerup_count) {
237 result = regmap_write(st->map, st->reg->pwr_mgmt_1, 0);
240 usleep_range(INV_MPU6050_REG_UP_TIME_MIN,
241 INV_MPU6050_REG_UP_TIME_MAX);
245 if (st->powerup_count == 1) {
246 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
247 INV_MPU6050_BIT_SLEEP);
254 dev_dbg(regmap_get_device(st->map), "set power %d, count=%u\n",
255 power_on, st->powerup_count);
259 EXPORT_SYMBOL_GPL(inv_mpu6050_set_power_itg);
262 * inv_mpu6050_set_lpf_regs() - set low pass filter registers, chip dependent
264 * MPU60xx/MPU9150 use only 1 register for accelerometer + gyroscope
265 * MPU6500 and above have a dedicated register for accelerometer
267 static int inv_mpu6050_set_lpf_regs(struct inv_mpu6050_state *st,
268 enum inv_mpu6050_filter_e val)
272 result = regmap_write(st->map, st->reg->lpf, val);
276 switch (st->chip_type) {
280 /* old chips, nothing to do */
285 result = regmap_write(st->map, st->reg->accel_lpf, val);
293 * inv_mpu6050_init_config() - Initialize hardware, disable FIFO.
295 * Initial configuration:
299 * Clock source: Gyro PLL
301 static int inv_mpu6050_init_config(struct iio_dev *indio_dev)
305 struct inv_mpu6050_state *st = iio_priv(indio_dev);
307 result = inv_mpu6050_set_power_itg(st, true);
310 d = (INV_MPU6050_FSR_2000DPS << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
311 result = regmap_write(st->map, st->reg->gyro_config, d);
313 goto error_power_off;
315 result = inv_mpu6050_set_lpf_regs(st, INV_MPU6050_FILTER_20HZ);
317 goto error_power_off;
319 d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(INV_MPU6050_INIT_FIFO_RATE);
320 result = regmap_write(st->map, st->reg->sample_rate_div, d);
322 goto error_power_off;
324 d = (INV_MPU6050_FS_02G << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
325 result = regmap_write(st->map, st->reg->accl_config, d);
327 goto error_power_off;
329 result = regmap_write(st->map, st->reg->int_pin_cfg, st->irq_mask);
333 memcpy(&st->chip_config, hw_info[st->chip_type].config,
334 sizeof(struct inv_mpu6050_chip_config));
337 * Internal chip period is 1ms (1kHz).
338 * Let's use at the beginning the theorical value before measuring
339 * with interrupt timestamps.
341 st->chip_period = NSEC_PER_MSEC;
343 return inv_mpu6050_set_power_itg(st, false);
346 inv_mpu6050_set_power_itg(st, false);
350 static int inv_mpu6050_sensor_set(struct inv_mpu6050_state *st, int reg,
354 __be16 d = cpu_to_be16(val);
356 ind = (axis - IIO_MOD_X) * 2;
357 result = regmap_bulk_write(st->map, reg + ind, (u8 *)&d, 2);
364 static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg,
370 ind = (axis - IIO_MOD_X) * 2;
371 result = regmap_bulk_read(st->map, reg + ind, (u8 *)&d, 2);
374 *val = (short)be16_to_cpup(&d);
379 static int inv_mpu6050_read_channel_data(struct iio_dev *indio_dev,
380 struct iio_chan_spec const *chan,
383 struct inv_mpu6050_state *st = iio_priv(indio_dev);
387 result = inv_mpu6050_set_power_itg(st, true);
391 switch (chan->type) {
393 result = inv_mpu6050_switch_engine(st, true,
394 INV_MPU6050_BIT_PWR_GYRO_STBY);
396 goto error_power_off;
397 ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro,
398 chan->channel2, val);
399 result = inv_mpu6050_switch_engine(st, false,
400 INV_MPU6050_BIT_PWR_GYRO_STBY);
402 goto error_power_off;
405 result = inv_mpu6050_switch_engine(st, true,
406 INV_MPU6050_BIT_PWR_ACCL_STBY);
408 goto error_power_off;
409 ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl,
410 chan->channel2, val);
411 result = inv_mpu6050_switch_engine(st, false,
412 INV_MPU6050_BIT_PWR_ACCL_STBY);
414 goto error_power_off;
417 /* wait for stablization */
418 msleep(INV_MPU6050_SENSOR_UP_TIME);
419 ret = inv_mpu6050_sensor_show(st, st->reg->temperature,
427 result = inv_mpu6050_set_power_itg(st, false);
429 goto error_power_off;
434 inv_mpu6050_set_power_itg(st, false);
439 inv_mpu6050_read_raw(struct iio_dev *indio_dev,
440 struct iio_chan_spec const *chan,
441 int *val, int *val2, long mask)
443 struct inv_mpu6050_state *st = iio_priv(indio_dev);
447 case IIO_CHAN_INFO_RAW:
448 ret = iio_device_claim_direct_mode(indio_dev);
451 mutex_lock(&st->lock);
452 ret = inv_mpu6050_read_channel_data(indio_dev, chan, val);
453 mutex_unlock(&st->lock);
454 iio_device_release_direct_mode(indio_dev);
456 case IIO_CHAN_INFO_SCALE:
457 switch (chan->type) {
459 mutex_lock(&st->lock);
461 *val2 = gyro_scale_6050[st->chip_config.fsr];
462 mutex_unlock(&st->lock);
464 return IIO_VAL_INT_PLUS_NANO;
466 mutex_lock(&st->lock);
468 *val2 = accel_scale[st->chip_config.accl_fs];
469 mutex_unlock(&st->lock);
471 return IIO_VAL_INT_PLUS_MICRO;
474 *val2 = INV_MPU6050_TEMP_SCALE;
476 return IIO_VAL_INT_PLUS_MICRO;
480 case IIO_CHAN_INFO_OFFSET:
481 switch (chan->type) {
483 *val = INV_MPU6050_TEMP_OFFSET;
489 case IIO_CHAN_INFO_CALIBBIAS:
490 switch (chan->type) {
492 mutex_lock(&st->lock);
493 ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset,
494 chan->channel2, val);
495 mutex_unlock(&st->lock);
498 mutex_lock(&st->lock);
499 ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset,
500 chan->channel2, val);
501 mutex_unlock(&st->lock);
512 static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val)
517 for (i = 0; i < ARRAY_SIZE(gyro_scale_6050); ++i) {
518 if (gyro_scale_6050[i] == val) {
519 d = (i << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
520 result = regmap_write(st->map, st->reg->gyro_config, d);
524 st->chip_config.fsr = i;
532 static int inv_write_raw_get_fmt(struct iio_dev *indio_dev,
533 struct iio_chan_spec const *chan, long mask)
536 case IIO_CHAN_INFO_SCALE:
537 switch (chan->type) {
539 return IIO_VAL_INT_PLUS_NANO;
541 return IIO_VAL_INT_PLUS_MICRO;
544 return IIO_VAL_INT_PLUS_MICRO;
550 static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val)
555 for (i = 0; i < ARRAY_SIZE(accel_scale); ++i) {
556 if (accel_scale[i] == val) {
557 d = (i << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
558 result = regmap_write(st->map, st->reg->accl_config, d);
562 st->chip_config.accl_fs = i;
570 static int inv_mpu6050_write_raw(struct iio_dev *indio_dev,
571 struct iio_chan_spec const *chan,
572 int val, int val2, long mask)
574 struct inv_mpu6050_state *st = iio_priv(indio_dev);
578 * we should only update scale when the chip is disabled, i.e.
581 result = iio_device_claim_direct_mode(indio_dev);
585 mutex_lock(&st->lock);
586 result = inv_mpu6050_set_power_itg(st, true);
588 goto error_write_raw_unlock;
591 case IIO_CHAN_INFO_SCALE:
592 switch (chan->type) {
594 result = inv_mpu6050_write_gyro_scale(st, val2);
597 result = inv_mpu6050_write_accel_scale(st, val2);
604 case IIO_CHAN_INFO_CALIBBIAS:
605 switch (chan->type) {
607 result = inv_mpu6050_sensor_set(st,
608 st->reg->gyro_offset,
609 chan->channel2, val);
612 result = inv_mpu6050_sensor_set(st,
613 st->reg->accl_offset,
614 chan->channel2, val);
626 result |= inv_mpu6050_set_power_itg(st, false);
627 error_write_raw_unlock:
628 mutex_unlock(&st->lock);
629 iio_device_release_direct_mode(indio_dev);
635 * inv_mpu6050_set_lpf() - set low pass filer based on fifo rate.
637 * Based on the Nyquist principle, the sampling rate must
638 * exceed twice of the bandwidth of the signal, or there
639 * would be alising. This function basically search for the
640 * correct low pass parameters based on the fifo rate, e.g,
641 * sampling frequency.
643 * lpf is set automatically when setting sampling rate to avoid any aliases.
645 static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
647 static const int hz[] = {188, 98, 42, 20, 10, 5};
648 static const int d[] = {
649 INV_MPU6050_FILTER_188HZ, INV_MPU6050_FILTER_98HZ,
650 INV_MPU6050_FILTER_42HZ, INV_MPU6050_FILTER_20HZ,
651 INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ
658 while ((h < hz[i]) && (i < ARRAY_SIZE(d) - 1))
661 result = inv_mpu6050_set_lpf_regs(st, data);
664 st->chip_config.lpf = data;
670 * inv_mpu6050_fifo_rate_store() - Set fifo rate.
673 inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr,
674 const char *buf, size_t count)
679 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
680 struct inv_mpu6050_state *st = iio_priv(indio_dev);
682 if (kstrtoint(buf, 10, &fifo_rate))
684 if (fifo_rate < INV_MPU6050_MIN_FIFO_RATE ||
685 fifo_rate > INV_MPU6050_MAX_FIFO_RATE)
688 result = iio_device_claim_direct_mode(indio_dev);
692 /* compute the chip sample rate divider */
693 d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate);
694 /* compute back the fifo rate to handle truncation cases */
695 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(d);
697 mutex_lock(&st->lock);
698 if (d == st->chip_config.divider) {
700 goto fifo_rate_fail_unlock;
702 result = inv_mpu6050_set_power_itg(st, true);
704 goto fifo_rate_fail_unlock;
706 result = regmap_write(st->map, st->reg->sample_rate_div, d);
708 goto fifo_rate_fail_power_off;
709 st->chip_config.divider = d;
711 result = inv_mpu6050_set_lpf(st, fifo_rate);
713 goto fifo_rate_fail_power_off;
715 fifo_rate_fail_power_off:
716 result |= inv_mpu6050_set_power_itg(st, false);
717 fifo_rate_fail_unlock:
718 mutex_unlock(&st->lock);
719 iio_device_release_direct_mode(indio_dev);
727 * inv_fifo_rate_show() - Get the current sampling rate.
730 inv_fifo_rate_show(struct device *dev, struct device_attribute *attr,
733 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
736 mutex_lock(&st->lock);
737 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
738 mutex_unlock(&st->lock);
740 return scnprintf(buf, PAGE_SIZE, "%u\n", fifo_rate);
744 * inv_attr_show() - calling this function will show current
747 * Deprecated in favor of IIO mounting matrix API.
749 * See inv_get_mount_matrix()
751 static ssize_t inv_attr_show(struct device *dev, struct device_attribute *attr,
754 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
755 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
758 switch (this_attr->address) {
760 * In MPU6050, the two matrix are the same because gyro and accel
761 * are integrated in one chip
763 case ATTR_GYRO_MATRIX:
764 case ATTR_ACCL_MATRIX:
765 m = st->plat_data.orientation;
767 return scnprintf(buf, PAGE_SIZE,
768 "%d, %d, %d; %d, %d, %d; %d, %d, %d\n",
769 m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]);
776 * inv_mpu6050_validate_trigger() - validate_trigger callback for invensense
778 * @indio_dev: The IIO device
779 * @trig: The new trigger
781 * Returns: 0 if the 'trig' matches the trigger registered by the MPU6050
782 * device, -EINVAL otherwise.
784 static int inv_mpu6050_validate_trigger(struct iio_dev *indio_dev,
785 struct iio_trigger *trig)
787 struct inv_mpu6050_state *st = iio_priv(indio_dev);
789 if (st->trig != trig)
795 static const struct iio_mount_matrix *
796 inv_get_mount_matrix(const struct iio_dev *indio_dev,
797 const struct iio_chan_spec *chan)
799 struct inv_mpu6050_state *data = iio_priv(indio_dev);
801 return &data->orientation;
804 static const struct iio_chan_spec_ext_info inv_ext_info[] = {
805 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, inv_get_mount_matrix),
809 #define INV_MPU6050_CHAN(_type, _channel2, _index) \
813 .channel2 = _channel2, \
814 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
815 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
816 BIT(IIO_CHAN_INFO_CALIBBIAS), \
817 .scan_index = _index, \
823 .endianness = IIO_BE, \
825 .ext_info = inv_ext_info, \
828 static const struct iio_chan_spec inv_mpu_channels[] = {
829 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
831 * Note that temperature should only be via polled reading only,
832 * not the final scan elements output.
836 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)
837 | BIT(IIO_CHAN_INFO_OFFSET)
838 | BIT(IIO_CHAN_INFO_SCALE),
841 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
842 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
843 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
845 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
846 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
847 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
851 * The user can choose any frequency between INV_MPU6050_MIN_FIFO_RATE and
852 * INV_MPU6050_MAX_FIFO_RATE, but only these frequencies are matched by the
853 * low-pass filter. Specifically, each of these sampling rates are about twice
854 * the bandwidth of a corresponding low-pass filter, which should eliminate
855 * aliasing following the Nyquist principle. By picking a frequency different
856 * from these, the user risks aliasing effects.
858 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 20 50 100 200 500");
859 static IIO_CONST_ATTR(in_anglvel_scale_available,
860 "0.000133090 0.000266181 0.000532362 0.001064724");
861 static IIO_CONST_ATTR(in_accel_scale_available,
862 "0.000598 0.001196 0.002392 0.004785");
863 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, inv_fifo_rate_show,
864 inv_mpu6050_fifo_rate_store);
866 /* Deprecated: kept for userspace backward compatibility. */
867 static IIO_DEVICE_ATTR(in_gyro_matrix, S_IRUGO, inv_attr_show, NULL,
869 static IIO_DEVICE_ATTR(in_accel_matrix, S_IRUGO, inv_attr_show, NULL,
872 static struct attribute *inv_attributes[] = {
873 &iio_dev_attr_in_gyro_matrix.dev_attr.attr, /* deprecated */
874 &iio_dev_attr_in_accel_matrix.dev_attr.attr, /* deprecated */
875 &iio_dev_attr_sampling_frequency.dev_attr.attr,
876 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
877 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
878 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
882 static const struct attribute_group inv_attribute_group = {
883 .attrs = inv_attributes
886 static const struct iio_info mpu_info = {
887 .read_raw = &inv_mpu6050_read_raw,
888 .write_raw = &inv_mpu6050_write_raw,
889 .write_raw_get_fmt = &inv_write_raw_get_fmt,
890 .attrs = &inv_attribute_group,
891 .validate_trigger = inv_mpu6050_validate_trigger,
895 * inv_check_and_setup_chip() - check and setup chip.
897 static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
903 st->hw = &hw_info[st->chip_type];
904 st->reg = hw_info[st->chip_type].reg;
906 /* check chip self-identification */
907 result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val);
910 if (regval != st->hw->whoami) {
911 /* check whoami against all possible values */
912 for (i = 0; i < INV_NUM_PARTS; ++i) {
913 if (regval == hw_info[i].whoami) {
914 dev_warn(regmap_get_device(st->map),
915 "whoami mismatch got %#02x (%s)"
916 "expected %#02hhx (%s)\n",
917 regval, hw_info[i].name,
918 st->hw->whoami, st->hw->name);
922 if (i >= INV_NUM_PARTS) {
923 dev_err(regmap_get_device(st->map),
924 "invalid whoami %#02x expected %#02hhx (%s)\n",
925 regval, st->hw->whoami, st->hw->name);
930 /* reset to make sure previous state are not there */
931 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
932 INV_MPU6050_BIT_H_RESET);
935 msleep(INV_MPU6050_POWER_UP_TIME);
938 * Turn power on. After reset, the sleep bit could be on
939 * or off depending on the OTP settings. Turning power on
940 * make it in a definite state as well as making the hardware
941 * state align with the software state
943 result = inv_mpu6050_set_power_itg(st, true);
947 result = inv_mpu6050_switch_engine(st, false,
948 INV_MPU6050_BIT_PWR_ACCL_STBY);
950 goto error_power_off;
951 result = inv_mpu6050_switch_engine(st, false,
952 INV_MPU6050_BIT_PWR_GYRO_STBY);
954 goto error_power_off;
956 return inv_mpu6050_set_power_itg(st, false);
959 inv_mpu6050_set_power_itg(st, false);
963 static int inv_mpu_core_enable_regulator(struct inv_mpu6050_state *st)
967 result = regulator_enable(st->vddio_supply);
969 dev_err(regmap_get_device(st->map),
970 "Failed to enable regulator: %d\n", result);
972 /* Give the device a little bit of time to start up. */
973 usleep_range(35000, 70000);
979 static int inv_mpu_core_disable_regulator(struct inv_mpu6050_state *st)
983 result = regulator_disable(st->vddio_supply);
985 dev_err(regmap_get_device(st->map),
986 "Failed to disable regulator: %d\n", result);
991 static void inv_mpu_core_disable_regulator_action(void *_data)
993 inv_mpu_core_disable_regulator(_data);
996 int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
997 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type)
999 struct inv_mpu6050_state *st;
1000 struct iio_dev *indio_dev;
1001 struct inv_mpu6050_platform_data *pdata;
1002 struct device *dev = regmap_get_device(regmap);
1004 struct irq_data *desc;
1007 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1011 BUILD_BUG_ON(ARRAY_SIZE(hw_info) != INV_NUM_PARTS);
1012 if (chip_type < 0 || chip_type >= INV_NUM_PARTS) {
1013 dev_err(dev, "Bad invensense chip_type=%d name=%s\n",
1017 st = iio_priv(indio_dev);
1018 mutex_init(&st->lock);
1019 st->chip_type = chip_type;
1020 st->powerup_count = 0;
1024 pdata = dev_get_platdata(dev);
1026 result = iio_read_mount_matrix(dev, "mount-matrix",
1029 dev_err(dev, "Failed to retrieve mounting matrix %d\n",
1034 st->plat_data = *pdata;
1037 desc = irq_get_irq_data(irq);
1039 dev_err(dev, "Could not find IRQ %d\n", irq);
1043 irq_type = irqd_get_trigger_type(desc);
1045 irq_type = IRQF_TRIGGER_RISING;
1046 if (irq_type == IRQF_TRIGGER_RISING)
1047 st->irq_mask = INV_MPU6050_ACTIVE_HIGH;
1048 else if (irq_type == IRQF_TRIGGER_FALLING)
1049 st->irq_mask = INV_MPU6050_ACTIVE_LOW;
1050 else if (irq_type == IRQF_TRIGGER_HIGH)
1051 st->irq_mask = INV_MPU6050_ACTIVE_HIGH |
1052 INV_MPU6050_LATCH_INT_EN;
1053 else if (irq_type == IRQF_TRIGGER_LOW)
1054 st->irq_mask = INV_MPU6050_ACTIVE_LOW |
1055 INV_MPU6050_LATCH_INT_EN;
1057 dev_err(dev, "Invalid interrupt type 0x%x specified\n",
1062 st->vddio_supply = devm_regulator_get(dev, "vddio");
1063 if (IS_ERR(st->vddio_supply)) {
1064 if (PTR_ERR(st->vddio_supply) != -EPROBE_DEFER)
1065 dev_err(dev, "Failed to get vddio regulator %d\n",
1066 (int)PTR_ERR(st->vddio_supply));
1068 return PTR_ERR(st->vddio_supply);
1071 result = inv_mpu_core_enable_regulator(st);
1075 result = devm_add_action(dev, inv_mpu_core_disable_regulator_action,
1078 inv_mpu_core_disable_regulator_action(st);
1079 dev_err(dev, "Failed to setup regulator cleanup action %d\n",
1084 /* power is turned on inside check chip type*/
1085 result = inv_check_and_setup_chip(st);
1089 result = inv_mpu6050_init_config(indio_dev);
1091 dev_err(dev, "Could not initialize device.\n");
1095 if (inv_mpu_bus_setup)
1096 inv_mpu_bus_setup(indio_dev);
1098 dev_set_drvdata(dev, indio_dev);
1099 indio_dev->dev.parent = dev;
1100 /* name will be NULL when enumerated via ACPI */
1102 indio_dev->name = name;
1104 indio_dev->name = dev_name(dev);
1105 indio_dev->channels = inv_mpu_channels;
1106 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
1108 indio_dev->info = &mpu_info;
1109 indio_dev->modes = INDIO_BUFFER_TRIGGERED;
1111 result = devm_iio_triggered_buffer_setup(dev, indio_dev,
1112 iio_pollfunc_store_time,
1113 inv_mpu6050_read_fifo,
1116 dev_err(dev, "configure buffer fail %d\n", result);
1119 result = inv_mpu6050_probe_trigger(indio_dev, irq_type);
1121 dev_err(dev, "trigger probe fail %d\n", result);
1125 result = devm_iio_device_register(dev, indio_dev);
1127 dev_err(dev, "IIO register fail %d\n", result);
1133 EXPORT_SYMBOL_GPL(inv_mpu_core_probe);
1135 #ifdef CONFIG_PM_SLEEP
1137 static int inv_mpu_resume(struct device *dev)
1139 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1142 mutex_lock(&st->lock);
1143 result = inv_mpu_core_enable_regulator(st);
1147 result = inv_mpu6050_set_power_itg(st, true);
1149 mutex_unlock(&st->lock);
1154 static int inv_mpu_suspend(struct device *dev)
1156 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1159 mutex_lock(&st->lock);
1160 result = inv_mpu6050_set_power_itg(st, false);
1161 inv_mpu_core_disable_regulator(st);
1162 mutex_unlock(&st->lock);
1166 #endif /* CONFIG_PM_SLEEP */
1168 SIMPLE_DEV_PM_OPS(inv_mpu_pmops, inv_mpu_suspend, inv_mpu_resume);
1169 EXPORT_SYMBOL_GPL(inv_mpu_pmops);
1171 MODULE_AUTHOR("Invensense Corporation");
1172 MODULE_DESCRIPTION("Invensense device MPU6050 driver");
1173 MODULE_LICENSE("GPL");