drivers/iio/gyro/fxas21002c_core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for NXP FXAS21002C Gyroscope - Core
   4  *
   5  * Copyright (C) 2019 Linaro Ltd.
   6  */
   7
   8 #include <linux/interrupt.h>
   9 #include <linux/module.h>
  10 #include <linux/of_irq.h>
  11 #include <linux/pm.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/regmap.h>
  14 #include <linux/regulator/consumer.h>
  15
  16 #include <linux/iio/events.h>
  17 #include <linux/iio/iio.h>
  18 #include <linux/iio/buffer.h>
  19 #include <linux/iio/sysfs.h>
  20 #include <linux/iio/trigger.h>
  21 #include <linux/iio/trigger_consumer.h>
  22 #include <linux/iio/triggered_buffer.h>
  23
  24 #include "fxas21002c.h"
  25
  26 #define FXAS21002C_CHIP_ID_1    0xD6
  27 #define FXAS21002C_CHIP_ID_2    0xD7
  28
  29 enum fxas21002c_mode_state {
  30         FXAS21002C_MODE_STANDBY,
  31         FXAS21002C_MODE_READY,
  32         FXAS21002C_MODE_ACTIVE,
  33 };
  34
  35 #define FXAS21002C_STANDBY_ACTIVE_TIME_MS       62
  36 #define FXAS21002C_READY_ACTIVE_TIME_MS         7
  37
  38 #define FXAS21002C_ODR_LIST_MAX         10
  39
  40 #define FXAS21002C_SCALE_FRACTIONAL     32
  41 #define FXAS21002C_RANGE_LIMIT_DOUBLE   2000
  42
  43 #define FXAS21002C_AXIS_TO_REG(axis) (FXAS21002C_REG_OUT_X_MSB + ((axis) * 2))
  44
  45 static const struct reg_field fxas21002c_reg_fields[] = {
  46         [F_DR_STATUS]           = REG_FIELD(FXAS21002C_REG_STATUS, 0, 7),
  47         [F_OUT_X_MSB]           = REG_FIELD(FXAS21002C_REG_OUT_X_MSB, 0, 7),
  48         [F_OUT_X_LSB]           = REG_FIELD(FXAS21002C_REG_OUT_X_LSB, 0, 7),
  49         [F_OUT_Y_MSB]           = REG_FIELD(FXAS21002C_REG_OUT_Y_MSB, 0, 7),
  50         [F_OUT_Y_LSB]           = REG_FIELD(FXAS21002C_REG_OUT_Y_LSB, 0, 7),
  51         [F_OUT_Z_MSB]           = REG_FIELD(FXAS21002C_REG_OUT_Z_MSB, 0, 7),
  52         [F_OUT_Z_LSB]           = REG_FIELD(FXAS21002C_REG_OUT_Z_LSB, 0, 7),
  53         [F_ZYX_OW]              = REG_FIELD(FXAS21002C_REG_DR_STATUS, 7, 7),
  54         [F_Z_OW]                = REG_FIELD(FXAS21002C_REG_DR_STATUS, 6, 6),
  55         [F_Y_OW]                = REG_FIELD(FXAS21002C_REG_DR_STATUS, 5, 5),
  56         [F_X_OW]                = REG_FIELD(FXAS21002C_REG_DR_STATUS, 4, 4),
  57         [F_ZYX_DR]              = REG_FIELD(FXAS21002C_REG_DR_STATUS, 3, 3),
  58         [F_Z_DR]                = REG_FIELD(FXAS21002C_REG_DR_STATUS, 2, 2),
  59         [F_Y_DR]                = REG_FIELD(FXAS21002C_REG_DR_STATUS, 1, 1),
  60         [F_X_DR]                = REG_FIELD(FXAS21002C_REG_DR_STATUS, 0, 0),
  61         [F_OVF]                 = REG_FIELD(FXAS21002C_REG_F_STATUS, 7, 7),
  62         [F_WMKF]                = REG_FIELD(FXAS21002C_REG_F_STATUS, 6, 6),
  63         [F_CNT]                 = REG_FIELD(FXAS21002C_REG_F_STATUS, 0, 5),
  64         [F_MODE]                = REG_FIELD(FXAS21002C_REG_F_SETUP, 6, 7),
  65         [F_WMRK]                = REG_FIELD(FXAS21002C_REG_F_SETUP, 0, 5),
  66         [F_EVENT]               = REG_FIELD(FXAS21002C_REG_F_EVENT, 5, 5),
  67         [FE_TIME]               = REG_FIELD(FXAS21002C_REG_F_EVENT, 0, 4),
  68         [F_BOOTEND]             = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 3, 3),
  69         [F_SRC_FIFO]            = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 2, 2),
  70         [F_SRC_RT]              = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 1, 1),
  71         [F_SRC_DRDY]            = REG_FIELD(FXAS21002C_REG_INT_SRC_FLAG, 0, 0),
  72         [F_WHO_AM_I]            = REG_FIELD(FXAS21002C_REG_WHO_AM_I, 0, 7),
  73         [F_BW]                  = REG_FIELD(FXAS21002C_REG_CTRL0, 6, 7),
  74         [F_SPIW]                = REG_FIELD(FXAS21002C_REG_CTRL0, 5, 5),
  75         [F_SEL]                 = REG_FIELD(FXAS21002C_REG_CTRL0, 3, 4),
  76         [F_HPF_EN]              = REG_FIELD(FXAS21002C_REG_CTRL0, 2, 2),
  77         [F_FS]                  = REG_FIELD(FXAS21002C_REG_CTRL0, 0, 1),
  78         [F_ELE]                 = REG_FIELD(FXAS21002C_REG_RT_CFG, 3, 3),
  79         [F_ZTEFE]               = REG_FIELD(FXAS21002C_REG_RT_CFG, 2, 2),
  80         [F_YTEFE]               = REG_FIELD(FXAS21002C_REG_RT_CFG, 1, 1),
  81         [F_XTEFE]               = REG_FIELD(FXAS21002C_REG_RT_CFG, 0, 0),
  82         [F_EA]                  = REG_FIELD(FXAS21002C_REG_RT_SRC, 6, 6),
  83         [F_ZRT]                 = REG_FIELD(FXAS21002C_REG_RT_SRC, 5, 5),
  84         [F_ZRT_POL]             = REG_FIELD(FXAS21002C_REG_RT_SRC, 4, 4),
  85         [F_YRT]                 = REG_FIELD(FXAS21002C_REG_RT_SRC, 3, 3),
  86         [F_YRT_POL]             = REG_FIELD(FXAS21002C_REG_RT_SRC, 2, 2),
  87         [F_XRT]                 = REG_FIELD(FXAS21002C_REG_RT_SRC, 1, 1),
  88         [F_XRT_POL]             = REG_FIELD(FXAS21002C_REG_RT_SRC, 0, 0),
  89         [F_DBCNTM]              = REG_FIELD(FXAS21002C_REG_RT_THS, 7, 7),
  90         [F_THS]                 = REG_FIELD(FXAS21002C_REG_RT_SRC, 0, 6),
  91         [F_RT_COUNT]            = REG_FIELD(FXAS21002C_REG_RT_COUNT, 0, 7),
  92         [F_TEMP]                = REG_FIELD(FXAS21002C_REG_TEMP, 0, 7),
  93         [F_RST]                 = REG_FIELD(FXAS21002C_REG_CTRL1, 6, 6),
  94         [F_ST]                  = REG_FIELD(FXAS21002C_REG_CTRL1, 5, 5),
  95         [F_DR]                  = REG_FIELD(FXAS21002C_REG_CTRL1, 2, 4),
  96         [F_ACTIVE]              = REG_FIELD(FXAS21002C_REG_CTRL1, 1, 1),
  97         [F_READY]               = REG_FIELD(FXAS21002C_REG_CTRL1, 0, 0),
  98         [F_INT_CFG_FIFO]        = REG_FIELD(FXAS21002C_REG_CTRL2, 7, 7),
  99         [F_INT_EN_FIFO]         = REG_FIELD(FXAS21002C_REG_CTRL2, 6, 6),
 100         [F_INT_CFG_RT]          = REG_FIELD(FXAS21002C_REG_CTRL2, 5, 5),
 101         [F_INT_EN_RT]           = REG_FIELD(FXAS21002C_REG_CTRL2, 4, 4),
 102         [F_INT_CFG_DRDY]        = REG_FIELD(FXAS21002C_REG_CTRL2, 3, 3),
 103         [F_INT_EN_DRDY]         = REG_FIELD(FXAS21002C_REG_CTRL2, 2, 2),
 104         [F_IPOL]                = REG_FIELD(FXAS21002C_REG_CTRL2, 1, 1),
 105         [F_PP_OD]               = REG_FIELD(FXAS21002C_REG_CTRL2, 0, 0),
 106         [F_WRAPTOONE]           = REG_FIELD(FXAS21002C_REG_CTRL3, 3, 3),
 107         [F_EXTCTRLEN]           = REG_FIELD(FXAS21002C_REG_CTRL3, 2, 2),
 108         [F_FS_DOUBLE]           = REG_FIELD(FXAS21002C_REG_CTRL3, 0, 0),
 109 };
 110
 111 static const int fxas21002c_odr_values[] = {
 112         800, 400, 200, 100, 50, 25, 12, 12
 113 };
 114
 115 /*
 116  * These values are taken from the low-pass filter cutoff frequency calculated
 117  * ODR * 0.lpf_values. So, for ODR = 800Hz with a lpf value = 0.32
 118  * => LPF cutoff frequency = 800 * 0.32 = 256 Hz
 119  */
 120 static const int fxas21002c_lpf_values[] = {
 121         32, 16, 8
 122 };
 123
 124 /*
 125  * These values are taken from the high-pass filter cutoff frequency calculated
 126  * ODR * 0.0hpf_values. So, for ODR = 800Hz with a hpf value = 0.018750
 127  * => HPF cutoff frequency = 800 * 0.018750 = 15 Hz
 128  */
 129 static const int fxas21002c_hpf_values[] = {
 130         18750, 9625, 4875, 2475
 131 };
 132
 133 static const int fxas21002c_range_values[] = {
 134         4000, 2000, 1000, 500, 250
 135 };
 136
 137 struct fxas21002c_data {
 138         u8 chip_id;
 139         enum fxas21002c_mode_state mode;
 140         enum fxas21002c_mode_state prev_mode;
 141
 142         struct mutex lock;              /* serialize data access */
 143         struct regmap *regmap;
 144         struct regmap_field *regmap_fields[F_MAX_FIELDS];
 145         struct iio_trigger *dready_trig;
 146         s64 timestamp;
 147         int irq;
 148
 149         struct regulator *vdd;
 150         struct regulator *vddio;
 151
 152         /*
 153          * DMA (thus cache coherency maintenance) requires the
 154          * transfer buffers to live in their own cache lines.
 155          */
 156         s16 buffer[8] ____cacheline_aligned;
 157 };
 158
 159 enum fxas21002c_channel_index {
 160         CHANNEL_SCAN_INDEX_X,
 161         CHANNEL_SCAN_INDEX_Y,
 162         CHANNEL_SCAN_INDEX_Z,
 163         CHANNEL_SCAN_MAX,
 164 };
 165
 166 static int fxas21002c_odr_hz_from_value(struct fxas21002c_data *data, u8 value)
 167 {
 168         int odr_value_max = ARRAY_SIZE(fxas21002c_odr_values) - 1;
 169
 170         value = min_t(u8, value, odr_value_max);
 171
 172         return fxas21002c_odr_values[value];
 173 }
 174
 175 static int fxas21002c_odr_value_from_hz(struct fxas21002c_data *data,
 176                                         unsigned int hz)
 177 {
 178         int odr_table_size = ARRAY_SIZE(fxas21002c_odr_values);
 179         int i;
 180
 181         for (i = 0; i < odr_table_size; i++)
 182                 if (fxas21002c_odr_values[i] == hz)
 183                         return i;
 184
 185         return -EINVAL;
 186 }
 187
 188 static int fxas21002c_lpf_bw_from_value(struct fxas21002c_data *data, u8 value)
 189 {
 190         int lpf_value_max = ARRAY_SIZE(fxas21002c_lpf_values) - 1;
 191
 192         value = min_t(u8, value, lpf_value_max);
 193
 194         return fxas21002c_lpf_values[value];
 195 }
 196
 197 static int fxas21002c_lpf_value_from_bw(struct fxas21002c_data *data,
 198                                         unsigned int hz)
 199 {
 200         int lpf_table_size = ARRAY_SIZE(fxas21002c_lpf_values);
 201         int i;
 202
 203         for (i = 0; i < lpf_table_size; i++)
 204                 if (fxas21002c_lpf_values[i] == hz)
 205                         return i;
 206
 207         return -EINVAL;
 208 }
 209
 210 static int fxas21002c_hpf_sel_from_value(struct fxas21002c_data *data, u8 value)
 211 {
 212         int hpf_value_max = ARRAY_SIZE(fxas21002c_hpf_values) - 1;
 213
 214         value = min_t(u8, value, hpf_value_max);
 215
 216         return fxas21002c_hpf_values[value];
 217 }
 218
 219 static int fxas21002c_hpf_value_from_sel(struct fxas21002c_data *data,
 220                                          unsigned int hz)
 221 {
 222         int hpf_table_size = ARRAY_SIZE(fxas21002c_hpf_values);
 223         int i;
 224
 225         for (i = 0; i < hpf_table_size; i++)
 226                 if (fxas21002c_hpf_values[i] == hz)
 227                         return i;
 228
 229         return -EINVAL;
 230 }
 231
 232 static int fxas21002c_range_fs_from_value(struct fxas21002c_data *data,
 233                                           u8 value)
 234 {
 235         int range_value_max = ARRAY_SIZE(fxas21002c_range_values) - 1;
 236         unsigned int fs_double;
 237         int ret;
 238
 239         /* We need to check if FS_DOUBLE is enabled to offset the value */
 240         ret = regmap_field_read(data->regmap_fields[F_FS_DOUBLE], &fs_double);
 241         if (ret < 0)
 242                 return ret;
 243
 244         if (!fs_double)
 245                 value += 1;
 246
 247         value = min_t(u8, value, range_value_max);
 248
 249         return fxas21002c_range_values[value];
 250 }
 251
 252 static int fxas21002c_range_value_from_fs(struct fxas21002c_data *data,
 253                                           unsigned int range)
 254 {
 255         int range_table_size = ARRAY_SIZE(fxas21002c_range_values);
 256         bool found = false;
 257         int fs_double = 0;
 258         int ret;
 259         int i;
 260
 261         for (i = 0; i < range_table_size; i++)
 262                 if (fxas21002c_range_values[i] == range) {
 263                         found = true;
 264                         break;
 265                 }
 266
 267         if (!found)
 268                 return -EINVAL;
 269
 270         if (range > FXAS21002C_RANGE_LIMIT_DOUBLE)
 271                 fs_double = 1;
 272
 273         ret = regmap_field_write(data->regmap_fields[F_FS_DOUBLE], fs_double);
 274         if (ret < 0)
 275                 return ret;
 276
 277         return i;
 278 }
 279
 280 static int fxas21002c_mode_get(struct fxas21002c_data *data)
 281 {
 282         unsigned int active;
 283         unsigned int ready;
 284         int ret;
 285
 286         ret = regmap_field_read(data->regmap_fields[F_ACTIVE], &active);
 287         if (ret < 0)
 288                 return ret;
 289         if (active)
 290                 return FXAS21002C_MODE_ACTIVE;
 291
 292         ret = regmap_field_read(data->regmap_fields[F_READY], &ready);
 293         if (ret < 0)
 294                 return ret;
 295         if (ready)
 296                 return FXAS21002C_MODE_READY;
 297
 298         return FXAS21002C_MODE_STANDBY;
 299 }
 300
 301 static int fxas21002c_mode_set(struct fxas21002c_data *data,
 302                                enum fxas21002c_mode_state mode)
 303 {
 304         int ret;
 305
 306         if (mode == data->mode)
 307                 return 0;
 308
 309         if (mode == FXAS21002C_MODE_READY)
 310                 ret = regmap_field_write(data->regmap_fields[F_READY], 1);
 311         else
 312                 ret = regmap_field_write(data->regmap_fields[F_READY], 0);
 313         if (ret < 0)
 314                 return ret;
 315
 316         if (mode == FXAS21002C_MODE_ACTIVE)
 317                 ret = regmap_field_write(data->regmap_fields[F_ACTIVE], 1);
 318         else
 319                 ret = regmap_field_write(data->regmap_fields[F_ACTIVE], 0);
 320         if (ret < 0)
 321                 return ret;
 322
 323         /* if going to active wait the setup times */
 324         if (mode == FXAS21002C_MODE_ACTIVE &&
 325             data->mode == FXAS21002C_MODE_STANDBY)
 326                 msleep_interruptible(FXAS21002C_STANDBY_ACTIVE_TIME_MS);
 327
 328         if (data->mode == FXAS21002C_MODE_READY)
 329                 msleep_interruptible(FXAS21002C_READY_ACTIVE_TIME_MS);
 330
 331         data->prev_mode = data->mode;
 332         data->mode = mode;
 333
 334         return ret;
 335 }
 336
 337 static int fxas21002c_write(struct fxas21002c_data *data,
 338                             enum fxas21002c_fields field, int bits)
 339 {
 340         int actual_mode;
 341         int ret;
 342
 343         mutex_lock(&data->lock);
 344
 345         actual_mode = fxas21002c_mode_get(data);
 346         if (actual_mode < 0) {
 347                 ret = actual_mode;
 348                 goto out_unlock;
 349         }
 350
 351         ret = fxas21002c_mode_set(data, FXAS21002C_MODE_READY);
 352         if (ret < 0)
 353                 goto out_unlock;
 354
 355         ret = regmap_field_write(data->regmap_fields[field], bits);
 356         if (ret < 0)
 357                 goto out_unlock;
 358
 359         ret = fxas21002c_mode_set(data, data->prev_mode);
 360
 361 out_unlock:
 362         mutex_unlock(&data->lock);
 363
 364         return ret;
 365 }
 366
 367 static int  fxas21002c_pm_get(struct fxas21002c_data *data)
 368 {
 369         struct device *dev = regmap_get_device(data->regmap);
 370         int ret;
 371
 372         ret = pm_runtime_get_sync(dev);
 373         if (ret < 0)
 374                 pm_runtime_put_noidle(dev);
 375
 376         return ret;
 377 }
 378
 379 static int  fxas21002c_pm_put(struct fxas21002c_data *data)
 380 {
 381         struct device *dev = regmap_get_device(data->regmap);
 382
 383         pm_runtime_mark_last_busy(dev);
 384
 385         return pm_runtime_put_autosuspend(dev);
 386 }
 387
 388 static int fxas21002c_temp_get(struct fxas21002c_data *data, int *val)
 389 {
 390         struct device *dev = regmap_get_device(data->regmap);
 391         unsigned int temp;
 392         int ret;
 393
 394         mutex_lock(&data->lock);
 395         ret = fxas21002c_pm_get(data);
 396         if (ret < 0)
 397                 goto data_unlock;
 398
 399         ret = regmap_field_read(data->regmap_fields[F_TEMP], &temp);
 400         if (ret < 0) {
 401                 dev_err(dev, "failed to read temp: %d\n", ret);
 402                 goto data_unlock;
 403         }
 404
 405         *val = sign_extend32(temp, 7);
 406
 407         ret = fxas21002c_pm_put(data);
 408         if (ret < 0)
 409                 goto data_unlock;
 410
 411         ret = IIO_VAL_INT;
 412
 413 data_unlock:
 414         mutex_unlock(&data->lock);
 415
 416         return ret;
 417 }
 418
 419 static int fxas21002c_axis_get(struct fxas21002c_data *data,
 420                                int index, int *val)
 421 {
 422         struct device *dev = regmap_get_device(data->regmap);
 423         __be16 axis_be;
 424         int ret;
 425
 426         mutex_lock(&data->lock);
 427         ret = fxas21002c_pm_get(data);
 428         if (ret < 0)
 429                 goto data_unlock;
 430
 431         ret = regmap_bulk_read(data->regmap, FXAS21002C_AXIS_TO_REG(index),
 432                                &axis_be, sizeof(axis_be));
 433         if (ret < 0) {
 434                 dev_err(dev, "failed to read axis: %d: %d\n", index, ret);
 435                 goto data_unlock;
 436         }
 437
 438         *val = sign_extend32(be16_to_cpu(axis_be), 15);
 439
 440         ret = fxas21002c_pm_put(data);
 441         if (ret < 0)
 442                 goto data_unlock;
 443
 444         ret = IIO_VAL_INT;
 445
 446 data_unlock:
 447         mutex_unlock(&data->lock);
 448
 449         return ret;
 450 }
 451
 452 static int fxas21002c_odr_get(struct fxas21002c_data *data, int *odr)
 453 {
 454         unsigned int odr_bits;
 455         int ret;
 456
 457         mutex_lock(&data->lock);
 458         ret = regmap_field_read(data->regmap_fields[F_DR], &odr_bits);
 459         if (ret < 0)
 460                 goto data_unlock;
 461
 462         *odr = fxas21002c_odr_hz_from_value(data, odr_bits);
 463
 464         ret = IIO_VAL_INT;
 465
 466 data_unlock:
 467         mutex_unlock(&data->lock);
 468
 469         return ret;
 470 }
 471
 472 static int fxas21002c_odr_set(struct fxas21002c_data *data, int odr)
 473 {
 474         int odr_bits;
 475
 476         odr_bits = fxas21002c_odr_value_from_hz(data, odr);
 477         if (odr_bits < 0)
 478                 return odr_bits;
 479
 480         return fxas21002c_write(data, F_DR, odr_bits);
 481 }
 482
 483 static int fxas21002c_lpf_get(struct fxas21002c_data *data, int *val2)
 484 {
 485         unsigned int bw_bits;
 486         int ret;
 487
 488         mutex_lock(&data->lock);
 489         ret = regmap_field_read(data->regmap_fields[F_BW], &bw_bits);
 490         if (ret < 0)
 491                 goto data_unlock;
 492
 493         *val2 = fxas21002c_lpf_bw_from_value(data, bw_bits) * 10000;
 494
 495         ret = IIO_VAL_INT_PLUS_MICRO;
 496
 497 data_unlock:
 498         mutex_unlock(&data->lock);
 499
 500         return ret;
 501 }
 502
 503 static int fxas21002c_lpf_set(struct fxas21002c_data *data, int bw)
 504 {
 505         int bw_bits;
 506         int odr;
 507         int ret;
 508
 509         bw_bits = fxas21002c_lpf_value_from_bw(data, bw);
 510         if (bw_bits < 0)
 511                 return bw_bits;
 512
 513         /*
 514          * From table 33 of the device spec, for ODR = 25Hz and 12.5 value 0.08
 515          * is not allowed and for ODR = 12.5 value 0.16 is also not allowed
 516          */
 517         ret = fxas21002c_odr_get(data, &odr);
 518         if (ret < 0)
 519                 return -EINVAL;
 520
 521         if ((odr == 25 && bw_bits > 0x01) || (odr == 12 && bw_bits > 0))
 522                 return -EINVAL;
 523
 524         return fxas21002c_write(data, F_BW, bw_bits);
 525 }
 526
 527 static int fxas21002c_hpf_get(struct fxas21002c_data *data, int *val2)
 528 {
 529         unsigned int sel_bits;
 530         int ret;
 531
 532         mutex_lock(&data->lock);
 533         ret = regmap_field_read(data->regmap_fields[F_SEL], &sel_bits);
 534         if (ret < 0)
 535                 goto data_unlock;
 536
 537         *val2 = fxas21002c_hpf_sel_from_value(data, sel_bits);
 538
 539         ret = IIO_VAL_INT_PLUS_MICRO;
 540
 541 data_unlock:
 542         mutex_unlock(&data->lock);
 543
 544         return ret;
 545 }
 546
 547 static int fxas21002c_hpf_set(struct fxas21002c_data *data, int sel)
 548 {
 549         int sel_bits;
 550
 551         sel_bits = fxas21002c_hpf_value_from_sel(data, sel);
 552         if (sel_bits < 0)
 553                 return sel_bits;
 554
 555         return fxas21002c_write(data, F_SEL, sel_bits);
 556 }
 557
 558 static int fxas21002c_scale_get(struct fxas21002c_data *data, int *val)
 559 {
 560         int fs_bits;
 561         int scale;
 562         int ret;
 563
 564         mutex_lock(&data->lock);
 565         ret = regmap_field_read(data->regmap_fields[F_FS], &fs_bits);
 566         if (ret < 0)
 567                 goto data_unlock;
 568
 569         scale = fxas21002c_range_fs_from_value(data, fs_bits);
 570         if (scale < 0) {
 571                 ret = scale;
 572                 goto data_unlock;
 573         }
 574
 575         *val = scale;
 576
 577 data_unlock:
 578         mutex_unlock(&data->lock);
 579
 580         return ret;
 581 }
 582
 583 static int fxas21002c_scale_set(struct fxas21002c_data *data, int range)
 584 {
 585         int fs_bits;
 586
 587         fs_bits = fxas21002c_range_value_from_fs(data, range);
 588         if (fs_bits < 0)
 589                 return fs_bits;
 590
 591         return fxas21002c_write(data, F_FS, fs_bits);
 592 }
 593
 594 static int fxas21002c_read_raw(struct iio_dev *indio_dev,
 595                                struct iio_chan_spec const *chan, int *val,
 596                                int *val2, long mask)
 597 {
 598         struct fxas21002c_data *data = iio_priv(indio_dev);
 599         int ret;
 600
 601         switch (mask) {
 602         case IIO_CHAN_INFO_RAW:
 603                 switch (chan->type) {
 604                 case IIO_TEMP:
 605                         return fxas21002c_temp_get(data, val);
 606                 case IIO_ANGL_VEL:
 607                         return fxas21002c_axis_get(data, chan->scan_index, val);
 608                 default:
 609                         return -EINVAL;
 610                 }
 611         case IIO_CHAN_INFO_SCALE:
 612                 switch (chan->type) {
 613                 case IIO_ANGL_VEL:
 614                         *val2 = FXAS21002C_SCALE_FRACTIONAL;
 615                         ret = fxas21002c_scale_get(data, val);
 616                         if (ret < 0)
 617                                 return ret;
 618
 619                         return IIO_VAL_FRACTIONAL;
 620                 default:
 621                         return -EINVAL;
 622                 }
 623         case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
 624                 *val = 0;
 625                 return fxas21002c_lpf_get(data, val2);
 626         case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
 627                 *val = 0;
 628                 return fxas21002c_hpf_get(data, val2);
 629         case IIO_CHAN_INFO_SAMP_FREQ:
 630                 *val2 = 0;
 631                 return fxas21002c_odr_get(data, val);
 632         default:
 633                 return -EINVAL;
 634         }
 635 }
 636
 637 static int fxas21002c_write_raw(struct iio_dev *indio_dev,
 638                                 struct iio_chan_spec const *chan, int val,
 639                                 int val2, long mask)
 640 {
 641         struct fxas21002c_data *data = iio_priv(indio_dev);
 642         int range;
 643
 644         switch (mask) {
 645         case IIO_CHAN_INFO_SAMP_FREQ:
 646                 if (val2)
 647                         return -EINVAL;
 648
 649                 return fxas21002c_odr_set(data, val);
 650         case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
 651                 if (val)
 652                         return -EINVAL;
 653
 654                 val2 = val2 / 10000;
 655                 return fxas21002c_lpf_set(data, val2);
 656         case IIO_CHAN_INFO_SCALE:
 657                 switch (chan->type) {
 658                 case IIO_ANGL_VEL:
 659                         range = (((val * 1000 + val2 / 1000) *
 660                                   FXAS21002C_SCALE_FRACTIONAL) / 1000);
 661                         return fxas21002c_scale_set(data, range);
 662                 default:
 663                         return -EINVAL;
 664                 }
 665         case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
 666                 return fxas21002c_hpf_set(data, val2);
 667         default:
 668                 return -EINVAL;
 669         }
 670 }
 671
 672 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("12.5 25 50 100 200 400 800");
 673
 674 static IIO_CONST_ATTR(in_anglvel_filter_low_pass_3db_frequency_available,
 675                       "0.32 0.16 0.08");
 676
 677 static IIO_CONST_ATTR(in_anglvel_filter_high_pass_3db_frequency_available,
 678                       "0.018750 0.009625 0.004875 0.002475");
 679
 680 static IIO_CONST_ATTR(in_anglvel_scale_available,
 681                       "125.0 62.5 31.25 15.625 7.8125");
 682
 683 static struct attribute *fxas21002c_attributes[] = {
 684         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 685         &iio_const_attr_in_anglvel_filter_low_pass_3db_frequency_available.dev_attr.attr,
 686         &iio_const_attr_in_anglvel_filter_high_pass_3db_frequency_available.dev_attr.attr,
 687         &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
 688         NULL,
 689 };
 690
 691 static const struct attribute_group fxas21002c_attrs_group = {
 692         .attrs = fxas21002c_attributes,
 693 };
 694
 695 #define FXAS21002C_CHANNEL(_axis) {                                     \
 696         .type = IIO_ANGL_VEL,                                           \
 697         .modified = 1,                                                  \
 698         .channel2 = IIO_MOD_##_axis,                                    \
 699         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),                   \
 700         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |          \
 701                 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) |      \
 702                 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) |     \
 703                 BIT(IIO_CHAN_INFO_SAMP_FREQ),                           \
 704         .scan_index = CHANNEL_SCAN_INDEX_##_axis,                       \
 705         .scan_type = {                                                  \
 706                 .sign = 's',                                            \
 707                 .realbits = 16,                                         \
 708                 .storagebits = 16,                                      \
 709                 .endianness = IIO_BE,                                   \
 710         },                                                              \
 711 }
 712
 713 static const struct iio_chan_spec fxas21002c_channels[] = {
 714         {
 715                 .type = IIO_TEMP,
 716                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
 717                 .scan_index = -1,
 718         },
 719         FXAS21002C_CHANNEL(X),
 720         FXAS21002C_CHANNEL(Y),
 721         FXAS21002C_CHANNEL(Z),
 722 };
 723
 724 static const struct iio_info fxas21002c_info = {
 725         .attrs                  = &fxas21002c_attrs_group,
 726         .read_raw               = &fxas21002c_read_raw,
 727         .write_raw              = &fxas21002c_write_raw,
 728 };
 729
 730 static irqreturn_t fxas21002c_trigger_handler(int irq, void *p)
 731 {
 732         struct iio_poll_func *pf = p;
 733         struct iio_dev *indio_dev = pf->indio_dev;
 734         struct fxas21002c_data *data = iio_priv(indio_dev);
 735         int ret;
 736
 737         mutex_lock(&data->lock);
 738         ret = regmap_bulk_read(data->regmap, FXAS21002C_REG_OUT_X_MSB,
 739                                data->buffer, CHANNEL_SCAN_MAX * sizeof(s16));
 740         if (ret < 0)
 741                 goto out_unlock;
 742
 743         iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
 744                                            data->timestamp);
 745
 746 out_unlock:
 747         mutex_unlock(&data->lock);
 748
 749         iio_trigger_notify_done(indio_dev->trig);
 750
 751         return IRQ_HANDLED;
 752 }
 753
 754 static int fxas21002c_chip_init(struct fxas21002c_data *data)
 755 {
 756         struct device *dev = regmap_get_device(data->regmap);
 757         unsigned int chip_id;
 758         int ret;
 759
 760         ret = regmap_field_read(data->regmap_fields[F_WHO_AM_I], &chip_id);
 761         if (ret < 0)
 762                 return ret;
 763
 764         if (chip_id != FXAS21002C_CHIP_ID_1 &&
 765             chip_id != FXAS21002C_CHIP_ID_2) {
 766                 dev_err(dev, "chip id 0x%02x is not supported\n", chip_id);
 767                 return -EINVAL;
 768         }
 769
 770         data->chip_id = chip_id;
 771
 772         ret = fxas21002c_mode_set(data, FXAS21002C_MODE_STANDBY);
 773         if (ret < 0)
 774                 return ret;
 775
 776         /* Set ODR to 200HZ as default */
 777         ret = fxas21002c_odr_set(data, 200);
 778         if (ret < 0)
 779                 dev_err(dev, "failed to set ODR: %d\n", ret);
 780
 781         return ret;
 782 }
 783
 784 static int fxas21002c_data_rdy_trigger_set_state(struct iio_trigger *trig,
 785                                                  bool state)
 786 {
 787         struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
 788         struct fxas21002c_data *data = iio_priv(indio_dev);
 789
 790         return regmap_field_write(data->regmap_fields[F_INT_EN_DRDY], state);
 791 }
 792
 793 static const struct iio_trigger_ops fxas21002c_trigger_ops = {
 794         .set_trigger_state = &fxas21002c_data_rdy_trigger_set_state,
 795 };
 796
 797 static irqreturn_t fxas21002c_data_rdy_handler(int irq, void *private)
 798 {
 799         struct iio_dev *indio_dev = private;
 800         struct fxas21002c_data *data = iio_priv(indio_dev);
 801
 802         data->timestamp = iio_get_time_ns(indio_dev);
 803
 804         return IRQ_WAKE_THREAD;
 805 }
 806
 807 static irqreturn_t fxas21002c_data_rdy_thread(int irq, void *private)
 808 {
 809         struct iio_dev *indio_dev = private;
 810         struct fxas21002c_data *data = iio_priv(indio_dev);
 811         unsigned int data_ready;
 812         int ret;
 813
 814         ret = regmap_field_read(data->regmap_fields[F_SRC_DRDY], &data_ready);
 815         if (ret < 0)
 816                 return IRQ_NONE;
 817
 818         if (!data_ready)
 819                 return IRQ_NONE;
 820
 821         iio_trigger_poll_chained(data->dready_trig);
 822
 823         return IRQ_HANDLED;
 824 }
 825
 826 static int fxas21002c_trigger_probe(struct fxas21002c_data *data)
 827 {
 828         struct device *dev = regmap_get_device(data->regmap);
 829         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 830         struct device_node *np = indio_dev->dev.of_node;
 831         unsigned long irq_trig;
 832         bool irq_open_drain;
 833         int irq1;
 834         int ret;
 835
 836         if (!data->irq)
 837                 return 0;
 838
 839         irq1 = of_irq_get_byname(np, "INT1");
 840
 841         if (irq1 == data->irq) {
 842                 dev_info(dev, "using interrupt line INT1\n");
 843                 ret = regmap_field_write(data->regmap_fields[F_INT_CFG_DRDY],
 844                                          1);
 845                 if (ret < 0)
 846                         return ret;
 847         }
 848
 849         dev_info(dev, "using interrupt line INT2\n");
 850
 851         irq_open_drain = of_property_read_bool(np, "drive-open-drain");
 852
 853         data->dready_trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
 854                                                    indio_dev->name,
 855                                                    indio_dev->id);
 856         if (!data->dready_trig)
 857                 return -ENOMEM;
 858
 859         irq_trig = irqd_get_trigger_type(irq_get_irq_data(data->irq));
 860
 861         if (irq_trig == IRQF_TRIGGER_RISING) {
 862                 ret = regmap_field_write(data->regmap_fields[F_IPOL], 1);
 863                 if (ret < 0)
 864                         return ret;
 865         }
 866
 867         if (irq_open_drain)
 868                 irq_trig |= IRQF_SHARED;
 869
 870         ret = devm_request_threaded_irq(dev, data->irq,
 871                                         fxas21002c_data_rdy_handler,
 872                                         fxas21002c_data_rdy_thread,
 873                                         irq_trig, "fxas21002c_data_ready",
 874                                         indio_dev);
 875         if (ret < 0)
 876                 return ret;
 877
 878         data->dready_trig->dev.parent = dev;
 879         data->dready_trig->ops = &fxas21002c_trigger_ops;
 880         iio_trigger_set_drvdata(data->dready_trig, indio_dev);
 881
 882         return devm_iio_trigger_register(dev, data->dready_trig);
 883 }
 884
 885 static int fxas21002c_power_enable(struct fxas21002c_data *data)
 886 {
 887         int ret;
 888
 889         ret = regulator_enable(data->vdd);
 890         if (ret < 0)
 891                 return ret;
 892
 893         ret = regulator_enable(data->vddio);
 894         if (ret < 0) {
 895                 regulator_disable(data->vdd);
 896                 return ret;
 897         }
 898
 899         return 0;
 900 }
 901
 902 static void fxas21002c_power_disable(struct fxas21002c_data *data)
 903 {
 904         regulator_disable(data->vdd);
 905         regulator_disable(data->vddio);
 906 }
 907
 908 static void fxas21002c_power_disable_action(void *_data)
 909 {
 910         struct fxas21002c_data *data = _data;
 911
 912         fxas21002c_power_disable(data);
 913 }
 914
 915 static int fxas21002c_regulators_get(struct fxas21002c_data *data)
 916 {
 917         struct device *dev = regmap_get_device(data->regmap);
 918
 919         data->vdd = devm_regulator_get(dev->parent, "vdd");
 920         if (IS_ERR(data->vdd))
 921                 return PTR_ERR(data->vdd);
 922
 923         data->vddio = devm_regulator_get(dev->parent, "vddio");
 924
 925         return PTR_ERR_OR_ZERO(data->vddio);
 926 }
 927
 928 int fxas21002c_core_probe(struct device *dev, struct regmap *regmap, int irq,
 929                           const char *name)
 930 {
 931         struct fxas21002c_data *data;
 932         struct iio_dev *indio_dev;
 933         struct regmap_field *f;
 934         int i;
 935         int ret;
 936
 937         indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
 938         if (!indio_dev)
 939                 return -ENOMEM;
 940
 941         data = iio_priv(indio_dev);
 942         dev_set_drvdata(dev, indio_dev);
 943         data->irq = irq;
 944         data->regmap = regmap;
 945
 946         for (i = 0; i < F_MAX_FIELDS; i++) {
 947                 f = devm_regmap_field_alloc(dev, data->regmap,
 948                                             fxas21002c_reg_fields[i]);
 949                 if (IS_ERR(f))
 950                         return PTR_ERR(f);
 951
 952                 data->regmap_fields[i] = f;
 953         }
 954
 955         mutex_init(&data->lock);
 956
 957         ret = fxas21002c_regulators_get(data);
 958         if (ret < 0)
 959                 return ret;
 960
 961         ret = fxas21002c_power_enable(data);
 962         if (ret < 0)
 963                 return ret;
 964
 965         ret = devm_add_action_or_reset(dev, fxas21002c_power_disable_action,
 966                                        data);
 967         if (ret < 0)
 968                 return ret;
 969
 970         ret = fxas21002c_chip_init(data);
 971         if (ret < 0)
 972                 return ret;
 973
 974         indio_dev->channels = fxas21002c_channels;
 975         indio_dev->num_channels = ARRAY_SIZE(fxas21002c_channels);
 976         indio_dev->name = name;
 977         indio_dev->modes = INDIO_DIRECT_MODE;
 978         indio_dev->info = &fxas21002c_info;
 979
 980         ret = fxas21002c_trigger_probe(data);
 981         if (ret < 0)
 982                 return ret;
 983
 984         ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
 985                                               fxas21002c_trigger_handler, NULL);
 986         if (ret < 0)
 987                 return ret;
 988
 989         ret = pm_runtime_set_active(dev);
 990         if (ret)
 991                 return ret;
 992
 993         pm_runtime_enable(dev);
 994         pm_runtime_set_autosuspend_delay(dev, 2000);
 995         pm_runtime_use_autosuspend(dev);
 996
 997         ret = iio_device_register(indio_dev);
 998         if (ret < 0)
 999                 goto pm_disable;
1000
1001         return 0;
1002
1003 pm_disable:
1004         pm_runtime_disable(dev);
1005         pm_runtime_set_suspended(dev);
1006         pm_runtime_put_noidle(dev);
1007
1008         return ret;
1009 }
1010 EXPORT_SYMBOL_GPL(fxas21002c_core_probe);
1011
1012 void fxas21002c_core_remove(struct device *dev)
1013 {
1014         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1015
1016         iio_device_unregister(indio_dev);
1017
1018         pm_runtime_disable(dev);
1019         pm_runtime_set_suspended(dev);
1020         pm_runtime_put_noidle(dev);
1021 }
1022 EXPORT_SYMBOL_GPL(fxas21002c_core_remove);
1023
1024 static int __maybe_unused fxas21002c_suspend(struct device *dev)
1025 {
1026         struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
1027
1028         fxas21002c_mode_set(data, FXAS21002C_MODE_STANDBY);
1029         fxas21002c_power_disable(data);
1030
1031         return 0;
1032 }
1033
1034 static int __maybe_unused fxas21002c_resume(struct device *dev)
1035 {
1036         struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
1037         int ret;
1038
1039         ret = fxas21002c_power_enable(data);
1040         if (ret < 0)
1041                 return ret;
1042
1043         return fxas21002c_mode_set(data, data->prev_mode);
1044 }
1045
1046 static int __maybe_unused fxas21002c_runtime_suspend(struct device *dev)
1047 {
1048         struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
1049
1050         return fxas21002c_mode_set(data, FXAS21002C_MODE_READY);
1051 }
1052
1053 static int __maybe_unused fxas21002c_runtime_resume(struct device *dev)
1054 {
1055         struct fxas21002c_data *data = iio_priv(dev_get_drvdata(dev));
1056
1057         return fxas21002c_mode_set(data, FXAS21002C_MODE_ACTIVE);
1058 }
1059
1060 const struct dev_pm_ops fxas21002c_pm_ops = {
1061         SET_SYSTEM_SLEEP_PM_OPS(fxas21002c_suspend, fxas21002c_resume)
1062         SET_RUNTIME_PM_OPS(fxas21002c_runtime_suspend,
1063                            fxas21002c_runtime_resume, NULL)
1064 };
1065 EXPORT_SYMBOL_GPL(fxas21002c_pm_ops);
1066
1067 MODULE_AUTHOR("Rui Miguel Silva <rui.silva@linaro.org>");
1068 MODULE_LICENSE("GPL v2");
1069 MODULE_DESCRIPTION("FXAS21002C Gyro driver");