1 // SPDX-License-Identifier: GPL-2.0-only
3 * BMG160 Gyro Sensor driver
4 * Copyright (c) 2014, Intel Corporation.
7 #include <linux/module.h>
8 #include <linux/interrupt.h>
9 #include <linux/delay.h>
10 #include <linux/slab.h>
11 #include <linux/acpi.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/iio/iio.h>
15 #include <linux/iio/sysfs.h>
16 #include <linux/iio/buffer.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/events.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/iio/triggered_buffer.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
25 #define BMG160_IRQ_NAME "bmg160_event"
27 #define BMG160_REG_CHIP_ID 0x00
28 #define BMG160_CHIP_ID_VAL 0x0F
30 #define BMG160_REG_PMU_LPW 0x11
31 #define BMG160_MODE_NORMAL 0x00
32 #define BMG160_MODE_DEEP_SUSPEND 0x20
33 #define BMG160_MODE_SUSPEND 0x80
35 #define BMG160_REG_RANGE 0x0F
37 #define BMG160_RANGE_2000DPS 0
38 #define BMG160_RANGE_1000DPS 1
39 #define BMG160_RANGE_500DPS 2
40 #define BMG160_RANGE_250DPS 3
41 #define BMG160_RANGE_125DPS 4
43 #define BMG160_REG_PMU_BW 0x10
44 #define BMG160_NO_FILTER 0
45 #define BMG160_DEF_BW 100
46 #define BMG160_REG_PMU_BW_RES BIT(7)
48 #define BMG160_GYRO_REG_RESET 0x14
49 #define BMG160_GYRO_RESET_VAL 0xb6
51 #define BMG160_REG_INT_MAP_0 0x17
52 #define BMG160_INT_MAP_0_BIT_ANY BIT(1)
54 #define BMG160_REG_INT_MAP_1 0x18
55 #define BMG160_INT_MAP_1_BIT_NEW_DATA BIT(0)
57 #define BMG160_REG_INT_RST_LATCH 0x21
58 #define BMG160_INT_MODE_LATCH_RESET 0x80
59 #define BMG160_INT_MODE_LATCH_INT 0x0F
60 #define BMG160_INT_MODE_NON_LATCH_INT 0x00
62 #define BMG160_REG_INT_EN_0 0x15
63 #define BMG160_DATA_ENABLE_INT BIT(7)
65 #define BMG160_REG_INT_EN_1 0x16
66 #define BMG160_INT1_BIT_OD BIT(1)
68 #define BMG160_REG_XOUT_L 0x02
69 #define BMG160_AXIS_TO_REG(axis) (BMG160_REG_XOUT_L + (axis * 2))
71 #define BMG160_REG_SLOPE_THRES 0x1B
72 #define BMG160_SLOPE_THRES_MASK 0x0F
74 #define BMG160_REG_MOTION_INTR 0x1C
75 #define BMG160_INT_MOTION_X BIT(0)
76 #define BMG160_INT_MOTION_Y BIT(1)
77 #define BMG160_INT_MOTION_Z BIT(2)
78 #define BMG160_ANY_DUR_MASK 0x30
79 #define BMG160_ANY_DUR_SHIFT 4
81 #define BMG160_REG_INT_STATUS_2 0x0B
82 #define BMG160_ANY_MOTION_MASK 0x07
83 #define BMG160_ANY_MOTION_BIT_X BIT(0)
84 #define BMG160_ANY_MOTION_BIT_Y BIT(1)
85 #define BMG160_ANY_MOTION_BIT_Z BIT(2)
87 #define BMG160_REG_TEMP 0x08
88 #define BMG160_TEMP_CENTER_VAL 23
90 #define BMG160_MAX_STARTUP_TIME_MS 80
92 #define BMG160_AUTO_SUSPEND_DELAY_MS 2000
95 struct regmap *regmap;
96 struct regulator_bulk_data regulators[2];
97 struct iio_trigger *dready_trig;
98 struct iio_trigger *motion_trig;
99 struct iio_mount_matrix orientation;
105 bool dready_trigger_on;
106 bool motion_trigger_on;
117 static const struct {
121 } bmg160_samp_freq_table[] = { {100, 32, 0x07},
129 static const struct {
132 } bmg160_scale_table[] = { { 1065, BMG160_RANGE_2000DPS},
133 { 532, BMG160_RANGE_1000DPS},
134 { 266, BMG160_RANGE_500DPS},
135 { 133, BMG160_RANGE_250DPS},
136 { 66, BMG160_RANGE_125DPS} };
138 static int bmg160_set_mode(struct bmg160_data *data, u8 mode)
140 struct device *dev = regmap_get_device(data->regmap);
143 ret = regmap_write(data->regmap, BMG160_REG_PMU_LPW, mode);
145 dev_err(dev, "Error writing reg_pmu_lpw\n");
152 static int bmg160_convert_freq_to_bit(int val)
156 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
157 if (bmg160_samp_freq_table[i].odr == val)
158 return bmg160_samp_freq_table[i].bw_bits;
164 static int bmg160_set_bw(struct bmg160_data *data, int val)
166 struct device *dev = regmap_get_device(data->regmap);
170 bw_bits = bmg160_convert_freq_to_bit(val);
174 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW, bw_bits);
176 dev_err(dev, "Error writing reg_pmu_bw\n");
183 static int bmg160_get_filter(struct bmg160_data *data, int *val)
185 struct device *dev = regmap_get_device(data->regmap);
188 unsigned int bw_bits;
190 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
192 dev_err(dev, "Error reading reg_pmu_bw\n");
196 /* Ignore the readonly reserved bit. */
197 bw_bits &= ~BMG160_REG_PMU_BW_RES;
199 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
200 if (bmg160_samp_freq_table[i].bw_bits == bw_bits)
204 *val = bmg160_samp_freq_table[i].filter;
206 return ret ? ret : IIO_VAL_INT;
210 static int bmg160_set_filter(struct bmg160_data *data, int val)
212 struct device *dev = regmap_get_device(data->regmap);
216 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
217 if (bmg160_samp_freq_table[i].filter == val)
221 ret = regmap_write(data->regmap, BMG160_REG_PMU_BW,
222 bmg160_samp_freq_table[i].bw_bits);
224 dev_err(dev, "Error writing reg_pmu_bw\n");
231 static int bmg160_chip_init(struct bmg160_data *data)
233 struct device *dev = regmap_get_device(data->regmap);
238 * Reset chip to get it in a known good state. A delay of 30ms after
239 * reset is required according to the datasheet.
241 regmap_write(data->regmap, BMG160_GYRO_REG_RESET,
242 BMG160_GYRO_RESET_VAL);
243 usleep_range(30000, 30700);
245 ret = regmap_read(data->regmap, BMG160_REG_CHIP_ID, &val);
247 dev_err(dev, "Error reading reg_chip_id\n");
251 dev_dbg(dev, "Chip Id %x\n", val);
252 if (val != BMG160_CHIP_ID_VAL) {
253 dev_err(dev, "invalid chip %x\n", val);
257 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
261 /* Wait upto 500 ms to be ready after changing mode */
262 usleep_range(500, 1000);
265 ret = bmg160_set_bw(data, BMG160_DEF_BW);
269 /* Set Default Range */
270 ret = regmap_write(data->regmap, BMG160_REG_RANGE, BMG160_RANGE_500DPS);
272 dev_err(dev, "Error writing reg_range\n");
275 data->dps_range = BMG160_RANGE_500DPS;
277 ret = regmap_read(data->regmap, BMG160_REG_SLOPE_THRES, &val);
279 dev_err(dev, "Error reading reg_slope_thres\n");
282 data->slope_thres = val;
284 /* Set default interrupt mode */
285 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_EN_1,
286 BMG160_INT1_BIT_OD, 0);
288 dev_err(dev, "Error updating bits in reg_int_en_1\n");
292 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
293 BMG160_INT_MODE_LATCH_INT |
294 BMG160_INT_MODE_LATCH_RESET);
297 "Error writing reg_motion_intr\n");
304 static int bmg160_set_power_state(struct bmg160_data *data, bool on)
307 struct device *dev = regmap_get_device(data->regmap);
311 ret = pm_runtime_get_sync(dev);
313 pm_runtime_mark_last_busy(dev);
314 ret = pm_runtime_put_autosuspend(dev);
318 dev_err(dev, "Failed: bmg160_set_power_state for %d\n", on);
321 pm_runtime_put_noidle(dev);
330 static int bmg160_setup_any_motion_interrupt(struct bmg160_data *data,
333 struct device *dev = regmap_get_device(data->regmap);
336 /* Enable/Disable INT_MAP0 mapping */
337 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_0,
338 BMG160_INT_MAP_0_BIT_ANY,
339 (status ? BMG160_INT_MAP_0_BIT_ANY : 0));
341 dev_err(dev, "Error updating bits reg_int_map0\n");
345 /* Enable/Disable slope interrupts */
347 /* Update slope thres */
348 ret = regmap_write(data->regmap, BMG160_REG_SLOPE_THRES,
351 dev_err(dev, "Error writing reg_slope_thres\n");
355 ret = regmap_write(data->regmap, BMG160_REG_MOTION_INTR,
356 BMG160_INT_MOTION_X | BMG160_INT_MOTION_Y |
357 BMG160_INT_MOTION_Z);
359 dev_err(dev, "Error writing reg_motion_intr\n");
364 * New data interrupt is always non-latched,
365 * which will have higher priority, so no need
366 * to set latched mode, we will be flooded anyway with INTR
368 if (!data->dready_trigger_on) {
369 ret = regmap_write(data->regmap,
370 BMG160_REG_INT_RST_LATCH,
371 BMG160_INT_MODE_LATCH_INT |
372 BMG160_INT_MODE_LATCH_RESET);
374 dev_err(dev, "Error writing reg_rst_latch\n");
379 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
380 BMG160_DATA_ENABLE_INT);
383 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
387 dev_err(dev, "Error writing reg_int_en0\n");
394 static int bmg160_setup_new_data_interrupt(struct bmg160_data *data,
397 struct device *dev = regmap_get_device(data->regmap);
400 /* Enable/Disable INT_MAP1 mapping */
401 ret = regmap_update_bits(data->regmap, BMG160_REG_INT_MAP_1,
402 BMG160_INT_MAP_1_BIT_NEW_DATA,
403 (status ? BMG160_INT_MAP_1_BIT_NEW_DATA : 0));
405 dev_err(dev, "Error updating bits in reg_int_map1\n");
410 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
411 BMG160_INT_MODE_NON_LATCH_INT |
412 BMG160_INT_MODE_LATCH_RESET);
414 dev_err(dev, "Error writing reg_rst_latch\n");
418 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0,
419 BMG160_DATA_ENABLE_INT);
422 /* Restore interrupt mode */
423 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
424 BMG160_INT_MODE_LATCH_INT |
425 BMG160_INT_MODE_LATCH_RESET);
427 dev_err(dev, "Error writing reg_rst_latch\n");
431 ret = regmap_write(data->regmap, BMG160_REG_INT_EN_0, 0);
435 dev_err(dev, "Error writing reg_int_en0\n");
442 static int bmg160_get_bw(struct bmg160_data *data, int *val)
444 struct device *dev = regmap_get_device(data->regmap);
446 unsigned int bw_bits;
449 ret = regmap_read(data->regmap, BMG160_REG_PMU_BW, &bw_bits);
451 dev_err(dev, "Error reading reg_pmu_bw\n");
455 /* Ignore the readonly reserved bit. */
456 bw_bits &= ~BMG160_REG_PMU_BW_RES;
458 for (i = 0; i < ARRAY_SIZE(bmg160_samp_freq_table); ++i) {
459 if (bmg160_samp_freq_table[i].bw_bits == bw_bits) {
460 *val = bmg160_samp_freq_table[i].odr;
468 static int bmg160_set_scale(struct bmg160_data *data, int val)
470 struct device *dev = regmap_get_device(data->regmap);
473 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
474 if (bmg160_scale_table[i].scale == val) {
475 ret = regmap_write(data->regmap, BMG160_REG_RANGE,
476 bmg160_scale_table[i].dps_range);
478 dev_err(dev, "Error writing reg_range\n");
481 data->dps_range = bmg160_scale_table[i].dps_range;
489 static int bmg160_get_temp(struct bmg160_data *data, int *val)
491 struct device *dev = regmap_get_device(data->regmap);
493 unsigned int raw_val;
495 mutex_lock(&data->mutex);
496 ret = bmg160_set_power_state(data, true);
498 mutex_unlock(&data->mutex);
502 ret = regmap_read(data->regmap, BMG160_REG_TEMP, &raw_val);
504 dev_err(dev, "Error reading reg_temp\n");
505 bmg160_set_power_state(data, false);
506 mutex_unlock(&data->mutex);
510 *val = sign_extend32(raw_val, 7);
511 ret = bmg160_set_power_state(data, false);
512 mutex_unlock(&data->mutex);
519 static int bmg160_get_axis(struct bmg160_data *data, int axis, int *val)
521 struct device *dev = regmap_get_device(data->regmap);
525 mutex_lock(&data->mutex);
526 ret = bmg160_set_power_state(data, true);
528 mutex_unlock(&data->mutex);
532 ret = regmap_bulk_read(data->regmap, BMG160_AXIS_TO_REG(axis), &raw_val,
535 dev_err(dev, "Error reading axis %d\n", axis);
536 bmg160_set_power_state(data, false);
537 mutex_unlock(&data->mutex);
541 *val = sign_extend32(le16_to_cpu(raw_val), 15);
542 ret = bmg160_set_power_state(data, false);
543 mutex_unlock(&data->mutex);
550 static int bmg160_read_raw(struct iio_dev *indio_dev,
551 struct iio_chan_spec const *chan,
552 int *val, int *val2, long mask)
554 struct bmg160_data *data = iio_priv(indio_dev);
558 case IIO_CHAN_INFO_RAW:
559 switch (chan->type) {
561 return bmg160_get_temp(data, val);
563 if (iio_buffer_enabled(indio_dev))
566 return bmg160_get_axis(data, chan->scan_index,
571 case IIO_CHAN_INFO_OFFSET:
572 if (chan->type == IIO_TEMP) {
573 *val = BMG160_TEMP_CENTER_VAL;
577 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
578 return bmg160_get_filter(data, val);
579 case IIO_CHAN_INFO_SCALE:
580 switch (chan->type) {
588 for (i = 0; i < ARRAY_SIZE(bmg160_scale_table); ++i) {
589 if (bmg160_scale_table[i].dps_range ==
592 *val2 = bmg160_scale_table[i].scale;
593 return IIO_VAL_INT_PLUS_MICRO;
601 case IIO_CHAN_INFO_SAMP_FREQ:
603 mutex_lock(&data->mutex);
604 ret = bmg160_get_bw(data, val);
605 mutex_unlock(&data->mutex);
612 static int bmg160_write_raw(struct iio_dev *indio_dev,
613 struct iio_chan_spec const *chan,
614 int val, int val2, long mask)
616 struct bmg160_data *data = iio_priv(indio_dev);
620 case IIO_CHAN_INFO_SAMP_FREQ:
621 mutex_lock(&data->mutex);
623 * Section 4.2 of spec
624 * In suspend mode, the only supported operations are reading
625 * registers as well as writing to the (0x14) softreset
626 * register. Since we will be in suspend mode by default, change
627 * mode to power on for other writes.
629 ret = bmg160_set_power_state(data, true);
631 mutex_unlock(&data->mutex);
634 ret = bmg160_set_bw(data, val);
636 bmg160_set_power_state(data, false);
637 mutex_unlock(&data->mutex);
640 ret = bmg160_set_power_state(data, false);
641 mutex_unlock(&data->mutex);
643 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
647 mutex_lock(&data->mutex);
648 ret = bmg160_set_power_state(data, true);
650 bmg160_set_power_state(data, false);
651 mutex_unlock(&data->mutex);
654 ret = bmg160_set_filter(data, val);
656 bmg160_set_power_state(data, false);
657 mutex_unlock(&data->mutex);
660 ret = bmg160_set_power_state(data, false);
661 mutex_unlock(&data->mutex);
663 case IIO_CHAN_INFO_SCALE:
667 mutex_lock(&data->mutex);
668 /* Refer to comments above for the suspend mode ops */
669 ret = bmg160_set_power_state(data, true);
671 mutex_unlock(&data->mutex);
674 ret = bmg160_set_scale(data, val2);
676 bmg160_set_power_state(data, false);
677 mutex_unlock(&data->mutex);
680 ret = bmg160_set_power_state(data, false);
681 mutex_unlock(&data->mutex);
690 static int bmg160_read_event(struct iio_dev *indio_dev,
691 const struct iio_chan_spec *chan,
692 enum iio_event_type type,
693 enum iio_event_direction dir,
694 enum iio_event_info info,
697 struct bmg160_data *data = iio_priv(indio_dev);
701 case IIO_EV_INFO_VALUE:
702 *val = data->slope_thres & BMG160_SLOPE_THRES_MASK;
711 static int bmg160_write_event(struct iio_dev *indio_dev,
712 const struct iio_chan_spec *chan,
713 enum iio_event_type type,
714 enum iio_event_direction dir,
715 enum iio_event_info info,
718 struct bmg160_data *data = iio_priv(indio_dev);
721 case IIO_EV_INFO_VALUE:
722 if (data->ev_enable_state)
724 data->slope_thres &= ~BMG160_SLOPE_THRES_MASK;
725 data->slope_thres |= (val & BMG160_SLOPE_THRES_MASK);
734 static int bmg160_read_event_config(struct iio_dev *indio_dev,
735 const struct iio_chan_spec *chan,
736 enum iio_event_type type,
737 enum iio_event_direction dir)
740 struct bmg160_data *data = iio_priv(indio_dev);
742 return data->ev_enable_state;
745 static int bmg160_write_event_config(struct iio_dev *indio_dev,
746 const struct iio_chan_spec *chan,
747 enum iio_event_type type,
748 enum iio_event_direction dir,
751 struct bmg160_data *data = iio_priv(indio_dev);
754 if (state && data->ev_enable_state)
757 mutex_lock(&data->mutex);
759 if (!state && data->motion_trigger_on) {
760 data->ev_enable_state = 0;
761 mutex_unlock(&data->mutex);
765 * We will expect the enable and disable to do operation in
766 * in reverse order. This will happen here anyway as our
767 * resume operation uses sync mode runtime pm calls, the
768 * suspend operation will be delayed by autosuspend delay
769 * So the disable operation will still happen in reverse of
770 * enable operation. When runtime pm is disabled the mode
771 * is always on so sequence doesn't matter
773 ret = bmg160_set_power_state(data, state);
775 mutex_unlock(&data->mutex);
779 ret = bmg160_setup_any_motion_interrupt(data, state);
781 bmg160_set_power_state(data, false);
782 mutex_unlock(&data->mutex);
786 data->ev_enable_state = state;
787 mutex_unlock(&data->mutex);
792 static const struct iio_mount_matrix *
793 bmg160_get_mount_matrix(const struct iio_dev *indio_dev,
794 const struct iio_chan_spec *chan)
796 struct bmg160_data *data = iio_priv(indio_dev);
798 return &data->orientation;
801 static const struct iio_chan_spec_ext_info bmg160_ext_info[] = {
802 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmg160_get_mount_matrix),
806 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100 200 400 1000 2000");
808 static IIO_CONST_ATTR(in_anglvel_scale_available,
809 "0.001065 0.000532 0.000266 0.000133 0.000066");
811 static struct attribute *bmg160_attributes[] = {
812 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
813 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
817 static const struct attribute_group bmg160_attrs_group = {
818 .attrs = bmg160_attributes,
821 static const struct iio_event_spec bmg160_event = {
822 .type = IIO_EV_TYPE_ROC,
823 .dir = IIO_EV_DIR_EITHER,
824 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
825 BIT(IIO_EV_INFO_ENABLE)
828 #define BMG160_CHANNEL(_axis) { \
829 .type = IIO_ANGL_VEL, \
831 .channel2 = IIO_MOD_##_axis, \
832 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
833 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
834 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
835 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
836 .scan_index = AXIS_##_axis, \
841 .endianness = IIO_LE, \
843 .ext_info = bmg160_ext_info, \
844 .event_spec = &bmg160_event, \
845 .num_event_specs = 1 \
848 static const struct iio_chan_spec bmg160_channels[] = {
851 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
852 BIT(IIO_CHAN_INFO_SCALE) |
853 BIT(IIO_CHAN_INFO_OFFSET),
859 IIO_CHAN_SOFT_TIMESTAMP(3),
862 static const struct iio_info bmg160_info = {
863 .attrs = &bmg160_attrs_group,
864 .read_raw = bmg160_read_raw,
865 .write_raw = bmg160_write_raw,
866 .read_event_value = bmg160_read_event,
867 .write_event_value = bmg160_write_event,
868 .write_event_config = bmg160_write_event_config,
869 .read_event_config = bmg160_read_event_config,
872 static const unsigned long bmg160_accel_scan_masks[] = {
873 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
876 static irqreturn_t bmg160_trigger_handler(int irq, void *p)
878 struct iio_poll_func *pf = p;
879 struct iio_dev *indio_dev = pf->indio_dev;
880 struct bmg160_data *data = iio_priv(indio_dev);
883 mutex_lock(&data->mutex);
884 ret = regmap_bulk_read(data->regmap, BMG160_REG_XOUT_L,
885 data->buffer, AXIS_MAX * 2);
886 mutex_unlock(&data->mutex);
890 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
893 iio_trigger_notify_done(indio_dev->trig);
898 static void bmg160_trig_reen(struct iio_trigger *trig)
900 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
901 struct bmg160_data *data = iio_priv(indio_dev);
902 struct device *dev = regmap_get_device(data->regmap);
905 /* new data interrupts don't need ack */
906 if (data->dready_trigger_on)
909 /* Set latched mode interrupt and clear any latched interrupt */
910 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
911 BMG160_INT_MODE_LATCH_INT |
912 BMG160_INT_MODE_LATCH_RESET);
914 dev_err(dev, "Error writing reg_rst_latch\n");
917 static int bmg160_data_rdy_trigger_set_state(struct iio_trigger *trig,
920 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
921 struct bmg160_data *data = iio_priv(indio_dev);
924 mutex_lock(&data->mutex);
926 if (!state && data->ev_enable_state && data->motion_trigger_on) {
927 data->motion_trigger_on = false;
928 mutex_unlock(&data->mutex);
933 * Refer to comment in bmg160_write_event_config for
934 * enable/disable operation order
936 ret = bmg160_set_power_state(data, state);
938 mutex_unlock(&data->mutex);
941 if (data->motion_trig == trig)
942 ret = bmg160_setup_any_motion_interrupt(data, state);
944 ret = bmg160_setup_new_data_interrupt(data, state);
946 bmg160_set_power_state(data, false);
947 mutex_unlock(&data->mutex);
950 if (data->motion_trig == trig)
951 data->motion_trigger_on = state;
953 data->dready_trigger_on = state;
955 mutex_unlock(&data->mutex);
960 static const struct iio_trigger_ops bmg160_trigger_ops = {
961 .set_trigger_state = bmg160_data_rdy_trigger_set_state,
962 .reenable = bmg160_trig_reen,
965 static irqreturn_t bmg160_event_handler(int irq, void *private)
967 struct iio_dev *indio_dev = private;
968 struct bmg160_data *data = iio_priv(indio_dev);
969 struct device *dev = regmap_get_device(data->regmap);
974 ret = regmap_read(data->regmap, BMG160_REG_INT_STATUS_2, &val);
976 dev_err(dev, "Error reading reg_int_status2\n");
977 goto ack_intr_status;
981 dir = IIO_EV_DIR_RISING;
983 dir = IIO_EV_DIR_FALLING;
985 if (val & BMG160_ANY_MOTION_BIT_X)
986 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
991 iio_get_time_ns(indio_dev));
992 if (val & BMG160_ANY_MOTION_BIT_Y)
993 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
998 iio_get_time_ns(indio_dev));
999 if (val & BMG160_ANY_MOTION_BIT_Z)
1000 iio_push_event(indio_dev, IIO_MOD_EVENT_CODE(IIO_ANGL_VEL,
1005 iio_get_time_ns(indio_dev));
1008 if (!data->dready_trigger_on) {
1009 ret = regmap_write(data->regmap, BMG160_REG_INT_RST_LATCH,
1010 BMG160_INT_MODE_LATCH_INT |
1011 BMG160_INT_MODE_LATCH_RESET);
1013 dev_err(dev, "Error writing reg_rst_latch\n");
1019 static irqreturn_t bmg160_data_rdy_trig_poll(int irq, void *private)
1021 struct iio_dev *indio_dev = private;
1022 struct bmg160_data *data = iio_priv(indio_dev);
1024 if (data->dready_trigger_on)
1025 iio_trigger_poll(data->dready_trig);
1026 else if (data->motion_trigger_on)
1027 iio_trigger_poll(data->motion_trig);
1029 if (data->ev_enable_state)
1030 return IRQ_WAKE_THREAD;
1036 static int bmg160_buffer_preenable(struct iio_dev *indio_dev)
1038 struct bmg160_data *data = iio_priv(indio_dev);
1040 return bmg160_set_power_state(data, true);
1043 static int bmg160_buffer_postdisable(struct iio_dev *indio_dev)
1045 struct bmg160_data *data = iio_priv(indio_dev);
1047 return bmg160_set_power_state(data, false);
1050 static const struct iio_buffer_setup_ops bmg160_buffer_setup_ops = {
1051 .preenable = bmg160_buffer_preenable,
1052 .postdisable = bmg160_buffer_postdisable,
1055 static const char *bmg160_match_acpi_device(struct device *dev)
1057 const struct acpi_device_id *id;
1059 id = acpi_match_device(dev->driver->acpi_match_table, dev);
1063 return dev_name(dev);
1066 static void bmg160_disable_regulators(void *d)
1068 struct bmg160_data *data = d;
1070 regulator_bulk_disable(ARRAY_SIZE(data->regulators), data->regulators);
1073 int bmg160_core_probe(struct device *dev, struct regmap *regmap, int irq,
1076 struct bmg160_data *data;
1077 struct iio_dev *indio_dev;
1080 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1084 data = iio_priv(indio_dev);
1085 dev_set_drvdata(dev, indio_dev);
1087 data->regmap = regmap;
1089 data->regulators[0].supply = "vdd";
1090 data->regulators[1].supply = "vddio";
1091 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(data->regulators),
1094 return dev_err_probe(dev, ret, "Failed to get regulators\n");
1096 ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators),
1101 ret = devm_add_action_or_reset(dev, bmg160_disable_regulators, data);
1105 ret = iio_read_mount_matrix(dev, "mount-matrix",
1106 &data->orientation);
1110 ret = bmg160_chip_init(data);
1114 mutex_init(&data->mutex);
1116 if (ACPI_HANDLE(dev))
1117 name = bmg160_match_acpi_device(dev);
1119 indio_dev->channels = bmg160_channels;
1120 indio_dev->num_channels = ARRAY_SIZE(bmg160_channels);
1121 indio_dev->name = name;
1122 indio_dev->available_scan_masks = bmg160_accel_scan_masks;
1123 indio_dev->modes = INDIO_DIRECT_MODE;
1124 indio_dev->info = &bmg160_info;
1126 if (data->irq > 0) {
1127 ret = devm_request_threaded_irq(dev,
1129 bmg160_data_rdy_trig_poll,
1130 bmg160_event_handler,
1131 IRQF_TRIGGER_RISING,
1137 data->dready_trig = devm_iio_trigger_alloc(dev,
1141 if (!data->dready_trig)
1144 data->motion_trig = devm_iio_trigger_alloc(dev,
1145 "%s-any-motion-dev%d",
1148 if (!data->motion_trig)
1151 data->dready_trig->ops = &bmg160_trigger_ops;
1152 iio_trigger_set_drvdata(data->dready_trig, indio_dev);
1153 ret = iio_trigger_register(data->dready_trig);
1157 data->motion_trig->ops = &bmg160_trigger_ops;
1158 iio_trigger_set_drvdata(data->motion_trig, indio_dev);
1159 ret = iio_trigger_register(data->motion_trig);
1161 data->motion_trig = NULL;
1162 goto err_trigger_unregister;
1166 ret = iio_triggered_buffer_setup(indio_dev,
1167 iio_pollfunc_store_time,
1168 bmg160_trigger_handler,
1169 &bmg160_buffer_setup_ops);
1172 "iio triggered buffer setup failed\n");
1173 goto err_trigger_unregister;
1176 ret = pm_runtime_set_active(dev);
1178 goto err_buffer_cleanup;
1180 pm_runtime_enable(dev);
1181 pm_runtime_set_autosuspend_delay(dev,
1182 BMG160_AUTO_SUSPEND_DELAY_MS);
1183 pm_runtime_use_autosuspend(dev);
1185 ret = iio_device_register(indio_dev);
1187 dev_err(dev, "unable to register iio device\n");
1188 goto err_buffer_cleanup;
1194 iio_triggered_buffer_cleanup(indio_dev);
1195 err_trigger_unregister:
1196 if (data->dready_trig)
1197 iio_trigger_unregister(data->dready_trig);
1198 if (data->motion_trig)
1199 iio_trigger_unregister(data->motion_trig);
1203 EXPORT_SYMBOL_GPL(bmg160_core_probe);
1205 void bmg160_core_remove(struct device *dev)
1207 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1208 struct bmg160_data *data = iio_priv(indio_dev);
1210 iio_device_unregister(indio_dev);
1212 pm_runtime_disable(dev);
1213 pm_runtime_set_suspended(dev);
1214 pm_runtime_put_noidle(dev);
1216 iio_triggered_buffer_cleanup(indio_dev);
1218 if (data->dready_trig) {
1219 iio_trigger_unregister(data->dready_trig);
1220 iio_trigger_unregister(data->motion_trig);
1223 mutex_lock(&data->mutex);
1224 bmg160_set_mode(data, BMG160_MODE_DEEP_SUSPEND);
1225 mutex_unlock(&data->mutex);
1227 EXPORT_SYMBOL_GPL(bmg160_core_remove);
1229 #ifdef CONFIG_PM_SLEEP
1230 static int bmg160_suspend(struct device *dev)
1232 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1233 struct bmg160_data *data = iio_priv(indio_dev);
1235 mutex_lock(&data->mutex);
1236 bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1237 mutex_unlock(&data->mutex);
1242 static int bmg160_resume(struct device *dev)
1244 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1245 struct bmg160_data *data = iio_priv(indio_dev);
1247 mutex_lock(&data->mutex);
1248 if (data->dready_trigger_on || data->motion_trigger_on ||
1249 data->ev_enable_state)
1250 bmg160_set_mode(data, BMG160_MODE_NORMAL);
1251 mutex_unlock(&data->mutex);
1258 static int bmg160_runtime_suspend(struct device *dev)
1260 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1261 struct bmg160_data *data = iio_priv(indio_dev);
1264 ret = bmg160_set_mode(data, BMG160_MODE_SUSPEND);
1266 dev_err(dev, "set mode failed\n");
1273 static int bmg160_runtime_resume(struct device *dev)
1275 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1276 struct bmg160_data *data = iio_priv(indio_dev);
1279 ret = bmg160_set_mode(data, BMG160_MODE_NORMAL);
1283 msleep_interruptible(BMG160_MAX_STARTUP_TIME_MS);
1289 const struct dev_pm_ops bmg160_pm_ops = {
1290 SET_SYSTEM_SLEEP_PM_OPS(bmg160_suspend, bmg160_resume)
1291 SET_RUNTIME_PM_OPS(bmg160_runtime_suspend,
1292 bmg160_runtime_resume, NULL)
1294 EXPORT_SYMBOL_GPL(bmg160_pm_ops);
1296 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1297 MODULE_LICENSE("GPL v2");
1298 MODULE_DESCRIPTION("BMG160 Gyro driver");