1 // SPDX-License-Identifier: GPL-2.0
3 * This file is part of STM32 DAC driver
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Authors: Amelie Delaunay <amelie.delaunay@st.com>
7 * Fabrice Gasnier <fabrice.gasnier@st.com>
10 #include <linux/bitfield.h>
11 #include <linux/delay.h>
12 #include <linux/iio/iio.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
18 #include "stm32-dac-core.h"
20 #define STM32_DAC_CHANNEL_1 1
21 #define STM32_DAC_CHANNEL_2 2
22 #define STM32_DAC_IS_CHAN_1(ch) ((ch) & STM32_DAC_CHANNEL_1)
24 #define STM32_DAC_AUTO_SUSPEND_DELAY_MS 2000
27 * struct stm32_dac - private data of DAC driver
28 * @common: reference to DAC common data
29 * @lock: lock to protect against potential races when reading
30 * and update CR, to keep it in sync with pm_runtime
33 struct stm32_dac_common *common;
37 static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel)
39 struct stm32_dac *dac = iio_priv(indio_dev);
43 ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
46 if (STM32_DAC_IS_CHAN_1(channel))
47 en = FIELD_GET(STM32_DAC_CR_EN1, val);
49 en = FIELD_GET(STM32_DAC_CR_EN2, val);
54 static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch,
57 struct stm32_dac *dac = iio_priv(indio_dev);
58 struct device *dev = indio_dev->dev.parent;
59 u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2;
60 u32 en = enable ? msk : 0;
63 /* already enabled / disabled ? */
64 mutex_lock(&dac->lock);
65 ret = stm32_dac_is_enabled(indio_dev, ch);
66 if (ret < 0 || enable == !!ret) {
67 mutex_unlock(&dac->lock);
68 return ret < 0 ? ret : 0;
72 ret = pm_runtime_resume_and_get(dev);
74 mutex_unlock(&dac->lock);
79 ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en);
80 mutex_unlock(&dac->lock);
82 dev_err(&indio_dev->dev, "%s failed\n", en ?
83 "Enable" : "Disable");
88 * When HFSEL is set, it is not allowed to write the DHRx register
89 * during 8 clock cycles after the ENx bit is set. It is not allowed
90 * to make software/hardware trigger during this period either.
92 if (en && dac->common->hfsel)
96 pm_runtime_mark_last_busy(dev);
97 pm_runtime_put_autosuspend(dev);
104 pm_runtime_mark_last_busy(dev);
105 pm_runtime_put_autosuspend(dev);
111 static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val)
115 if (STM32_DAC_IS_CHAN_1(channel))
116 ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val);
118 ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val);
120 return ret ? ret : IIO_VAL_INT;
123 static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val)
127 if (STM32_DAC_IS_CHAN_1(channel))
128 ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val);
130 ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val);
135 static int stm32_dac_read_raw(struct iio_dev *indio_dev,
136 struct iio_chan_spec const *chan,
137 int *val, int *val2, long mask)
139 struct stm32_dac *dac = iio_priv(indio_dev);
142 case IIO_CHAN_INFO_RAW:
143 return stm32_dac_get_value(dac, chan->channel, val);
144 case IIO_CHAN_INFO_SCALE:
145 *val = dac->common->vref_mv;
146 *val2 = chan->scan_type.realbits;
147 return IIO_VAL_FRACTIONAL_LOG2;
153 static int stm32_dac_write_raw(struct iio_dev *indio_dev,
154 struct iio_chan_spec const *chan,
155 int val, int val2, long mask)
157 struct stm32_dac *dac = iio_priv(indio_dev);
160 case IIO_CHAN_INFO_RAW:
161 return stm32_dac_set_value(dac, chan->channel, val);
167 static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev,
168 unsigned reg, unsigned writeval,
171 struct stm32_dac *dac = iio_priv(indio_dev);
174 return regmap_write(dac->common->regmap, reg, writeval);
176 return regmap_read(dac->common->regmap, reg, readval);
179 static const struct iio_info stm32_dac_iio_info = {
180 .read_raw = stm32_dac_read_raw,
181 .write_raw = stm32_dac_write_raw,
182 .debugfs_reg_access = stm32_dac_debugfs_reg_access,
185 static const char * const stm32_dac_powerdown_modes[] = {
189 static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev,
190 const struct iio_chan_spec *chan)
195 static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev,
196 const struct iio_chan_spec *chan,
202 static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev,
204 const struct iio_chan_spec *chan,
207 int ret = stm32_dac_is_enabled(indio_dev, chan->channel);
212 return sysfs_emit(buf, "%d\n", ret ? 0 : 1);
215 static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
217 const struct iio_chan_spec *chan,
218 const char *buf, size_t len)
223 ret = strtobool(buf, &powerdown);
227 ret = stm32_dac_set_enable_state(indio_dev, chan->channel, !powerdown);
234 static const struct iio_enum stm32_dac_powerdown_mode_en = {
235 .items = stm32_dac_powerdown_modes,
236 .num_items = ARRAY_SIZE(stm32_dac_powerdown_modes),
237 .get = stm32_dac_get_powerdown_mode,
238 .set = stm32_dac_set_powerdown_mode,
241 static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = {
244 .read = stm32_dac_read_powerdown,
245 .write = stm32_dac_write_powerdown,
246 .shared = IIO_SEPARATE,
248 IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en),
249 IIO_ENUM_AVAILABLE("powerdown_mode", &stm32_dac_powerdown_mode_en),
253 #define STM32_DAC_CHANNEL(chan, name) { \
254 .type = IIO_VOLTAGE, \
258 .info_mask_separate = \
259 BIT(IIO_CHAN_INFO_RAW) | \
260 BIT(IIO_CHAN_INFO_SCALE), \
261 /* scan_index is always 0 as num_channels is 1 */ \
267 .datasheet_name = name, \
268 .ext_info = stm32_dac_ext_info \
271 static const struct iio_chan_spec stm32_dac_channels[] = {
272 STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1"),
273 STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2"),
276 static int stm32_dac_chan_of_init(struct iio_dev *indio_dev)
278 struct device_node *np = indio_dev->dev.of_node;
283 ret = of_property_read_u32(np, "reg", &channel);
285 dev_err(&indio_dev->dev, "Failed to read reg property\n");
289 for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) {
290 if (stm32_dac_channels[i].channel == channel)
293 if (i >= ARRAY_SIZE(stm32_dac_channels)) {
294 dev_err(&indio_dev->dev, "Invalid reg property\n");
298 indio_dev->channels = &stm32_dac_channels[i];
300 * Expose only one channel here, as they can be used independently,
301 * with separate trigger. Then separate IIO devices are instantiated
304 indio_dev->num_channels = 1;
309 static int stm32_dac_probe(struct platform_device *pdev)
311 struct device_node *np = pdev->dev.of_node;
312 struct device *dev = &pdev->dev;
313 struct iio_dev *indio_dev;
314 struct stm32_dac *dac;
320 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac));
323 platform_set_drvdata(pdev, indio_dev);
325 dac = iio_priv(indio_dev);
326 dac->common = dev_get_drvdata(pdev->dev.parent);
327 indio_dev->name = dev_name(&pdev->dev);
328 indio_dev->dev.of_node = pdev->dev.of_node;
329 indio_dev->info = &stm32_dac_iio_info;
330 indio_dev->modes = INDIO_DIRECT_MODE;
332 mutex_init(&dac->lock);
334 ret = stm32_dac_chan_of_init(indio_dev);
338 /* Get stm32-dac-core PM online */
339 pm_runtime_get_noresume(dev);
340 pm_runtime_set_active(dev);
341 pm_runtime_set_autosuspend_delay(dev, STM32_DAC_AUTO_SUSPEND_DELAY_MS);
342 pm_runtime_use_autosuspend(dev);
343 pm_runtime_enable(dev);
345 ret = iio_device_register(indio_dev);
349 pm_runtime_mark_last_busy(dev);
350 pm_runtime_put_autosuspend(dev);
355 pm_runtime_disable(dev);
356 pm_runtime_set_suspended(dev);
357 pm_runtime_put_noidle(dev);
362 static int stm32_dac_remove(struct platform_device *pdev)
364 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
366 pm_runtime_get_sync(&pdev->dev);
367 iio_device_unregister(indio_dev);
368 pm_runtime_disable(&pdev->dev);
369 pm_runtime_set_suspended(&pdev->dev);
370 pm_runtime_put_noidle(&pdev->dev);
375 static int __maybe_unused stm32_dac_suspend(struct device *dev)
377 struct iio_dev *indio_dev = dev_get_drvdata(dev);
378 int channel = indio_dev->channels[0].channel;
381 /* Ensure DAC is disabled before suspend */
382 ret = stm32_dac_is_enabled(indio_dev, channel);
384 return ret < 0 ? ret : -EBUSY;
386 return pm_runtime_force_suspend(dev);
389 static const struct dev_pm_ops stm32_dac_pm_ops = {
390 SET_SYSTEM_SLEEP_PM_OPS(stm32_dac_suspend, pm_runtime_force_resume)
393 static const struct of_device_id stm32_dac_of_match[] = {
394 { .compatible = "st,stm32-dac", },
397 MODULE_DEVICE_TABLE(of, stm32_dac_of_match);
399 static struct platform_driver stm32_dac_driver = {
400 .probe = stm32_dac_probe,
401 .remove = stm32_dac_remove,
404 .of_match_table = stm32_dac_of_match,
405 .pm = &stm32_dac_pm_ops,
408 module_platform_driver(stm32_dac_driver);
410 MODULE_ALIAS("platform:stm32-dac");
411 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
412 MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver");
413 MODULE_LICENSE("GPL v2");