1 // SPDX-License-Identifier: GPL-2.0-only
3 * AD5592R Digital <-> Analog converters driver
5 * Copyright 2014-2016 Analog Devices Inc.
6 * Author: Paul Cercueil <paul.cercueil@analog.com>
9 #include <linux/bitops.h>
10 #include <linux/delay.h>
11 #include <linux/iio/iio.h>
12 #include <linux/module.h>
13 #include <linux/mutex.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/property.h>
20 #include <dt-bindings/iio/adi,ad5592r.h>
22 #include "ad5592r-base.h"
24 static int ad5592r_gpio_get(struct gpio_chip *chip, unsigned offset)
26 struct ad5592r_state *st = gpiochip_get_data(chip);
30 mutex_lock(&st->gpio_lock);
32 if (st->gpio_out & BIT(offset))
35 ret = st->ops->gpio_read(st, &val);
37 mutex_unlock(&st->gpio_lock);
42 return !!(val & BIT(offset));
45 static void ad5592r_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
47 struct ad5592r_state *st = gpiochip_get_data(chip);
49 mutex_lock(&st->gpio_lock);
52 st->gpio_val |= BIT(offset);
54 st->gpio_val &= ~BIT(offset);
56 st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
58 mutex_unlock(&st->gpio_lock);
61 static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
63 struct ad5592r_state *st = gpiochip_get_data(chip);
66 mutex_lock(&st->gpio_lock);
68 st->gpio_out &= ~BIT(offset);
69 st->gpio_in |= BIT(offset);
71 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
75 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
78 mutex_unlock(&st->gpio_lock);
83 static int ad5592r_gpio_direction_output(struct gpio_chip *chip,
84 unsigned offset, int value)
86 struct ad5592r_state *st = gpiochip_get_data(chip);
89 mutex_lock(&st->gpio_lock);
92 st->gpio_val |= BIT(offset);
94 st->gpio_val &= ~BIT(offset);
96 st->gpio_in &= ~BIT(offset);
97 st->gpio_out |= BIT(offset);
99 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
103 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
107 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
110 mutex_unlock(&st->gpio_lock);
115 static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset)
117 struct ad5592r_state *st = gpiochip_get_data(chip);
119 if (!(st->gpio_map & BIT(offset))) {
120 dev_err(st->dev, "GPIO %d is reserved by alternate function\n",
128 static int ad5592r_gpio_init(struct ad5592r_state *st)
133 st->gpiochip.label = dev_name(st->dev);
134 st->gpiochip.base = -1;
135 st->gpiochip.ngpio = 8;
136 st->gpiochip.parent = st->dev;
137 st->gpiochip.can_sleep = true;
138 st->gpiochip.direction_input = ad5592r_gpio_direction_input;
139 st->gpiochip.direction_output = ad5592r_gpio_direction_output;
140 st->gpiochip.get = ad5592r_gpio_get;
141 st->gpiochip.set = ad5592r_gpio_set;
142 st->gpiochip.request = ad5592r_gpio_request;
143 st->gpiochip.owner = THIS_MODULE;
145 mutex_init(&st->gpio_lock);
147 return gpiochip_add_data(&st->gpiochip, st);
150 static void ad5592r_gpio_cleanup(struct ad5592r_state *st)
153 gpiochip_remove(&st->gpiochip);
156 static int ad5592r_reset(struct ad5592r_state *st)
158 struct gpio_desc *gpio;
160 gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_LOW);
162 return PTR_ERR(gpio);
166 gpiod_set_value(gpio, 1);
168 mutex_lock(&st->lock);
169 /* Writing this magic value resets the device */
170 st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac);
171 mutex_unlock(&st->lock);
179 static int ad5592r_get_vref(struct ad5592r_state *st)
184 ret = regulator_get_voltage(st->reg);
194 static int ad5592r_set_channel_modes(struct ad5592r_state *st)
196 const struct ad5592r_rw_ops *ops = st->ops;
199 u8 pulldown = 0, tristate = 0, dac = 0, adc = 0;
202 for (i = 0; i < st->num_channels; i++) {
203 switch (st->channel_modes[i]) {
212 case CH_MODE_DAC_AND_ADC:
218 st->gpio_map |= BIT(i);
219 st->gpio_in |= BIT(i); /* Default to input */
225 switch (st->channel_offstate[i]) {
226 case CH_OFFSTATE_OUT_TRISTATE:
230 case CH_OFFSTATE_OUT_LOW:
231 st->gpio_out |= BIT(i);
234 case CH_OFFSTATE_OUT_HIGH:
235 st->gpio_out |= BIT(i);
236 st->gpio_val |= BIT(i);
239 case CH_OFFSTATE_PULLDOWN:
248 mutex_lock(&st->lock);
250 /* Pull down unused pins to GND */
251 ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown);
255 ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate);
259 /* Configure pins that we use */
260 ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac);
264 ret = ops->reg_write(st, AD5592R_REG_ADC_EN, adc);
268 ret = ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val);
272 ret = ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out);
276 ret = ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in);
280 /* Verify that we can read back at least one register */
281 ret = ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back);
282 if (!ret && (read_back & 0xff) != adc)
286 mutex_unlock(&st->lock);
290 static int ad5592r_reset_channel_modes(struct ad5592r_state *st)
294 for (i = 0; i < ARRAY_SIZE(st->channel_modes); i++)
295 st->channel_modes[i] = CH_MODE_UNUSED;
297 return ad5592r_set_channel_modes(st);
300 static int ad5592r_write_raw(struct iio_dev *iio_dev,
301 struct iio_chan_spec const *chan, int val, int val2, long mask)
303 struct ad5592r_state *st = iio_priv(iio_dev);
307 case IIO_CHAN_INFO_RAW:
309 if (val >= (1 << chan->scan_type.realbits) || val < 0)
315 mutex_lock(&st->lock);
316 ret = st->ops->write_dac(st, chan->channel, val);
318 st->cached_dac[chan->channel] = val;
319 mutex_unlock(&st->lock);
321 case IIO_CHAN_INFO_SCALE:
322 if (chan->type == IIO_VOLTAGE) {
325 if (val == st->scale_avail[0][0] &&
326 val2 == st->scale_avail[0][1])
328 else if (val == st->scale_avail[1][0] &&
329 val2 == st->scale_avail[1][1])
334 mutex_lock(&st->lock);
336 ret = st->ops->reg_read(st, AD5592R_REG_CTRL,
337 &st->cached_gp_ctrl);
339 mutex_unlock(&st->lock);
345 st->cached_gp_ctrl |=
346 AD5592R_REG_CTRL_DAC_RANGE;
348 st->cached_gp_ctrl &=
349 ~AD5592R_REG_CTRL_DAC_RANGE;
352 st->cached_gp_ctrl |=
353 AD5592R_REG_CTRL_ADC_RANGE;
355 st->cached_gp_ctrl &=
356 ~AD5592R_REG_CTRL_ADC_RANGE;
359 ret = st->ops->reg_write(st, AD5592R_REG_CTRL,
361 mutex_unlock(&st->lock);
373 static int ad5592r_read_raw(struct iio_dev *iio_dev,
374 struct iio_chan_spec const *chan,
375 int *val, int *val2, long m)
377 struct ad5592r_state *st = iio_priv(iio_dev);
382 case IIO_CHAN_INFO_RAW:
383 mutex_lock(&st->lock);
386 ret = st->ops->read_adc(st, chan->channel, &read_val);
390 if ((read_val >> 12 & 0x7) != (chan->channel & 0x7)) {
391 dev_err(st->dev, "Error while reading channel %u\n",
397 read_val &= GENMASK(11, 0);
400 read_val = st->cached_dac[chan->channel];
403 dev_dbg(st->dev, "Channel %u read: 0x%04hX\n",
404 chan->channel, read_val);
406 *val = (int) read_val;
409 case IIO_CHAN_INFO_SCALE:
410 *val = ad5592r_get_vref(st);
412 if (chan->type == IIO_TEMP) {
413 s64 tmp = *val * (3767897513LL / 25LL);
414 *val = div_s64_rem(tmp, 1000000000LL, val2);
416 ret = IIO_VAL_INT_PLUS_MICRO;
420 mutex_lock(&st->lock);
423 mult = !!(st->cached_gp_ctrl &
424 AD5592R_REG_CTRL_DAC_RANGE);
426 mult = !!(st->cached_gp_ctrl &
427 AD5592R_REG_CTRL_ADC_RANGE);
431 *val2 = chan->scan_type.realbits;
432 ret = IIO_VAL_FRACTIONAL_LOG2;
435 case IIO_CHAN_INFO_OFFSET:
436 ret = ad5592r_get_vref(st);
438 mutex_lock(&st->lock);
440 if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE)
441 *val = (-34365 * 25) / ret;
443 *val = (-75365 * 25) / ret;
451 mutex_unlock(&st->lock);
455 static int ad5592r_write_raw_get_fmt(struct iio_dev *indio_dev,
456 struct iio_chan_spec const *chan, long mask)
459 case IIO_CHAN_INFO_SCALE:
460 return IIO_VAL_INT_PLUS_NANO;
463 return IIO_VAL_INT_PLUS_MICRO;
469 static const struct iio_info ad5592r_info = {
470 .read_raw = ad5592r_read_raw,
471 .write_raw = ad5592r_write_raw,
472 .write_raw_get_fmt = ad5592r_write_raw_get_fmt,
475 static ssize_t ad5592r_show_scale_available(struct iio_dev *iio_dev,
477 const struct iio_chan_spec *chan,
480 struct ad5592r_state *st = iio_priv(iio_dev);
482 return sprintf(buf, "%d.%09u %d.%09u\n",
483 st->scale_avail[0][0], st->scale_avail[0][1],
484 st->scale_avail[1][0], st->scale_avail[1][1]);
487 static struct iio_chan_spec_ext_info ad5592r_ext_info[] = {
489 .name = "scale_available",
490 .read = ad5592r_show_scale_available,
496 static void ad5592r_setup_channel(struct iio_dev *iio_dev,
497 struct iio_chan_spec *chan, bool output, unsigned id)
499 chan->type = IIO_VOLTAGE;
501 chan->output = output;
503 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
504 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
505 chan->scan_type.sign = 'u';
506 chan->scan_type.realbits = 12;
507 chan->scan_type.storagebits = 16;
508 chan->ext_info = ad5592r_ext_info;
511 static int ad5592r_alloc_channels(struct ad5592r_state *st)
513 unsigned i, curr_channel = 0,
514 num_channels = st->num_channels;
515 struct iio_dev *iio_dev = iio_priv_to_dev(st);
516 struct iio_chan_spec *channels;
517 struct fwnode_handle *child;
521 device_for_each_child_node(st->dev, child) {
522 ret = fwnode_property_read_u32(child, "reg", ®);
523 if (ret || reg >= ARRAY_SIZE(st->channel_modes))
526 ret = fwnode_property_read_u32(child, "adi,mode", &tmp);
528 st->channel_modes[reg] = tmp;
530 fwnode_property_read_u32(child, "adi,off-state", &tmp);
532 st->channel_offstate[reg] = tmp;
535 channels = devm_kcalloc(st->dev,
536 1 + 2 * num_channels, sizeof(*channels),
541 for (i = 0; i < num_channels; i++) {
542 switch (st->channel_modes[i]) {
544 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
550 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
555 case CH_MODE_DAC_AND_ADC:
556 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
559 ad5592r_setup_channel(iio_dev, &channels[curr_channel],
569 channels[curr_channel].type = IIO_TEMP;
570 channels[curr_channel].channel = 8;
571 channels[curr_channel].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
572 BIT(IIO_CHAN_INFO_SCALE) |
573 BIT(IIO_CHAN_INFO_OFFSET);
576 iio_dev->num_channels = curr_channel;
577 iio_dev->channels = channels;
582 static void ad5592r_init_scales(struct ad5592r_state *st, int vref_mV)
584 s64 tmp = (s64)vref_mV * 1000000000LL >> 12;
586 st->scale_avail[0][0] =
587 div_s64_rem(tmp, 1000000000LL, &st->scale_avail[0][1]);
588 st->scale_avail[1][0] =
589 div_s64_rem(tmp * 2, 1000000000LL, &st->scale_avail[1][1]);
592 int ad5592r_probe(struct device *dev, const char *name,
593 const struct ad5592r_rw_ops *ops)
595 struct iio_dev *iio_dev;
596 struct ad5592r_state *st;
599 iio_dev = devm_iio_device_alloc(dev, sizeof(*st));
603 st = iio_priv(iio_dev);
606 st->num_channels = 8;
607 dev_set_drvdata(dev, iio_dev);
609 st->reg = devm_regulator_get_optional(dev, "vref");
610 if (IS_ERR(st->reg)) {
611 if ((PTR_ERR(st->reg) != -ENODEV) && dev->of_node)
612 return PTR_ERR(st->reg);
616 ret = regulator_enable(st->reg);
621 iio_dev->dev.parent = dev;
622 iio_dev->name = name;
623 iio_dev->info = &ad5592r_info;
624 iio_dev->modes = INDIO_DIRECT_MODE;
626 mutex_init(&st->lock);
628 ad5592r_init_scales(st, ad5592r_get_vref(st));
630 ret = ad5592r_reset(st);
632 goto error_disable_reg;
634 ret = ops->reg_write(st, AD5592R_REG_PD,
635 (st->reg == NULL) ? AD5592R_REG_PD_EN_REF : 0);
637 goto error_disable_reg;
639 ret = ad5592r_alloc_channels(st);
641 goto error_disable_reg;
643 ret = ad5592r_set_channel_modes(st);
645 goto error_reset_ch_modes;
647 ret = iio_device_register(iio_dev);
649 goto error_reset_ch_modes;
651 ret = ad5592r_gpio_init(st);
653 goto error_dev_unregister;
657 error_dev_unregister:
658 iio_device_unregister(iio_dev);
660 error_reset_ch_modes:
661 ad5592r_reset_channel_modes(st);
665 regulator_disable(st->reg);
669 EXPORT_SYMBOL_GPL(ad5592r_probe);
671 int ad5592r_remove(struct device *dev)
673 struct iio_dev *iio_dev = dev_get_drvdata(dev);
674 struct ad5592r_state *st = iio_priv(iio_dev);
676 iio_device_unregister(iio_dev);
677 ad5592r_reset_channel_modes(st);
678 ad5592r_gpio_cleanup(st);
681 regulator_disable(st->reg);
685 EXPORT_SYMBOL_GPL(ad5592r_remove);
687 MODULE_AUTHOR("Paul Cercueil <paul.cercueil@analog.com>");
688 MODULE_DESCRIPTION("Analog Devices AD5592R multi-channel converters");
689 MODULE_LICENSE("GPL v2");