drivers/iio/adc/vf610_adc.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Freescale Vybrid vf610 ADC driver
   4  *
   5  * Copyright 2013 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <linux/mod_devicetable.h>
   9 #include <linux/module.h>
  10 #include <linux/property.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/delay.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/io.h>
  17 #include <linux/clk.h>
  18 #include <linux/completion.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/err.h>
  21
  22 #include <linux/iio/iio.h>
  23 #include <linux/iio/buffer.h>
  24 #include <linux/iio/sysfs.h>
  25 #include <linux/iio/trigger.h>
  26 #include <linux/iio/trigger_consumer.h>
  27 #include <linux/iio/triggered_buffer.h>
  28
  29 /* This will be the driver name the kernel reports */
  30 #define DRIVER_NAME "vf610-adc"
  31
  32 /* Vybrid/IMX ADC registers */
  33 #define VF610_REG_ADC_HC0               0x00
  34 #define VF610_REG_ADC_HC1               0x04
  35 #define VF610_REG_ADC_HS                0x08
  36 #define VF610_REG_ADC_R0                0x0c
  37 #define VF610_REG_ADC_R1                0x10
  38 #define VF610_REG_ADC_CFG               0x14
  39 #define VF610_REG_ADC_GC                0x18
  40 #define VF610_REG_ADC_GS                0x1c
  41 #define VF610_REG_ADC_CV                0x20
  42 #define VF610_REG_ADC_OFS               0x24
  43 #define VF610_REG_ADC_CAL               0x28
  44 #define VF610_REG_ADC_PCTL              0x30
  45
  46 /* Configuration register field define */
  47 #define VF610_ADC_MODE_BIT8             0x00
  48 #define VF610_ADC_MODE_BIT10            0x04
  49 #define VF610_ADC_MODE_BIT12            0x08
  50 #define VF610_ADC_MODE_MASK             0x0c
  51 #define VF610_ADC_BUSCLK2_SEL           0x01
  52 #define VF610_ADC_ALTCLK_SEL            0x02
  53 #define VF610_ADC_ADACK_SEL             0x03
  54 #define VF610_ADC_ADCCLK_MASK           0x03
  55 #define VF610_ADC_CLK_DIV2              0x20
  56 #define VF610_ADC_CLK_DIV4              0x40
  57 #define VF610_ADC_CLK_DIV8              0x60
  58 #define VF610_ADC_CLK_MASK              0x60
  59 #define VF610_ADC_ADLSMP_LONG           0x10
  60 #define VF610_ADC_ADSTS_SHORT   0x100
  61 #define VF610_ADC_ADSTS_NORMAL  0x200
  62 #define VF610_ADC_ADSTS_LONG    0x300
  63 #define VF610_ADC_ADSTS_MASK            0x300
  64 #define VF610_ADC_ADLPC_EN              0x80
  65 #define VF610_ADC_ADHSC_EN              0x400
  66 #define VF610_ADC_REFSEL_VALT           0x800
  67 #define VF610_ADC_REFSEL_VBG            0x1000
  68 #define VF610_ADC_ADTRG_HARD            0x2000
  69 #define VF610_ADC_AVGS_8                0x4000
  70 #define VF610_ADC_AVGS_16               0x8000
  71 #define VF610_ADC_AVGS_32               0xC000
  72 #define VF610_ADC_AVGS_MASK             0xC000
  73 #define VF610_ADC_OVWREN                0x10000
  74
  75 /* General control register field define */
  76 #define VF610_ADC_ADACKEN               0x1
  77 #define VF610_ADC_DMAEN                 0x2
  78 #define VF610_ADC_ACREN                 0x4
  79 #define VF610_ADC_ACFGT                 0x8
  80 #define VF610_ADC_ACFE                  0x10
  81 #define VF610_ADC_AVGEN                 0x20
  82 #define VF610_ADC_ADCON                 0x40
  83 #define VF610_ADC_CAL                   0x80
  84
  85 /* Other field define */
  86 #define VF610_ADC_ADCHC(x)              ((x) & 0x1F)
  87 #define VF610_ADC_AIEN                  (0x1 << 7)
  88 #define VF610_ADC_CONV_DISABLE          0x1F
  89 #define VF610_ADC_HS_COCO0              0x1
  90 #define VF610_ADC_CALF                  0x2
  91 #define VF610_ADC_TIMEOUT               msecs_to_jiffies(100)
  92
  93 #define DEFAULT_SAMPLE_TIME             1000
  94
  95 /* V at 25°C of 696 mV */
  96 #define VF610_VTEMP25_3V0               950
  97 /* V at 25°C of 699 mV */
  98 #define VF610_VTEMP25_3V3               867
  99 /* Typical sensor slope coefficient at all temperatures */
 100 #define VF610_TEMP_SLOPE_COEFF          1840
 101
 102 enum clk_sel {
 103         VF610_ADCIOC_BUSCLK_SET,
 104         VF610_ADCIOC_ALTCLK_SET,
 105         VF610_ADCIOC_ADACK_SET,
 106 };
 107
 108 enum vol_ref {
 109         VF610_ADCIOC_VR_VREF_SET,
 110         VF610_ADCIOC_VR_VALT_SET,
 111         VF610_ADCIOC_VR_VBG_SET,
 112 };
 113
 114 enum average_sel {
 115         VF610_ADC_SAMPLE_1,
 116         VF610_ADC_SAMPLE_4,
 117         VF610_ADC_SAMPLE_8,
 118         VF610_ADC_SAMPLE_16,
 119         VF610_ADC_SAMPLE_32,
 120 };
 121
 122 enum conversion_mode_sel {
 123         VF610_ADC_CONV_NORMAL,
 124         VF610_ADC_CONV_HIGH_SPEED,
 125         VF610_ADC_CONV_LOW_POWER,
 126 };
 127
 128 enum lst_adder_sel {
 129         VF610_ADCK_CYCLES_3,
 130         VF610_ADCK_CYCLES_5,
 131         VF610_ADCK_CYCLES_7,
 132         VF610_ADCK_CYCLES_9,
 133         VF610_ADCK_CYCLES_13,
 134         VF610_ADCK_CYCLES_17,
 135         VF610_ADCK_CYCLES_21,
 136         VF610_ADCK_CYCLES_25,
 137 };
 138
 139 struct vf610_adc_feature {
 140         enum clk_sel    clk_sel;
 141         enum vol_ref    vol_ref;
 142         enum conversion_mode_sel conv_mode;
 143
 144         int     clk_div;
 145         int     sample_rate;
 146         int     res_mode;
 147         u32 lst_adder_index;
 148         u32 default_sample_time;
 149
 150         bool    calibration;
 151         bool    ovwren;
 152 };
 153
 154 struct vf610_adc {
 155         struct device *dev;
 156         void __iomem *regs;
 157         struct clk *clk;
 158
 159         u32 vref_uv;
 160         u32 value;
 161         struct regulator *vref;
 162
 163         u32 max_adck_rate[3];
 164         struct vf610_adc_feature adc_feature;
 165
 166         u32 sample_freq_avail[5];
 167
 168         struct completion completion;
 169         /* Ensure the timestamp is naturally aligned */
 170         struct {
 171                 u16 chan;
 172                 s64 timestamp __aligned(8);
 173         } scan;
 174 };
 175
 176 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
 177 static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 };
 178
 179 static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
 180 {
 181         struct vf610_adc_feature *adc_feature = &info->adc_feature;
 182         unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
 183         u32 adck_period, lst_addr_min;
 184         int divisor, i;
 185
 186         adck_rate = info->max_adck_rate[adc_feature->conv_mode];
 187
 188         if (adck_rate) {
 189                 /* calculate clk divider which is within specification */
 190                 divisor = ipg_rate / adck_rate;
 191                 adc_feature->clk_div = 1 << fls(divisor + 1);
 192         } else {
 193                 /* fall-back value using a safe divisor */
 194                 adc_feature->clk_div = 8;
 195         }
 196
 197         adck_rate = ipg_rate / adc_feature->clk_div;
 198
 199         /*
 200          * Determine the long sample time adder value to be used based
 201          * on the default minimum sample time provided.
 202          */
 203         adck_period = NSEC_PER_SEC / adck_rate;
 204         lst_addr_min = adc_feature->default_sample_time / adck_period;
 205         for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) {
 206                 if (vf610_lst_adder[i] > lst_addr_min) {
 207                         adc_feature->lst_adder_index = i;
 208                         break;
 209                 }
 210         }
 211
 212         /*
 213          * Calculate ADC sample frequencies
 214          * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
 215          * which is the same as bus clock.
 216          *
 217          * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
 218          * SFCAdder: fixed to 6 ADCK cycles
 219          * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
 220          * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
 221          * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles
 222          */
 223         for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
 224                 info->sample_freq_avail[i] =
 225                         adck_rate / (6 + vf610_hw_avgs[i] *
 226                          (25 + vf610_lst_adder[adc_feature->lst_adder_index]));
 227 }
 228
 229 static inline void vf610_adc_cfg_init(struct vf610_adc *info)
 230 {
 231         struct vf610_adc_feature *adc_feature = &info->adc_feature;
 232
 233         /* set default Configuration for ADC controller */
 234         adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
 235         adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
 236
 237         adc_feature->calibration = true;
 238         adc_feature->ovwren = true;
 239
 240         adc_feature->res_mode = 12;
 241         adc_feature->sample_rate = 1;
 242
 243         adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
 244
 245         vf610_adc_calculate_rates(info);
 246 }
 247
 248 static void vf610_adc_cfg_post_set(struct vf610_adc *info)
 249 {
 250         struct vf610_adc_feature *adc_feature = &info->adc_feature;
 251         int cfg_data = 0;
 252         int gc_data = 0;
 253
 254         switch (adc_feature->clk_sel) {
 255         case VF610_ADCIOC_ALTCLK_SET:
 256                 cfg_data |= VF610_ADC_ALTCLK_SEL;
 257                 break;
 258         case VF610_ADCIOC_ADACK_SET:
 259                 cfg_data |= VF610_ADC_ADACK_SEL;
 260                 break;
 261         default:
 262                 break;
 263         }
 264
 265         /* low power set for calibration */
 266         cfg_data |= VF610_ADC_ADLPC_EN;
 267
 268         /* enable high speed for calibration */
 269         cfg_data |= VF610_ADC_ADHSC_EN;
 270
 271         /* voltage reference */
 272         switch (adc_feature->vol_ref) {
 273         case VF610_ADCIOC_VR_VREF_SET:
 274                 break;
 275         case VF610_ADCIOC_VR_VALT_SET:
 276                 cfg_data |= VF610_ADC_REFSEL_VALT;
 277                 break;
 278         case VF610_ADCIOC_VR_VBG_SET:
 279                 cfg_data |= VF610_ADC_REFSEL_VBG;
 280                 break;
 281         default:
 282                 dev_err(info->dev, "error voltage reference\n");
 283         }
 284
 285         /* data overwrite enable */
 286         if (adc_feature->ovwren)
 287                 cfg_data |= VF610_ADC_OVWREN;
 288
 289         writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
 290         writel(gc_data, info->regs + VF610_REG_ADC_GC);
 291 }
 292
 293 static void vf610_adc_calibration(struct vf610_adc *info)
 294 {
 295         int adc_gc, hc_cfg;
 296
 297         if (!info->adc_feature.calibration)
 298                 return;
 299
 300         /* enable calibration interrupt */
 301         hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
 302         writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 303
 304         adc_gc = readl(info->regs + VF610_REG_ADC_GC);
 305         writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
 306
 307         if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
 308                 dev_err(info->dev, "Timeout for adc calibration\n");
 309
 310         adc_gc = readl(info->regs + VF610_REG_ADC_GS);
 311         if (adc_gc & VF610_ADC_CALF)
 312                 dev_err(info->dev, "ADC calibration failed\n");
 313
 314         info->adc_feature.calibration = false;
 315 }
 316
 317 static void vf610_adc_cfg_set(struct vf610_adc *info)
 318 {
 319         struct vf610_adc_feature *adc_feature = &(info->adc_feature);
 320         int cfg_data;
 321
 322         cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
 323
 324         cfg_data &= ~VF610_ADC_ADLPC_EN;
 325         if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
 326                 cfg_data |= VF610_ADC_ADLPC_EN;
 327
 328         cfg_data &= ~VF610_ADC_ADHSC_EN;
 329         if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
 330                 cfg_data |= VF610_ADC_ADHSC_EN;
 331
 332         writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
 333 }
 334
 335 static void vf610_adc_sample_set(struct vf610_adc *info)
 336 {
 337         struct vf610_adc_feature *adc_feature = &(info->adc_feature);
 338         int cfg_data, gc_data;
 339
 340         cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
 341         gc_data = readl(info->regs + VF610_REG_ADC_GC);
 342
 343         /* resolution mode */
 344         cfg_data &= ~VF610_ADC_MODE_MASK;
 345         switch (adc_feature->res_mode) {
 346         case 8:
 347                 cfg_data |= VF610_ADC_MODE_BIT8;
 348                 break;
 349         case 10:
 350                 cfg_data |= VF610_ADC_MODE_BIT10;
 351                 break;
 352         case 12:
 353                 cfg_data |= VF610_ADC_MODE_BIT12;
 354                 break;
 355         default:
 356                 dev_err(info->dev, "error resolution mode\n");
 357                 break;
 358         }
 359
 360         /* clock select and clock divider */
 361         cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
 362         switch (adc_feature->clk_div) {
 363         case 1:
 364                 break;
 365         case 2:
 366                 cfg_data |= VF610_ADC_CLK_DIV2;
 367                 break;
 368         case 4:
 369                 cfg_data |= VF610_ADC_CLK_DIV4;
 370                 break;
 371         case 8:
 372                 cfg_data |= VF610_ADC_CLK_DIV8;
 373                 break;
 374         case 16:
 375                 switch (adc_feature->clk_sel) {
 376                 case VF610_ADCIOC_BUSCLK_SET:
 377                         cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
 378                         break;
 379                 default:
 380                         dev_err(info->dev, "error clk divider\n");
 381                         break;
 382                 }
 383                 break;
 384         }
 385
 386         /*
 387          * Set ADLSMP and ADSTS based on the Long Sample Time Adder value
 388          * determined.
 389          */
 390         switch (adc_feature->lst_adder_index) {
 391         case VF610_ADCK_CYCLES_3:
 392                 break;
 393         case VF610_ADCK_CYCLES_5:
 394                 cfg_data |= VF610_ADC_ADSTS_SHORT;
 395                 break;
 396         case VF610_ADCK_CYCLES_7:
 397                 cfg_data |= VF610_ADC_ADSTS_NORMAL;
 398                 break;
 399         case VF610_ADCK_CYCLES_9:
 400                 cfg_data |= VF610_ADC_ADSTS_LONG;
 401                 break;
 402         case VF610_ADCK_CYCLES_13:
 403                 cfg_data |= VF610_ADC_ADLSMP_LONG;
 404                 break;
 405         case VF610_ADCK_CYCLES_17:
 406                 cfg_data |= VF610_ADC_ADLSMP_LONG;
 407                 cfg_data |= VF610_ADC_ADSTS_SHORT;
 408                 break;
 409         case VF610_ADCK_CYCLES_21:
 410                 cfg_data |= VF610_ADC_ADLSMP_LONG;
 411                 cfg_data |= VF610_ADC_ADSTS_NORMAL;
 412                 break;
 413         case VF610_ADCK_CYCLES_25:
 414                 cfg_data |= VF610_ADC_ADLSMP_LONG;
 415                 cfg_data |= VF610_ADC_ADSTS_NORMAL;
 416                 break;
 417         default:
 418                 dev_err(info->dev, "error in sample time select\n");
 419         }
 420
 421         /* update hardware average selection */
 422         cfg_data &= ~VF610_ADC_AVGS_MASK;
 423         gc_data &= ~VF610_ADC_AVGEN;
 424         switch (adc_feature->sample_rate) {
 425         case VF610_ADC_SAMPLE_1:
 426                 break;
 427         case VF610_ADC_SAMPLE_4:
 428                 gc_data |= VF610_ADC_AVGEN;
 429                 break;
 430         case VF610_ADC_SAMPLE_8:
 431                 gc_data |= VF610_ADC_AVGEN;
 432                 cfg_data |= VF610_ADC_AVGS_8;
 433                 break;
 434         case VF610_ADC_SAMPLE_16:
 435                 gc_data |= VF610_ADC_AVGEN;
 436                 cfg_data |= VF610_ADC_AVGS_16;
 437                 break;
 438         case VF610_ADC_SAMPLE_32:
 439                 gc_data |= VF610_ADC_AVGEN;
 440                 cfg_data |= VF610_ADC_AVGS_32;
 441                 break;
 442         default:
 443                 dev_err(info->dev,
 444                         "error hardware sample average select\n");
 445         }
 446
 447         writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
 448         writel(gc_data, info->regs + VF610_REG_ADC_GC);
 449 }
 450
 451 static void vf610_adc_hw_init(struct vf610_adc *info)
 452 {
 453         /* CFG: Feature set */
 454         vf610_adc_cfg_post_set(info);
 455         vf610_adc_sample_set(info);
 456
 457         /* adc calibration */
 458         vf610_adc_calibration(info);
 459
 460         /* CFG: power and speed set */
 461         vf610_adc_cfg_set(info);
 462 }
 463
 464 static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
 465                                      const struct iio_chan_spec *chan,
 466                                      unsigned int mode)
 467 {
 468         struct vf610_adc *info = iio_priv(indio_dev);
 469
 470         mutex_lock(&indio_dev->mlock);
 471         info->adc_feature.conv_mode = mode;
 472         vf610_adc_calculate_rates(info);
 473         vf610_adc_hw_init(info);
 474         mutex_unlock(&indio_dev->mlock);
 475
 476         return 0;
 477 }
 478
 479 static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
 480                                      const struct iio_chan_spec *chan)
 481 {
 482         struct vf610_adc *info = iio_priv(indio_dev);
 483
 484         return info->adc_feature.conv_mode;
 485 }
 486
 487 static const char * const vf610_conv_modes[] = { "normal", "high-speed",
 488                                                  "low-power" };
 489
 490 static const struct iio_enum vf610_conversion_mode = {
 491         .items = vf610_conv_modes,
 492         .num_items = ARRAY_SIZE(vf610_conv_modes),
 493         .get = vf610_get_conversion_mode,
 494         .set = vf610_set_conversion_mode,
 495 };
 496
 497 static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
 498         IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
 499         {},
 500 };
 501
 502 #define VF610_ADC_CHAN(_idx, _chan_type) {                      \
 503         .type = (_chan_type),                                   \
 504         .indexed = 1,                                           \
 505         .channel = (_idx),                                      \
 506         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 507         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |  \
 508                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
 509         .ext_info = vf610_ext_info,                             \
 510         .scan_index = (_idx),                   \
 511         .scan_type = {                                  \
 512                 .sign = 'u',                            \
 513                 .realbits = 12,                         \
 514                 .storagebits = 16,                      \
 515         },                                              \
 516 }
 517
 518 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) {  \
 519         .type = (_chan_type),   \
 520         .channel = (_idx),              \
 521         .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),     \
 522         .scan_index = (_idx),                                   \
 523         .scan_type = {                                          \
 524                 .sign = 'u',                                    \
 525                 .realbits = 12,                                 \
 526                 .storagebits = 16,                              \
 527         },                                                      \
 528 }
 529
 530 static const struct iio_chan_spec vf610_adc_iio_channels[] = {
 531         VF610_ADC_CHAN(0, IIO_VOLTAGE),
 532         VF610_ADC_CHAN(1, IIO_VOLTAGE),
 533         VF610_ADC_CHAN(2, IIO_VOLTAGE),
 534         VF610_ADC_CHAN(3, IIO_VOLTAGE),
 535         VF610_ADC_CHAN(4, IIO_VOLTAGE),
 536         VF610_ADC_CHAN(5, IIO_VOLTAGE),
 537         VF610_ADC_CHAN(6, IIO_VOLTAGE),
 538         VF610_ADC_CHAN(7, IIO_VOLTAGE),
 539         VF610_ADC_CHAN(8, IIO_VOLTAGE),
 540         VF610_ADC_CHAN(9, IIO_VOLTAGE),
 541         VF610_ADC_CHAN(10, IIO_VOLTAGE),
 542         VF610_ADC_CHAN(11, IIO_VOLTAGE),
 543         VF610_ADC_CHAN(12, IIO_VOLTAGE),
 544         VF610_ADC_CHAN(13, IIO_VOLTAGE),
 545         VF610_ADC_CHAN(14, IIO_VOLTAGE),
 546         VF610_ADC_CHAN(15, IIO_VOLTAGE),
 547         VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
 548         IIO_CHAN_SOFT_TIMESTAMP(32),
 549         /* sentinel */
 550 };
 551
 552 static int vf610_adc_read_data(struct vf610_adc *info)
 553 {
 554         int result;
 555
 556         result = readl(info->regs + VF610_REG_ADC_R0);
 557
 558         switch (info->adc_feature.res_mode) {
 559         case 8:
 560                 result &= 0xFF;
 561                 break;
 562         case 10:
 563                 result &= 0x3FF;
 564                 break;
 565         case 12:
 566                 result &= 0xFFF;
 567                 break;
 568         default:
 569                 break;
 570         }
 571
 572         return result;
 573 }
 574
 575 static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
 576 {
 577         struct iio_dev *indio_dev = dev_id;
 578         struct vf610_adc *info = iio_priv(indio_dev);
 579         int coco;
 580
 581         coco = readl(info->regs + VF610_REG_ADC_HS);
 582         if (coco & VF610_ADC_HS_COCO0) {
 583                 info->value = vf610_adc_read_data(info);
 584                 if (iio_buffer_enabled(indio_dev)) {
 585                         info->scan.chan = info->value;
 586                         iio_push_to_buffers_with_timestamp(indio_dev,
 587                                         &info->scan,
 588                                         iio_get_time_ns(indio_dev));
 589                         iio_trigger_notify_done(indio_dev->trig);
 590                 } else
 591                         complete(&info->completion);
 592         }
 593
 594         return IRQ_HANDLED;
 595 }
 596
 597 static ssize_t vf610_show_samp_freq_avail(struct device *dev,
 598                                 struct device_attribute *attr, char *buf)
 599 {
 600         struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
 601         size_t len = 0;
 602         int i;
 603
 604         for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
 605                 len += scnprintf(buf + len, PAGE_SIZE - len,
 606                         "%u ", info->sample_freq_avail[i]);
 607
 608         /* replace trailing space by newline */
 609         buf[len - 1] = '\n';
 610
 611         return len;
 612 }
 613
 614 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
 615
 616 static struct attribute *vf610_attributes[] = {
 617         &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
 618         NULL
 619 };
 620
 621 static const struct attribute_group vf610_attribute_group = {
 622         .attrs = vf610_attributes,
 623 };
 624
 625 static int vf610_read_raw(struct iio_dev *indio_dev,
 626                         struct iio_chan_spec const *chan,
 627                         int *val,
 628                         int *val2,
 629                         long mask)
 630 {
 631         struct vf610_adc *info = iio_priv(indio_dev);
 632         unsigned int hc_cfg;
 633         long ret;
 634
 635         switch (mask) {
 636         case IIO_CHAN_INFO_RAW:
 637         case IIO_CHAN_INFO_PROCESSED:
 638                 mutex_lock(&indio_dev->mlock);
 639                 if (iio_buffer_enabled(indio_dev)) {
 640                         mutex_unlock(&indio_dev->mlock);
 641                         return -EBUSY;
 642                 }
 643
 644                 reinit_completion(&info->completion);
 645                 hc_cfg = VF610_ADC_ADCHC(chan->channel);
 646                 hc_cfg |= VF610_ADC_AIEN;
 647                 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 648                 ret = wait_for_completion_interruptible_timeout
 649                                 (&info->completion, VF610_ADC_TIMEOUT);
 650                 if (ret == 0) {
 651                         mutex_unlock(&indio_dev->mlock);
 652                         return -ETIMEDOUT;
 653                 }
 654                 if (ret < 0) {
 655                         mutex_unlock(&indio_dev->mlock);
 656                         return ret;
 657                 }
 658
 659                 switch (chan->type) {
 660                 case IIO_VOLTAGE:
 661                         *val = info->value;
 662                         break;
 663                 case IIO_TEMP:
 664                         /*
 665                          * Calculate in degree Celsius times 1000
 666                          * Using the typical sensor slope of 1.84 mV/°C
 667                          * and VREFH_ADC at 3.3V, V at 25°C of 699 mV
 668                          */
 669                         *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) *
 670                                         1000000 / VF610_TEMP_SLOPE_COEFF;
 671
 672                         break;
 673                 default:
 674                         mutex_unlock(&indio_dev->mlock);
 675                         return -EINVAL;
 676                 }
 677
 678                 mutex_unlock(&indio_dev->mlock);
 679                 return IIO_VAL_INT;
 680
 681         case IIO_CHAN_INFO_SCALE:
 682                 *val = info->vref_uv / 1000;
 683                 *val2 = info->adc_feature.res_mode;
 684                 return IIO_VAL_FRACTIONAL_LOG2;
 685
 686         case IIO_CHAN_INFO_SAMP_FREQ:
 687                 *val = info->sample_freq_avail[info->adc_feature.sample_rate];
 688                 *val2 = 0;
 689                 return IIO_VAL_INT;
 690
 691         default:
 692                 break;
 693         }
 694
 695         return -EINVAL;
 696 }
 697
 698 static int vf610_write_raw(struct iio_dev *indio_dev,
 699                         struct iio_chan_spec const *chan,
 700                         int val,
 701                         int val2,
 702                         long mask)
 703 {
 704         struct vf610_adc *info = iio_priv(indio_dev);
 705         int i;
 706
 707         switch (mask) {
 708         case IIO_CHAN_INFO_SAMP_FREQ:
 709                 for (i = 0;
 710                         i < ARRAY_SIZE(info->sample_freq_avail);
 711                         i++)
 712                         if (val == info->sample_freq_avail[i]) {
 713                                 info->adc_feature.sample_rate = i;
 714                                 vf610_adc_sample_set(info);
 715                                 return 0;
 716                         }
 717                 break;
 718
 719         default:
 720                 break;
 721         }
 722
 723         return -EINVAL;
 724 }
 725
 726 static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev)
 727 {
 728         struct vf610_adc *info = iio_priv(indio_dev);
 729         unsigned int channel;
 730         int val;
 731
 732         val = readl(info->regs + VF610_REG_ADC_GC);
 733         val |= VF610_ADC_ADCON;
 734         writel(val, info->regs + VF610_REG_ADC_GC);
 735
 736         channel = find_first_bit(indio_dev->active_scan_mask,
 737                                                 indio_dev->masklength);
 738
 739         val = VF610_ADC_ADCHC(channel);
 740         val |= VF610_ADC_AIEN;
 741
 742         writel(val, info->regs + VF610_REG_ADC_HC0);
 743
 744         return 0;
 745 }
 746
 747 static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev)
 748 {
 749         struct vf610_adc *info = iio_priv(indio_dev);
 750         unsigned int hc_cfg = 0;
 751         int val;
 752
 753         val = readl(info->regs + VF610_REG_ADC_GC);
 754         val &= ~VF610_ADC_ADCON;
 755         writel(val, info->regs + VF610_REG_ADC_GC);
 756
 757         hc_cfg |= VF610_ADC_CONV_DISABLE;
 758         hc_cfg &= ~VF610_ADC_AIEN;
 759
 760         writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 761
 762         return 0;
 763 }
 764
 765 static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
 766         .postenable = &vf610_adc_buffer_postenable,
 767         .predisable = &vf610_adc_buffer_predisable,
 768         .validate_scan_mask = &iio_validate_scan_mask_onehot,
 769 };
 770
 771 static int vf610_adc_reg_access(struct iio_dev *indio_dev,
 772                         unsigned reg, unsigned writeval,
 773                         unsigned *readval)
 774 {
 775         struct vf610_adc *info = iio_priv(indio_dev);
 776
 777         if ((readval == NULL) ||
 778                 ((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
 779                 return -EINVAL;
 780
 781         *readval = readl(info->regs + reg);
 782
 783         return 0;
 784 }
 785
 786 static const struct iio_info vf610_adc_iio_info = {
 787         .read_raw = &vf610_read_raw,
 788         .write_raw = &vf610_write_raw,
 789         .debugfs_reg_access = &vf610_adc_reg_access,
 790         .attrs = &vf610_attribute_group,
 791 };
 792
 793 static const struct of_device_id vf610_adc_match[] = {
 794         { .compatible = "fsl,vf610-adc", },
 795         { /* sentinel */ }
 796 };
 797 MODULE_DEVICE_TABLE(of, vf610_adc_match);
 798
 799 static int vf610_adc_probe(struct platform_device *pdev)
 800 {
 801         struct device *dev = &pdev->dev;
 802         struct vf610_adc *info;
 803         struct iio_dev *indio_dev;
 804         int irq;
 805         int ret;
 806
 807         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
 808         if (!indio_dev) {
 809                 dev_err(&pdev->dev, "Failed allocating iio device\n");
 810                 return -ENOMEM;
 811         }
 812
 813         info = iio_priv(indio_dev);
 814         info->dev = &pdev->dev;
 815
 816         info->regs = devm_platform_ioremap_resource(pdev, 0);
 817         if (IS_ERR(info->regs))
 818                 return PTR_ERR(info->regs);
 819
 820         irq = platform_get_irq(pdev, 0);
 821         if (irq < 0)
 822                 return irq;
 823
 824         ret = devm_request_irq(info->dev, irq,
 825                                 vf610_adc_isr, 0,
 826                                 dev_name(&pdev->dev), indio_dev);
 827         if (ret < 0) {
 828                 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
 829                 return ret;
 830         }
 831
 832         info->clk = devm_clk_get(&pdev->dev, "adc");
 833         if (IS_ERR(info->clk)) {
 834                 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
 835                                                 PTR_ERR(info->clk));
 836                 return PTR_ERR(info->clk);
 837         }
 838
 839         info->vref = devm_regulator_get(&pdev->dev, "vref");
 840         if (IS_ERR(info->vref))
 841                 return PTR_ERR(info->vref);
 842
 843         ret = regulator_enable(info->vref);
 844         if (ret)
 845                 return ret;
 846
 847         info->vref_uv = regulator_get_voltage(info->vref);
 848
 849         device_property_read_u32_array(dev, "fsl,adck-max-frequency", info->max_adck_rate, 3);
 850
 851         info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME;
 852         device_property_read_u32(dev, "min-sample-time", &info->adc_feature.default_sample_time);
 853
 854         platform_set_drvdata(pdev, indio_dev);
 855
 856         init_completion(&info->completion);
 857
 858         indio_dev->name = dev_name(&pdev->dev);
 859         indio_dev->info = &vf610_adc_iio_info;
 860         indio_dev->modes = INDIO_DIRECT_MODE;
 861         indio_dev->channels = vf610_adc_iio_channels;
 862         indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
 863
 864         ret = clk_prepare_enable(info->clk);
 865         if (ret) {
 866                 dev_err(&pdev->dev,
 867                         "Could not prepare or enable the clock.\n");
 868                 goto error_adc_clk_enable;
 869         }
 870
 871         vf610_adc_cfg_init(info);
 872         vf610_adc_hw_init(info);
 873
 874         ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
 875                                         NULL, &iio_triggered_buffer_setup_ops);
 876         if (ret < 0) {
 877                 dev_err(&pdev->dev, "Couldn't initialise the buffer\n");
 878                 goto error_iio_device_register;
 879         }
 880
 881         ret = iio_device_register(indio_dev);
 882         if (ret) {
 883                 dev_err(&pdev->dev, "Couldn't register the device.\n");
 884                 goto error_adc_buffer_init;
 885         }
 886
 887         return 0;
 888
 889 error_adc_buffer_init:
 890         iio_triggered_buffer_cleanup(indio_dev);
 891 error_iio_device_register:
 892         clk_disable_unprepare(info->clk);
 893 error_adc_clk_enable:
 894         regulator_disable(info->vref);
 895
 896         return ret;
 897 }
 898
 899 static int vf610_adc_remove(struct platform_device *pdev)
 900 {
 901         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 902         struct vf610_adc *info = iio_priv(indio_dev);
 903
 904         iio_device_unregister(indio_dev);
 905         iio_triggered_buffer_cleanup(indio_dev);
 906         regulator_disable(info->vref);
 907         clk_disable_unprepare(info->clk);
 908
 909         return 0;
 910 }
 911
 912 static int vf610_adc_suspend(struct device *dev)
 913 {
 914         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 915         struct vf610_adc *info = iio_priv(indio_dev);
 916         int hc_cfg;
 917
 918         /* ADC controller enters to stop mode */
 919         hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
 920         hc_cfg |= VF610_ADC_CONV_DISABLE;
 921         writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
 922
 923         clk_disable_unprepare(info->clk);
 924         regulator_disable(info->vref);
 925
 926         return 0;
 927 }
 928
 929 static int vf610_adc_resume(struct device *dev)
 930 {
 931         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 932         struct vf610_adc *info = iio_priv(indio_dev);
 933         int ret;
 934
 935         ret = regulator_enable(info->vref);
 936         if (ret)
 937                 return ret;
 938
 939         ret = clk_prepare_enable(info->clk);
 940         if (ret)
 941                 goto disable_reg;
 942
 943         vf610_adc_hw_init(info);
 944
 945         return 0;
 946
 947 disable_reg:
 948         regulator_disable(info->vref);
 949         return ret;
 950 }
 951
 952 static DEFINE_SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend,
 953                                 vf610_adc_resume);
 954
 955 static struct platform_driver vf610_adc_driver = {
 956         .probe          = vf610_adc_probe,
 957         .remove         = vf610_adc_remove,
 958         .driver         = {
 959                 .name   = DRIVER_NAME,
 960                 .of_match_table = vf610_adc_match,
 961                 .pm     = pm_sleep_ptr(&vf610_adc_pm_ops),
 962         },
 963 };
 964
 965 module_platform_driver(vf610_adc_driver);
 966
 967 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
 968 MODULE_DESCRIPTION("Freescale VF610 ADC driver");
 969 MODULE_LICENSE("GPL v2");