1 // SPDX-License-Identifier: GPL-2.0
3 * Texas Instruments TSC2046 SPI ADC driver
5 * Copyright (c) 2021 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
8 #include <linux/bitfield.h>
9 #include <linux/delay.h>
10 #include <linux/module.h>
11 #include <linux/spi/spi.h>
13 #include <asm/unaligned.h>
15 #include <linux/iio/buffer.h>
16 #include <linux/iio/trigger_consumer.h>
17 #include <linux/iio/triggered_buffer.h>
18 #include <linux/iio/trigger.h>
21 * The PENIRQ of TSC2046 controller is implemented as level shifter attached to
22 * the X+ line. If voltage of the X+ line reaches a specific level the IRQ will
23 * be activated or deactivated.
24 * To make this kind of IRQ reusable as trigger following additions were
27 * For typical touchscreen use case, we need to trigger about each 10ms.
29 * Continue triggering at least once after the IRQ was deactivated. Then
30 * deactivate this trigger to stop sampling in order to reduce power
34 #define TI_TSC2046_NAME "tsc2046"
36 /* This driver doesn't aim at the peak continuous sample rate */
37 #define TI_TSC2046_MAX_SAMPLE_RATE 125000
38 #define TI_TSC2046_SAMPLE_BITS \
39 BITS_PER_TYPE(struct tsc2046_adc_atom)
40 #define TI_TSC2046_MAX_CLK_FREQ \
41 (TI_TSC2046_MAX_SAMPLE_RATE * TI_TSC2046_SAMPLE_BITS)
43 #define TI_TSC2046_SAMPLE_INTERVAL_US 10000
45 #define TI_TSC2046_START BIT(7)
46 #define TI_TSC2046_ADDR GENMASK(6, 4)
47 #define TI_TSC2046_ADDR_TEMP1 7
48 #define TI_TSC2046_ADDR_AUX 6
49 #define TI_TSC2046_ADDR_X 5
50 #define TI_TSC2046_ADDR_Z2 4
51 #define TI_TSC2046_ADDR_Z1 3
52 #define TI_TSC2046_ADDR_VBAT 2
53 #define TI_TSC2046_ADDR_Y 1
54 #define TI_TSC2046_ADDR_TEMP0 0
57 * The mode bit sets the resolution of the ADC. With this bit low, the next
58 * conversion has 12-bit resolution, whereas with this bit high, the next
59 * conversion has 8-bit resolution. This driver is optimized for 12-bit mode.
60 * So, for this driver, this bit should stay zero.
62 #define TI_TSC2046_8BIT_MODE BIT(3)
65 * SER/DFR - The SER/DFR bit controls the reference mode, either single-ended
66 * (high) or differential (low).
68 #define TI_TSC2046_SER BIT(2)
71 * If VREF_ON and ADC_ON are both zero, then the chip operates in
72 * auto-wake/suspend mode. In most case this bits should stay zero.
74 #define TI_TSC2046_PD1_VREF_ON BIT(1)
75 #define TI_TSC2046_PD0_ADC_ON BIT(0)
78 * All supported devices can do 8 or 12bit resolution. This driver
79 * supports only 12bit mode, here we have a 16bit data transfer, where
80 * the MSB and the 3 LSB are 0.
82 #define TI_TSC2046_DATA_12BIT GENMASK(14, 3)
84 #define TI_TSC2046_MAX_CHAN 8
86 /* Represents a HW sample */
87 struct tsc2046_adc_atom {
89 * Command transmitted to the controller. This field is empty on the RX
94 * Data received from the controller. This field is empty for the TX
100 /* Layout of atomic buffers within big buffer */
101 struct tsc2046_adc_group_layout {
102 /* Group offset within the SPI RX buffer */
105 * Amount of tsc2046_adc_atom structs within the same command gathered
110 * Settling samples (tsc2046_adc_atom structs) which should be skipped
111 * before good samples will start.
116 struct tsc2046_adc_dcfg {
117 const struct iio_chan_spec *channels;
118 unsigned int num_channels;
121 struct tsc2046_adc_ch_cfg {
122 unsigned int settling_time_us;
123 unsigned int oversampling_ratio;
126 struct tsc2046_adc_priv {
127 struct spi_device *spi;
128 const struct tsc2046_adc_dcfg *dcfg;
130 struct iio_trigger *trig;
131 struct hrtimer trig_timer;
132 spinlock_t trig_lock;
133 unsigned int trig_more_count;
135 struct spi_transfer xfer;
136 struct spi_message msg;
139 /* Scan data for each channel */
140 u16 data[TI_TSC2046_MAX_CHAN];
146 * Lock to protect the layout and the SPI transfer buffer.
147 * tsc2046_adc_group_layout can be changed within update_scan_mode(),
148 * in this case the l[] and tx/rx buffer will be out of sync to each
152 struct tsc2046_adc_group_layout l[TI_TSC2046_MAX_CHAN];
153 struct tsc2046_adc_atom *rx;
154 struct tsc2046_adc_atom *tx;
156 struct tsc2046_adc_atom *rx_one;
157 struct tsc2046_adc_atom *tx_one;
161 u32 effective_speed_hz;
162 u32 scan_interval_us;
163 u32 time_per_scan_us;
166 struct tsc2046_adc_ch_cfg ch_cfg[TI_TSC2046_MAX_CHAN];
169 #define TI_TSC2046_V_CHAN(index, bits, name) \
171 .type = IIO_VOLTAGE, \
174 .datasheet_name = "#name", \
175 .scan_index = index, \
180 .endianness = IIO_CPU, \
184 #define DECLARE_TI_TSC2046_8_CHANNELS(name, bits) \
185 const struct iio_chan_spec name ## _channels[] = { \
186 TI_TSC2046_V_CHAN(0, bits, TEMP0), \
187 TI_TSC2046_V_CHAN(1, bits, Y), \
188 TI_TSC2046_V_CHAN(2, bits, VBAT), \
189 TI_TSC2046_V_CHAN(3, bits, Z1), \
190 TI_TSC2046_V_CHAN(4, bits, Z2), \
191 TI_TSC2046_V_CHAN(5, bits, X), \
192 TI_TSC2046_V_CHAN(6, bits, AUX), \
193 TI_TSC2046_V_CHAN(7, bits, TEMP1), \
194 IIO_CHAN_SOFT_TIMESTAMP(8), \
197 static DECLARE_TI_TSC2046_8_CHANNELS(tsc2046_adc, 12);
199 static const struct tsc2046_adc_dcfg tsc2046_adc_dcfg_tsc2046e = {
200 .channels = tsc2046_adc_channels,
201 .num_channels = ARRAY_SIZE(tsc2046_adc_channels),
205 * Convert time to a number of samples which can be transferred within this
208 static unsigned int tsc2046_adc_time_to_count(struct tsc2046_adc_priv *priv,
211 unsigned int bit_count, sample_count;
213 bit_count = DIV_ROUND_UP(time * NSEC_PER_USEC, priv->time_per_bit_ns);
214 sample_count = DIV_ROUND_UP(bit_count, TI_TSC2046_SAMPLE_BITS);
216 dev_dbg(&priv->spi->dev, "Effective speed %u, time per bit: %u, count bits: %u, count samples: %u\n",
217 priv->effective_speed_hz, priv->time_per_bit_ns,
218 bit_count, sample_count);
223 static u8 tsc2046_adc_get_cmd(struct tsc2046_adc_priv *priv, int ch_idx,
229 * if PD bits are 0, controller will automatically disable ADC, VREF and
233 pd = TI_TSC2046_PD0_ADC_ON;
237 return TI_TSC2046_START | FIELD_PREP(TI_TSC2046_ADDR, ch_idx) | pd;
240 static u16 tsc2046_adc_get_value(struct tsc2046_adc_atom *buf)
242 return FIELD_GET(TI_TSC2046_DATA_12BIT, get_unaligned_be16(&buf->data));
245 static int tsc2046_adc_read_one(struct tsc2046_adc_priv *priv, int ch_idx,
246 u32 *effective_speed_hz)
248 struct spi_transfer xfer;
249 struct spi_message msg;
252 memset(&xfer, 0, sizeof(xfer));
253 priv->tx_one->cmd = tsc2046_adc_get_cmd(priv, ch_idx, false);
254 priv->tx_one->data = 0;
255 xfer.tx_buf = priv->tx_one;
256 xfer.rx_buf = priv->rx_one;
257 xfer.len = sizeof(*priv->tx_one);
258 spi_message_init_with_transfers(&msg, &xfer, 1);
261 * We aren't using spi_write_then_read() because we need to be able
262 * to get hold of the effective_speed_hz from the xfer
264 ret = spi_sync(priv->spi, &msg);
266 dev_err_ratelimited(&priv->spi->dev, "SPI transfer failed %pe\n",
271 if (effective_speed_hz)
272 *effective_speed_hz = xfer.effective_speed_hz;
274 return tsc2046_adc_get_value(priv->rx_one);
277 static size_t tsc2046_adc_group_set_layout(struct tsc2046_adc_priv *priv,
281 struct tsc2046_adc_ch_cfg *ch = &priv->ch_cfg[ch_idx];
282 struct tsc2046_adc_group_layout *cur;
283 unsigned int max_count, count_skip;
284 unsigned int offset = 0;
287 offset = priv->l[group - 1].offset + priv->l[group - 1].count;
289 count_skip = tsc2046_adc_time_to_count(priv, ch->settling_time_us);
290 max_count = count_skip + ch->oversampling_ratio;
292 cur = &priv->l[group];
293 cur->offset = offset;
294 cur->count = max_count;
295 cur->skip = count_skip;
297 return sizeof(*priv->tx) * max_count;
300 static void tsc2046_adc_group_set_cmd(struct tsc2046_adc_priv *priv,
301 unsigned int group, int ch_idx)
303 struct tsc2046_adc_group_layout *l = &priv->l[group];
308 * Do not enable automatic power down on working samples. Otherwise the
309 * plates will never be completely charged.
311 cmd = tsc2046_adc_get_cmd(priv, ch_idx, true);
313 for (i = 0; i < l->count - 1; i++)
314 priv->tx[l->offset + i].cmd = cmd;
316 /* automatically power down on last sample */
317 priv->tx[l->offset + i].cmd = tsc2046_adc_get_cmd(priv, ch_idx, false);
320 static u16 tsc2046_adc_get_val(struct tsc2046_adc_priv *priv, int group)
322 struct tsc2046_adc_group_layout *l;
323 unsigned int val, val_normalized = 0;
327 valid_count = l->count - l->skip;
329 for (i = 0; i < valid_count; i++) {
330 val = tsc2046_adc_get_value(&priv->rx[l->offset + l->skip + i]);
331 val_normalized += val;
334 return DIV_ROUND_UP(val_normalized, valid_count);
337 static int tsc2046_adc_scan(struct iio_dev *indio_dev)
339 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
340 struct device *dev = &priv->spi->dev;
344 ret = spi_sync(priv->spi, &priv->msg);
346 dev_err_ratelimited(dev, "SPI transfer failed: %pe\n", ERR_PTR(ret));
350 for (group = 0; group < priv->groups; group++)
351 priv->scan_buf.data[group] = tsc2046_adc_get_val(priv, group);
353 ret = iio_push_to_buffers_with_timestamp(indio_dev, &priv->scan_buf,
354 iio_get_time_ns(indio_dev));
355 /* If the consumer is kfifo, we may get a EBUSY here - ignore it. */
356 if (ret < 0 && ret != -EBUSY) {
357 dev_err_ratelimited(dev, "Failed to push scan buffer %pe\n",
366 static irqreturn_t tsc2046_adc_trigger_handler(int irq, void *p)
368 struct iio_poll_func *pf = p;
369 struct iio_dev *indio_dev = pf->indio_dev;
370 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
372 mutex_lock(&priv->slock);
373 tsc2046_adc_scan(indio_dev);
374 mutex_unlock(&priv->slock);
376 iio_trigger_notify_done(indio_dev->trig);
381 static int tsc2046_adc_update_scan_mode(struct iio_dev *indio_dev,
382 const unsigned long *active_scan_mask)
384 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
385 unsigned int ch_idx, group = 0;
388 mutex_lock(&priv->slock);
391 for_each_set_bit(ch_idx, active_scan_mask, ARRAY_SIZE(priv->l)) {
392 size += tsc2046_adc_group_set_layout(priv, group, ch_idx);
393 tsc2046_adc_group_set_cmd(priv, group, ch_idx);
397 priv->groups = group;
398 priv->xfer.len = size;
399 priv->time_per_scan_us = size * 8 * priv->time_per_bit_ns / NSEC_PER_USEC;
401 if (priv->scan_interval_us < priv->time_per_scan_us)
402 dev_warn(&priv->spi->dev, "The scan interval (%d) is less then calculated scan time (%d)\n",
403 priv->scan_interval_us, priv->time_per_scan_us);
405 mutex_unlock(&priv->slock);
410 static const struct iio_info tsc2046_adc_info = {
411 .update_scan_mode = tsc2046_adc_update_scan_mode,
414 static enum hrtimer_restart tsc2046_adc_trig_more(struct hrtimer *hrtimer)
416 struct tsc2046_adc_priv *priv = container_of(hrtimer,
417 struct tsc2046_adc_priv,
421 spin_lock_irqsave(&priv->trig_lock, flags);
423 disable_irq_nosync(priv->spi->irq);
425 priv->trig_more_count++;
426 iio_trigger_poll(priv->trig);
428 spin_unlock_irqrestore(&priv->trig_lock, flags);
430 return HRTIMER_NORESTART;
433 static irqreturn_t tsc2046_adc_irq(int irq, void *dev_id)
435 struct iio_dev *indio_dev = dev_id;
436 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
438 spin_lock(&priv->trig_lock);
440 hrtimer_try_to_cancel(&priv->trig_timer);
442 priv->trig_more_count = 0;
443 disable_irq_nosync(priv->spi->irq);
444 iio_trigger_poll(priv->trig);
446 spin_unlock(&priv->trig_lock);
451 static void tsc2046_adc_reenable_trigger(struct iio_trigger *trig)
453 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
454 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
459 * We can sample it as fast as we can, but usually we do not need so
460 * many samples. Reduce the sample rate for default (touchscreen) use
462 * Currently we do not need a highly precise sample rate. It is enough
463 * to have calculated numbers.
465 delta = priv->scan_interval_us - priv->time_per_scan_us;
469 spin_lock_irqsave(&priv->trig_lock, flags);
472 * We need to trigger at least one extra sample to detect state
473 * difference on ADC side.
475 if (!priv->trig_more_count) {
476 int timeout_ms = DIV_ROUND_UP(priv->scan_interval_us,
479 hrtimer_start(&priv->trig_timer, ms_to_ktime(timeout_ms),
480 HRTIMER_MODE_REL_SOFT);
483 enable_irq(priv->spi->irq);
485 spin_unlock_irqrestore(&priv->trig_lock, flags);
488 static int tsc2046_adc_set_trigger_state(struct iio_trigger *trig, bool enable)
490 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
491 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
494 enable_irq(priv->spi->irq);
496 disable_irq(priv->spi->irq);
497 hrtimer_try_to_cancel(&priv->trig_timer);
503 static const struct iio_trigger_ops tsc2046_adc_trigger_ops = {
504 .set_trigger_state = tsc2046_adc_set_trigger_state,
505 .reenable = tsc2046_adc_reenable_trigger,
508 static int tsc2046_adc_setup_spi_msg(struct tsc2046_adc_priv *priv)
514 priv->tx_one = devm_kzalloc(&priv->spi->dev, sizeof(*priv->tx_one),
519 priv->rx_one = devm_kzalloc(&priv->spi->dev, sizeof(*priv->rx_one),
525 * Make dummy read to set initial power state and get real SPI clock
526 * freq. It seems to be not important which channel is used for this
529 ret = tsc2046_adc_read_one(priv, TI_TSC2046_ADDR_TEMP0,
530 &priv->effective_speed_hz);
535 * In case SPI controller do not report effective_speed_hz, use
536 * configure value and hope it will match.
538 if (!priv->effective_speed_hz)
539 priv->effective_speed_hz = priv->spi->max_speed_hz;
542 priv->scan_interval_us = TI_TSC2046_SAMPLE_INTERVAL_US;
543 priv->time_per_bit_ns = DIV_ROUND_UP(NSEC_PER_SEC,
544 priv->effective_speed_hz);
547 * Calculate and allocate maximal size buffer if all channels are
551 for (ch_idx = 0; ch_idx < ARRAY_SIZE(priv->l); ch_idx++)
552 size += tsc2046_adc_group_set_layout(priv, ch_idx, ch_idx);
554 priv->tx = devm_kzalloc(&priv->spi->dev, size, GFP_KERNEL);
558 priv->rx = devm_kzalloc(&priv->spi->dev, size, GFP_KERNEL);
562 priv->xfer.tx_buf = priv->tx;
563 priv->xfer.rx_buf = priv->rx;
564 priv->xfer.len = size;
565 spi_message_init_with_transfers(&priv->msg, &priv->xfer, 1);
570 static void tsc2046_adc_parse_fwnode(struct tsc2046_adc_priv *priv)
572 struct fwnode_handle *child;
573 struct device *dev = &priv->spi->dev;
576 for (i = 0; i < ARRAY_SIZE(priv->ch_cfg); i++) {
577 priv->ch_cfg[i].settling_time_us = 1;
578 priv->ch_cfg[i].oversampling_ratio = 1;
581 device_for_each_child_node(dev, child) {
585 ret = fwnode_property_read_u32(child, "reg", ®);
587 dev_err(dev, "invalid reg on %pfw, err: %pe\n", child,
592 if (reg >= ARRAY_SIZE(priv->ch_cfg)) {
593 dev_err(dev, "%pfw: Unsupported reg value: %i, max supported is: %zu.\n",
594 child, reg, ARRAY_SIZE(priv->ch_cfg));
598 ret = fwnode_property_read_u32(child, "settling-time-us", &stl);
600 priv->ch_cfg[reg].settling_time_us = stl;
602 ret = fwnode_property_read_u32(child, "oversampling-ratio",
605 priv->ch_cfg[reg].oversampling_ratio = overs;
609 static int tsc2046_adc_probe(struct spi_device *spi)
611 const struct tsc2046_adc_dcfg *dcfg;
612 struct device *dev = &spi->dev;
613 struct tsc2046_adc_priv *priv;
614 struct iio_dev *indio_dev;
615 struct iio_trigger *trig;
618 if (spi->max_speed_hz > TI_TSC2046_MAX_CLK_FREQ) {
619 dev_err(dev, "SPI max_speed_hz is too high: %d Hz. Max supported freq is %zu Hz\n",
620 spi->max_speed_hz, TI_TSC2046_MAX_CLK_FREQ);
624 dcfg = device_get_match_data(dev);
628 spi->bits_per_word = 8;
629 spi->mode &= ~SPI_MODE_X_MASK;
630 spi->mode |= SPI_MODE_0;
631 ret = spi_setup(spi);
633 return dev_err_probe(dev, ret, "Error in SPI setup\n");
635 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
639 priv = iio_priv(indio_dev);
644 indio_dev->name = TI_TSC2046_NAME;
645 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED;
646 indio_dev->channels = dcfg->channels;
647 indio_dev->num_channels = dcfg->num_channels;
648 indio_dev->info = &tsc2046_adc_info;
650 tsc2046_adc_parse_fwnode(priv);
652 ret = tsc2046_adc_setup_spi_msg(priv);
656 mutex_init(&priv->slock);
658 ret = devm_request_irq(dev, spi->irq, &tsc2046_adc_irq,
659 IRQF_NO_AUTOEN, indio_dev->name, indio_dev);
663 trig = devm_iio_trigger_alloc(dev, "touchscreen-%s", indio_dev->name);
668 iio_trigger_set_drvdata(trig, indio_dev);
669 trig->ops = &tsc2046_adc_trigger_ops;
671 spin_lock_init(&priv->trig_lock);
672 hrtimer_init(&priv->trig_timer, CLOCK_MONOTONIC,
673 HRTIMER_MODE_REL_SOFT);
674 priv->trig_timer.function = tsc2046_adc_trig_more;
676 ret = devm_iio_trigger_register(dev, trig);
678 dev_err(dev, "failed to register trigger\n");
682 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
683 &tsc2046_adc_trigger_handler, NULL);
685 dev_err(dev, "Failed to setup triggered buffer\n");
689 /* set default trigger */
690 indio_dev->trig = iio_trigger_get(priv->trig);
692 return devm_iio_device_register(dev, indio_dev);
695 static const struct of_device_id ads7950_of_table[] = {
696 { .compatible = "ti,tsc2046e-adc", .data = &tsc2046_adc_dcfg_tsc2046e },
699 MODULE_DEVICE_TABLE(of, ads7950_of_table);
701 static struct spi_driver tsc2046_adc_driver = {
704 .of_match_table = ads7950_of_table,
706 .probe = tsc2046_adc_probe,
708 module_spi_driver(tsc2046_adc_driver);
710 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
711 MODULE_DESCRIPTION("TI TSC2046 ADC");
712 MODULE_LICENSE("GPL v2");