drivers/iio/adc/ti-ads7950.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Texas Instruments ADS7950 SPI ADC driver
   4  *
   5  * Copyright 2016 David Lechner <david@lechnology.com>
   6  *
   7  * Based on iio/ad7923.c:
   8  * Copyright 2011 Analog Devices Inc
   9  * Copyright 2012 CS Systemes d'Information
  10  *
  11  * And also on hwmon/ads79xx.c
  12  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
  13  *      Nishanth Menon
  14  */
  15
  16 #include <linux/acpi.h>
  17 #include <linux/bitops.h>
  18 #include <linux/device.h>
  19 #include <linux/err.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/slab.h>
  25 #include <linux/spi/spi.h>
  26
  27 #include <linux/iio/buffer.h>
  28 #include <linux/iio/iio.h>
  29 #include <linux/iio/sysfs.h>
  30 #include <linux/iio/trigger_consumer.h>
  31 #include <linux/iio/triggered_buffer.h>
  32
  33 /*
  34  * In case of ACPI, we use the 5000 mV as default for the reference pin.
  35  * Device tree users encode that via the vref-supply regulator.
  36  */
  37 #define TI_ADS7950_VA_MV_ACPI_DEFAULT   5000
  38
  39 #define TI_ADS7950_CR_MANUAL    BIT(12)
  40 #define TI_ADS7950_CR_WRITE     BIT(11)
  41 #define TI_ADS7950_CR_CHAN(ch)  ((ch) << 7)
  42 #define TI_ADS7950_CR_RANGE_5V  BIT(6)
  43
  44 #define TI_ADS7950_MAX_CHAN     16
  45
  46 #define TI_ADS7950_TIMESTAMP_SIZE (sizeof(int64_t) / sizeof(__be16))
  47
  48 /* val = value, dec = left shift, bits = number of bits of the mask */
  49 #define TI_ADS7950_EXTRACT(val, dec, bits) \
  50         (((val) >> (dec)) & ((1 << (bits)) - 1))
  51
  52 struct ti_ads7950_state {
  53         struct spi_device       *spi;
  54         struct spi_transfer     ring_xfer;
  55         struct spi_transfer     scan_single_xfer[3];
  56         struct spi_message      ring_msg;
  57         struct spi_message      scan_single_msg;
  58
  59         struct regulator        *reg;
  60         unsigned int            vref_mv;
  61
  62         unsigned int            settings;
  63
  64         /*
  65          * DMA (thus cache coherency maintenance) requires the
  66          * transfer buffers to live in their own cache lines.
  67          */
  68         u16 rx_buf[TI_ADS7950_MAX_CHAN + 2 + TI_ADS7950_TIMESTAMP_SIZE]
  69                                                         ____cacheline_aligned;
  70         u16 tx_buf[TI_ADS7950_MAX_CHAN + 2];
  71         u16 single_tx;
  72         u16 single_rx;
  73
  74 };
  75
  76 struct ti_ads7950_chip_info {
  77         const struct iio_chan_spec *channels;
  78         unsigned int num_channels;
  79 };
  80
  81 enum ti_ads7950_id {
  82         TI_ADS7950,
  83         TI_ADS7951,
  84         TI_ADS7952,
  85         TI_ADS7953,
  86         TI_ADS7954,
  87         TI_ADS7955,
  88         TI_ADS7956,
  89         TI_ADS7957,
  90         TI_ADS7958,
  91         TI_ADS7959,
  92         TI_ADS7960,
  93         TI_ADS7961,
  94 };
  95
  96 #define TI_ADS7950_V_CHAN(index, bits)                          \
  97 {                                                               \
  98         .type = IIO_VOLTAGE,                                    \
  99         .indexed = 1,                                           \
 100         .channel = index,                                       \
 101         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 102         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 103         .address = index,                                       \
 104         .datasheet_name = "CH##index",                          \
 105         .scan_index = index,                                    \
 106         .scan_type = {                                          \
 107                 .sign = 'u',                                    \
 108                 .realbits = bits,                               \
 109                 .storagebits = 16,                              \
 110                 .shift = 12 - (bits),                           \
 111                 .endianness = IIO_CPU,                          \
 112         },                                                      \
 113 }
 114
 115 #define DECLARE_TI_ADS7950_4_CHANNELS(name, bits) \
 116 const struct iio_chan_spec name ## _channels[] = { \
 117         TI_ADS7950_V_CHAN(0, bits), \
 118         TI_ADS7950_V_CHAN(1, bits), \
 119         TI_ADS7950_V_CHAN(2, bits), \
 120         TI_ADS7950_V_CHAN(3, bits), \
 121         IIO_CHAN_SOFT_TIMESTAMP(4), \
 122 }
 123
 124 #define DECLARE_TI_ADS7950_8_CHANNELS(name, bits) \
 125 const struct iio_chan_spec name ## _channels[] = { \
 126         TI_ADS7950_V_CHAN(0, bits), \
 127         TI_ADS7950_V_CHAN(1, bits), \
 128         TI_ADS7950_V_CHAN(2, bits), \
 129         TI_ADS7950_V_CHAN(3, bits), \
 130         TI_ADS7950_V_CHAN(4, bits), \
 131         TI_ADS7950_V_CHAN(5, bits), \
 132         TI_ADS7950_V_CHAN(6, bits), \
 133         TI_ADS7950_V_CHAN(7, bits), \
 134         IIO_CHAN_SOFT_TIMESTAMP(8), \
 135 }
 136
 137 #define DECLARE_TI_ADS7950_12_CHANNELS(name, bits) \
 138 const struct iio_chan_spec name ## _channels[] = { \
 139         TI_ADS7950_V_CHAN(0, bits), \
 140         TI_ADS7950_V_CHAN(1, bits), \
 141         TI_ADS7950_V_CHAN(2, bits), \
 142         TI_ADS7950_V_CHAN(3, bits), \
 143         TI_ADS7950_V_CHAN(4, bits), \
 144         TI_ADS7950_V_CHAN(5, bits), \
 145         TI_ADS7950_V_CHAN(6, bits), \
 146         TI_ADS7950_V_CHAN(7, bits), \
 147         TI_ADS7950_V_CHAN(8, bits), \
 148         TI_ADS7950_V_CHAN(9, bits), \
 149         TI_ADS7950_V_CHAN(10, bits), \
 150         TI_ADS7950_V_CHAN(11, bits), \
 151         IIO_CHAN_SOFT_TIMESTAMP(12), \
 152 }
 153
 154 #define DECLARE_TI_ADS7950_16_CHANNELS(name, bits) \
 155 const struct iio_chan_spec name ## _channels[] = { \
 156         TI_ADS7950_V_CHAN(0, bits), \
 157         TI_ADS7950_V_CHAN(1, bits), \
 158         TI_ADS7950_V_CHAN(2, bits), \
 159         TI_ADS7950_V_CHAN(3, bits), \
 160         TI_ADS7950_V_CHAN(4, bits), \
 161         TI_ADS7950_V_CHAN(5, bits), \
 162         TI_ADS7950_V_CHAN(6, bits), \
 163         TI_ADS7950_V_CHAN(7, bits), \
 164         TI_ADS7950_V_CHAN(8, bits), \
 165         TI_ADS7950_V_CHAN(9, bits), \
 166         TI_ADS7950_V_CHAN(10, bits), \
 167         TI_ADS7950_V_CHAN(11, bits), \
 168         TI_ADS7950_V_CHAN(12, bits), \
 169         TI_ADS7950_V_CHAN(13, bits), \
 170         TI_ADS7950_V_CHAN(14, bits), \
 171         TI_ADS7950_V_CHAN(15, bits), \
 172         IIO_CHAN_SOFT_TIMESTAMP(16), \
 173 }
 174
 175 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7950, 12);
 176 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7951, 12);
 177 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7952, 12);
 178 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7953, 12);
 179 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7954, 10);
 180 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7955, 10);
 181 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7956, 10);
 182 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7957, 10);
 183 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7958, 8);
 184 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7959, 8);
 185 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7960, 8);
 186 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7961, 8);
 187
 188 static const struct ti_ads7950_chip_info ti_ads7950_chip_info[] = {
 189         [TI_ADS7950] = {
 190                 .channels       = ti_ads7950_channels,
 191                 .num_channels   = ARRAY_SIZE(ti_ads7950_channels),
 192         },
 193         [TI_ADS7951] = {
 194                 .channels       = ti_ads7951_channels,
 195                 .num_channels   = ARRAY_SIZE(ti_ads7951_channels),
 196         },
 197         [TI_ADS7952] = {
 198                 .channels       = ti_ads7952_channels,
 199                 .num_channels   = ARRAY_SIZE(ti_ads7952_channels),
 200         },
 201         [TI_ADS7953] = {
 202                 .channels       = ti_ads7953_channels,
 203                 .num_channels   = ARRAY_SIZE(ti_ads7953_channels),
 204         },
 205         [TI_ADS7954] = {
 206                 .channels       = ti_ads7954_channels,
 207                 .num_channels   = ARRAY_SIZE(ti_ads7954_channels),
 208         },
 209         [TI_ADS7955] = {
 210                 .channels       = ti_ads7955_channels,
 211                 .num_channels   = ARRAY_SIZE(ti_ads7955_channels),
 212         },
 213         [TI_ADS7956] = {
 214                 .channels       = ti_ads7956_channels,
 215                 .num_channels   = ARRAY_SIZE(ti_ads7956_channels),
 216         },
 217         [TI_ADS7957] = {
 218                 .channels       = ti_ads7957_channels,
 219                 .num_channels   = ARRAY_SIZE(ti_ads7957_channels),
 220         },
 221         [TI_ADS7958] = {
 222                 .channels       = ti_ads7958_channels,
 223                 .num_channels   = ARRAY_SIZE(ti_ads7958_channels),
 224         },
 225         [TI_ADS7959] = {
 226                 .channels       = ti_ads7959_channels,
 227                 .num_channels   = ARRAY_SIZE(ti_ads7959_channels),
 228         },
 229         [TI_ADS7960] = {
 230                 .channels       = ti_ads7960_channels,
 231                 .num_channels   = ARRAY_SIZE(ti_ads7960_channels),
 232         },
 233         [TI_ADS7961] = {
 234                 .channels       = ti_ads7961_channels,
 235                 .num_channels   = ARRAY_SIZE(ti_ads7961_channels),
 236         },
 237 };
 238
 239 /*
 240  * ti_ads7950_update_scan_mode() setup the spi transfer buffer for the new
 241  * scan mask
 242  */
 243 static int ti_ads7950_update_scan_mode(struct iio_dev *indio_dev,
 244                                        const unsigned long *active_scan_mask)
 245 {
 246         struct ti_ads7950_state *st = iio_priv(indio_dev);
 247         int i, cmd, len;
 248
 249         len = 0;
 250         for_each_set_bit(i, active_scan_mask, indio_dev->num_channels) {
 251                 cmd = TI_ADS7950_CR_WRITE | TI_ADS7950_CR_CHAN(i) | st->settings;
 252                 st->tx_buf[len++] = cmd;
 253         }
 254
 255         /* Data for the 1st channel is not returned until the 3rd transfer */
 256         st->tx_buf[len++] = 0;
 257         st->tx_buf[len++] = 0;
 258
 259         st->ring_xfer.len = len * 2;
 260
 261         return 0;
 262 }
 263
 264 static irqreturn_t ti_ads7950_trigger_handler(int irq, void *p)
 265 {
 266         struct iio_poll_func *pf = p;
 267         struct iio_dev *indio_dev = pf->indio_dev;
 268         struct ti_ads7950_state *st = iio_priv(indio_dev);
 269         int ret;
 270
 271         ret = spi_sync(st->spi, &st->ring_msg);
 272         if (ret < 0)
 273                 goto out;
 274
 275         iio_push_to_buffers_with_timestamp(indio_dev, &st->rx_buf[2],
 276                                            iio_get_time_ns(indio_dev));
 277
 278 out:
 279         iio_trigger_notify_done(indio_dev->trig);
 280
 281         return IRQ_HANDLED;
 282 }
 283
 284 static int ti_ads7950_scan_direct(struct iio_dev *indio_dev, unsigned int ch)
 285 {
 286         struct ti_ads7950_state *st = iio_priv(indio_dev);
 287         int ret, cmd;
 288
 289         mutex_lock(&indio_dev->mlock);
 290
 291         cmd = TI_ADS7950_CR_WRITE | TI_ADS7950_CR_CHAN(ch) | st->settings;
 292         st->single_tx = cmd;
 293
 294         ret = spi_sync(st->spi, &st->scan_single_msg);
 295         if (ret)
 296                 goto out;
 297
 298         ret = st->single_rx;
 299
 300 out:
 301         mutex_unlock(&indio_dev->mlock);
 302
 303         return ret;
 304 }
 305
 306 static int ti_ads7950_get_range(struct ti_ads7950_state *st)
 307 {
 308         int vref;
 309
 310         if (st->vref_mv) {
 311                 vref = st->vref_mv;
 312         } else {
 313                 vref = regulator_get_voltage(st->reg);
 314                 if (vref < 0)
 315                         return vref;
 316
 317                 vref /= 1000;
 318         }
 319
 320         if (st->settings & TI_ADS7950_CR_RANGE_5V)
 321                 vref *= 2;
 322
 323         return vref;
 324 }
 325
 326 static int ti_ads7950_read_raw(struct iio_dev *indio_dev,
 327                                struct iio_chan_spec const *chan,
 328                                int *val, int *val2, long m)
 329 {
 330         struct ti_ads7950_state *st = iio_priv(indio_dev);
 331         int ret;
 332
 333         switch (m) {
 334         case IIO_CHAN_INFO_RAW:
 335                 ret = ti_ads7950_scan_direct(indio_dev, chan->address);
 336                 if (ret < 0)
 337                         return ret;
 338
 339                 if (chan->address != TI_ADS7950_EXTRACT(ret, 12, 4))
 340                         return -EIO;
 341
 342                 *val = TI_ADS7950_EXTRACT(ret, chan->scan_type.shift,
 343                                           chan->scan_type.realbits);
 344
 345                 return IIO_VAL_INT;
 346         case IIO_CHAN_INFO_SCALE:
 347                 ret = ti_ads7950_get_range(st);
 348                 if (ret < 0)
 349                         return ret;
 350
 351                 *val = ret;
 352                 *val2 = (1 << chan->scan_type.realbits) - 1;
 353
 354                 return IIO_VAL_FRACTIONAL;
 355         }
 356
 357         return -EINVAL;
 358 }
 359
 360 static const struct iio_info ti_ads7950_info = {
 361         .read_raw               = &ti_ads7950_read_raw,
 362         .update_scan_mode       = ti_ads7950_update_scan_mode,
 363 };
 364
 365 static int ti_ads7950_probe(struct spi_device *spi)
 366 {
 367         struct ti_ads7950_state *st;
 368         struct iio_dev *indio_dev;
 369         const struct ti_ads7950_chip_info *info;
 370         int ret;
 371
 372         spi->bits_per_word = 16;
 373         spi->mode |= SPI_CS_WORD;
 374         ret = spi_setup(spi);
 375         if (ret < 0) {
 376                 dev_err(&spi->dev, "Error in spi setup\n");
 377                 return ret;
 378         }
 379
 380         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 381         if (!indio_dev)
 382                 return -ENOMEM;
 383
 384         st = iio_priv(indio_dev);
 385
 386         spi_set_drvdata(spi, indio_dev);
 387
 388         st->spi = spi;
 389         st->settings = TI_ADS7950_CR_MANUAL | TI_ADS7950_CR_RANGE_5V;
 390
 391         info = &ti_ads7950_chip_info[spi_get_device_id(spi)->driver_data];
 392
 393         indio_dev->name = spi_get_device_id(spi)->name;
 394         indio_dev->dev.parent = &spi->dev;
 395         indio_dev->modes = INDIO_DIRECT_MODE;
 396         indio_dev->channels = info->channels;
 397         indio_dev->num_channels = info->num_channels;
 398         indio_dev->info = &ti_ads7950_info;
 399
 400         /* build spi ring message */
 401         spi_message_init(&st->ring_msg);
 402
 403         st->ring_xfer.tx_buf = &st->tx_buf[0];
 404         st->ring_xfer.rx_buf = &st->rx_buf[0];
 405         /* len will be set later */
 406         st->ring_xfer.cs_change = true;
 407
 408         spi_message_add_tail(&st->ring_xfer, &st->ring_msg);
 409
 410         /*
 411          * Setup default message. The sample is read at the end of the first
 412          * transfer, then it takes one full cycle to convert the sample and one
 413          * more cycle to send the value. The conversion process is driven by
 414          * the SPI clock, which is why we have 3 transfers. The middle one is
 415          * just dummy data sent while the chip is converting the sample that
 416          * was read at the end of the first transfer.
 417          */
 418
 419         st->scan_single_xfer[0].tx_buf = &st->single_tx;
 420         st->scan_single_xfer[0].len = 2;
 421         st->scan_single_xfer[0].cs_change = 1;
 422         st->scan_single_xfer[1].tx_buf = &st->single_tx;
 423         st->scan_single_xfer[1].len = 2;
 424         st->scan_single_xfer[1].cs_change = 1;
 425         st->scan_single_xfer[2].rx_buf = &st->single_rx;
 426         st->scan_single_xfer[2].len = 2;
 427
 428         spi_message_init_with_transfers(&st->scan_single_msg,
 429                                         st->scan_single_xfer, 3);
 430
 431         /* Use hard coded value for reference voltage in ACPI case */
 432         if (ACPI_COMPANION(&spi->dev))
 433                 st->vref_mv = TI_ADS7950_VA_MV_ACPI_DEFAULT;
 434
 435         st->reg = devm_regulator_get(&spi->dev, "vref");
 436         if (IS_ERR(st->reg)) {
 437                 dev_err(&spi->dev, "Failed get get regulator \"vref\"\n");
 438                 return PTR_ERR(st->reg);
 439         }
 440
 441         ret = regulator_enable(st->reg);
 442         if (ret) {
 443                 dev_err(&spi->dev, "Failed to enable regulator \"vref\"\n");
 444                 return ret;
 445         }
 446
 447         ret = iio_triggered_buffer_setup(indio_dev, NULL,
 448                                          &ti_ads7950_trigger_handler, NULL);
 449         if (ret) {
 450                 dev_err(&spi->dev, "Failed to setup triggered buffer\n");
 451                 goto error_disable_reg;
 452         }
 453
 454         ret = iio_device_register(indio_dev);
 455         if (ret) {
 456                 dev_err(&spi->dev, "Failed to register iio device\n");
 457                 goto error_cleanup_ring;
 458         }
 459
 460         return 0;
 461
 462 error_cleanup_ring:
 463         iio_triggered_buffer_cleanup(indio_dev);
 464 error_disable_reg:
 465         regulator_disable(st->reg);
 466
 467         return ret;
 468 }
 469
 470 static int ti_ads7950_remove(struct spi_device *spi)
 471 {
 472         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 473         struct ti_ads7950_state *st = iio_priv(indio_dev);
 474
 475         iio_device_unregister(indio_dev);
 476         iio_triggered_buffer_cleanup(indio_dev);
 477         regulator_disable(st->reg);
 478
 479         return 0;
 480 }
 481
 482 static const struct spi_device_id ti_ads7950_id[] = {
 483         { "ads7950", TI_ADS7950 },
 484         { "ads7951", TI_ADS7951 },
 485         { "ads7952", TI_ADS7952 },
 486         { "ads7953", TI_ADS7953 },
 487         { "ads7954", TI_ADS7954 },
 488         { "ads7955", TI_ADS7955 },
 489         { "ads7956", TI_ADS7956 },
 490         { "ads7957", TI_ADS7957 },
 491         { "ads7958", TI_ADS7958 },
 492         { "ads7959", TI_ADS7959 },
 493         { "ads7960", TI_ADS7960 },
 494         { "ads7961", TI_ADS7961 },
 495         { }
 496 };
 497 MODULE_DEVICE_TABLE(spi, ti_ads7950_id);
 498
 499 static const struct of_device_id ads7950_of_table[] = {
 500         { .compatible = "ti,ads7950", .data = &ti_ads7950_chip_info[TI_ADS7950] },
 501         { .compatible = "ti,ads7951", .data = &ti_ads7950_chip_info[TI_ADS7951] },
 502         { .compatible = "ti,ads7952", .data = &ti_ads7950_chip_info[TI_ADS7952] },
 503         { .compatible = "ti,ads7953", .data = &ti_ads7950_chip_info[TI_ADS7953] },
 504         { .compatible = "ti,ads7954", .data = &ti_ads7950_chip_info[TI_ADS7954] },
 505         { .compatible = "ti,ads7955", .data = &ti_ads7950_chip_info[TI_ADS7955] },
 506         { .compatible = "ti,ads7956", .data = &ti_ads7950_chip_info[TI_ADS7956] },
 507         { .compatible = "ti,ads7957", .data = &ti_ads7950_chip_info[TI_ADS7957] },
 508         { .compatible = "ti,ads7958", .data = &ti_ads7950_chip_info[TI_ADS7958] },
 509         { .compatible = "ti,ads7959", .data = &ti_ads7950_chip_info[TI_ADS7959] },
 510         { .compatible = "ti,ads7960", .data = &ti_ads7950_chip_info[TI_ADS7960] },
 511         { .compatible = "ti,ads7961", .data = &ti_ads7950_chip_info[TI_ADS7961] },
 512         { },
 513 };
 514 MODULE_DEVICE_TABLE(of, ads7950_of_table);
 515
 516 static struct spi_driver ti_ads7950_driver = {
 517         .driver = {
 518                 .name   = "ads7950",
 519                 .of_match_table = ads7950_of_table,
 520         },
 521         .probe          = ti_ads7950_probe,
 522         .remove         = ti_ads7950_remove,
 523         .id_table       = ti_ads7950_id,
 524 };
 525 module_spi_driver(ti_ads7950_driver);
 526
 527 MODULE_AUTHOR("David Lechner <david@lechnology.com>");
 528 MODULE_DESCRIPTION("TI TI_ADS7950 ADC");
 529 MODULE_LICENSE("GPL v2");