1 // SPDX-License-Identifier: GPL-2.0
3 * This file is part the core part STM32 DFSDM driver
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com> for STMicroelectronics.
10 #include <linux/iio/iio.h>
11 #include <linux/iio/sysfs.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/pinctrl/consumer.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
20 #include "stm32-dfsdm.h"
22 struct stm32_dfsdm_dev_data {
23 unsigned int num_filters;
24 unsigned int num_channels;
25 const struct regmap_config *regmap_cfg;
28 #define STM32H7_DFSDM_NUM_FILTERS 4
29 #define STM32H7_DFSDM_NUM_CHANNELS 8
30 #define STM32MP1_DFSDM_NUM_FILTERS 6
31 #define STM32MP1_DFSDM_NUM_CHANNELS 8
33 static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg)
35 if (reg < DFSDM_FILTER_BASE_ADR)
39 * Mask is done on register to avoid to list registers of all
42 switch (reg & DFSDM_FILTER_REG_MASK) {
43 case DFSDM_CR1(0) & DFSDM_FILTER_REG_MASK:
44 case DFSDM_ISR(0) & DFSDM_FILTER_REG_MASK:
45 case DFSDM_JDATAR(0) & DFSDM_FILTER_REG_MASK:
46 case DFSDM_RDATAR(0) & DFSDM_FILTER_REG_MASK:
53 static const struct regmap_config stm32h7_dfsdm_regmap_cfg = {
56 .reg_stride = sizeof(u32),
57 .max_register = 0x2B8,
58 .volatile_reg = stm32_dfsdm_volatile_reg,
62 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_data = {
63 .num_filters = STM32H7_DFSDM_NUM_FILTERS,
64 .num_channels = STM32H7_DFSDM_NUM_CHANNELS,
65 .regmap_cfg = &stm32h7_dfsdm_regmap_cfg,
68 static const struct regmap_config stm32mp1_dfsdm_regmap_cfg = {
71 .reg_stride = sizeof(u32),
72 .max_register = 0x7fc,
73 .volatile_reg = stm32_dfsdm_volatile_reg,
77 static const struct stm32_dfsdm_dev_data stm32mp1_dfsdm_data = {
78 .num_filters = STM32MP1_DFSDM_NUM_FILTERS,
79 .num_channels = STM32MP1_DFSDM_NUM_CHANNELS,
80 .regmap_cfg = &stm32mp1_dfsdm_regmap_cfg,
84 struct platform_device *pdev; /* platform device */
86 struct stm32_dfsdm dfsdm; /* common data exported for all instances */
88 unsigned int spi_clk_out_div; /* SPI clkout divider value */
89 atomic_t n_active_ch; /* number of current active channels */
91 struct clk *clk; /* DFSDM clock */
92 struct clk *aclk; /* audio clock */
95 static inline struct dfsdm_priv *to_stm32_dfsdm_priv(struct stm32_dfsdm *dfsdm)
97 return container_of(dfsdm, struct dfsdm_priv, dfsdm);
100 static int stm32_dfsdm_clk_prepare_enable(struct stm32_dfsdm *dfsdm)
102 struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
105 ret = clk_prepare_enable(priv->clk);
106 if (ret || !priv->aclk)
109 ret = clk_prepare_enable(priv->aclk);
111 clk_disable_unprepare(priv->clk);
116 static void stm32_dfsdm_clk_disable_unprepare(struct stm32_dfsdm *dfsdm)
118 struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
120 clk_disable_unprepare(priv->aclk);
121 clk_disable_unprepare(priv->clk);
125 * stm32_dfsdm_start_dfsdm - start global dfsdm interface.
127 * Enable interface if n_active_ch is not null.
128 * @dfsdm: Handle used to retrieve dfsdm context.
130 int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm)
132 struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
133 struct device *dev = &priv->pdev->dev;
134 unsigned int clk_div = priv->spi_clk_out_div, clk_src;
137 if (atomic_inc_return(&priv->n_active_ch) == 1) {
138 ret = pm_runtime_resume_and_get(dev);
142 /* select clock source, e.g. 0 for "dfsdm" or 1 for "audio" */
143 clk_src = priv->aclk ? 1 : 0;
144 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
145 DFSDM_CHCFGR1_CKOUTSRC_MASK,
146 DFSDM_CHCFGR1_CKOUTSRC(clk_src));
150 /* Output the SPI CLKOUT (if clk_div == 0 clock if OFF) */
151 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
152 DFSDM_CHCFGR1_CKOUTDIV_MASK,
153 DFSDM_CHCFGR1_CKOUTDIV(clk_div));
157 /* Global enable of DFSDM interface */
158 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
159 DFSDM_CHCFGR1_DFSDMEN_MASK,
160 DFSDM_CHCFGR1_DFSDMEN(1));
165 dev_dbg(dev, "%s: n_active_ch %d\n", __func__,
166 atomic_read(&priv->n_active_ch));
171 pm_runtime_put_sync(dev);
173 atomic_dec(&priv->n_active_ch);
177 EXPORT_SYMBOL_GPL(stm32_dfsdm_start_dfsdm);
180 * stm32_dfsdm_stop_dfsdm - stop global DFSDM interface.
182 * Disable interface if n_active_ch is null
183 * @dfsdm: Handle used to retrieve dfsdm context.
185 int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm)
187 struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
190 if (atomic_dec_and_test(&priv->n_active_ch)) {
191 /* Global disable of DFSDM interface */
192 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
193 DFSDM_CHCFGR1_DFSDMEN_MASK,
194 DFSDM_CHCFGR1_DFSDMEN(0));
198 /* Stop SPI CLKOUT */
199 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
200 DFSDM_CHCFGR1_CKOUTDIV_MASK,
201 DFSDM_CHCFGR1_CKOUTDIV(0));
205 pm_runtime_put_sync(&priv->pdev->dev);
207 dev_dbg(&priv->pdev->dev, "%s: n_active_ch %d\n", __func__,
208 atomic_read(&priv->n_active_ch));
212 EXPORT_SYMBOL_GPL(stm32_dfsdm_stop_dfsdm);
214 static int stm32_dfsdm_parse_of(struct platform_device *pdev,
215 struct dfsdm_priv *priv)
217 struct device_node *node = pdev->dev.of_node;
218 struct resource *res;
219 unsigned long clk_freq, divider;
220 unsigned int spi_freq, rem;
226 priv->dfsdm.base = devm_platform_get_and_ioremap_resource(pdev, 0,
228 if (IS_ERR(priv->dfsdm.base))
229 return PTR_ERR(priv->dfsdm.base);
231 priv->dfsdm.phys_base = res->start;
234 * "dfsdm" clock is mandatory for DFSDM peripheral clocking.
235 * "dfsdm" or "audio" clocks can be used as source clock for
236 * the SPI clock out signal and internal processing, depending
239 priv->clk = devm_clk_get(&pdev->dev, "dfsdm");
240 if (IS_ERR(priv->clk))
241 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk),
242 "Failed to get clock\n");
244 priv->aclk = devm_clk_get(&pdev->dev, "audio");
245 if (IS_ERR(priv->aclk))
249 clk_freq = clk_get_rate(priv->aclk);
251 clk_freq = clk_get_rate(priv->clk);
253 /* SPI clock out frequency */
254 ret = of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
257 /* No SPI master mode */
261 divider = div_u64_rem(clk_freq, spi_freq, &rem);
262 /* Round up divider when ckout isn't precise, not to exceed spi_freq */
266 /* programmable divider is in range of [2:256] */
267 if (divider < 2 || divider > 256) {
268 dev_err(&pdev->dev, "spi-max-frequency not achievable\n");
272 /* SPI clock output divider is: divider = CKOUTDIV + 1 */
273 priv->spi_clk_out_div = divider - 1;
274 priv->dfsdm.spi_master_freq = clk_freq / (priv->spi_clk_out_div + 1);
277 dev_warn(&pdev->dev, "SPI clock not accurate\n");
278 dev_warn(&pdev->dev, "%ld = %d * %d + %d\n",
279 clk_freq, spi_freq, priv->spi_clk_out_div + 1, rem);
285 static const struct of_device_id stm32_dfsdm_of_match[] = {
287 .compatible = "st,stm32h7-dfsdm",
288 .data = &stm32h7_dfsdm_data,
291 .compatible = "st,stm32mp1-dfsdm",
292 .data = &stm32mp1_dfsdm_data,
296 MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match);
298 static int stm32_dfsdm_probe(struct platform_device *pdev)
300 struct dfsdm_priv *priv;
301 const struct stm32_dfsdm_dev_data *dev_data;
302 struct stm32_dfsdm *dfsdm;
305 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
311 dev_data = of_device_get_match_data(&pdev->dev);
313 dfsdm = &priv->dfsdm;
314 dfsdm->fl_list = devm_kcalloc(&pdev->dev, dev_data->num_filters,
315 sizeof(*dfsdm->fl_list), GFP_KERNEL);
319 dfsdm->num_fls = dev_data->num_filters;
320 dfsdm->ch_list = devm_kcalloc(&pdev->dev, dev_data->num_channels,
321 sizeof(*dfsdm->ch_list),
325 dfsdm->num_chs = dev_data->num_channels;
327 ret = stm32_dfsdm_parse_of(pdev, priv);
331 dfsdm->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dfsdm",
333 dev_data->regmap_cfg);
334 if (IS_ERR(dfsdm->regmap)) {
335 ret = PTR_ERR(dfsdm->regmap);
336 dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
341 platform_set_drvdata(pdev, dfsdm);
343 ret = stm32_dfsdm_clk_prepare_enable(dfsdm);
345 dev_err(&pdev->dev, "Failed to start clock\n");
349 pm_runtime_get_noresume(&pdev->dev);
350 pm_runtime_set_active(&pdev->dev);
351 pm_runtime_enable(&pdev->dev);
353 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
357 pm_runtime_put(&pdev->dev);
362 pm_runtime_disable(&pdev->dev);
363 pm_runtime_set_suspended(&pdev->dev);
364 pm_runtime_put_noidle(&pdev->dev);
365 stm32_dfsdm_clk_disable_unprepare(dfsdm);
370 static int stm32_dfsdm_core_remove(struct platform_device *pdev)
372 struct stm32_dfsdm *dfsdm = platform_get_drvdata(pdev);
374 pm_runtime_get_sync(&pdev->dev);
375 of_platform_depopulate(&pdev->dev);
376 pm_runtime_disable(&pdev->dev);
377 pm_runtime_set_suspended(&pdev->dev);
378 pm_runtime_put_noidle(&pdev->dev);
379 stm32_dfsdm_clk_disable_unprepare(dfsdm);
384 static int stm32_dfsdm_core_suspend(struct device *dev)
386 struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
387 struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
390 ret = pm_runtime_force_suspend(dev);
394 /* Balance devm_regmap_init_mmio_clk() clk_prepare() */
395 clk_unprepare(priv->clk);
397 return pinctrl_pm_select_sleep_state(dev);
400 static int stm32_dfsdm_core_resume(struct device *dev)
402 struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
403 struct dfsdm_priv *priv = to_stm32_dfsdm_priv(dfsdm);
406 ret = pinctrl_pm_select_default_state(dev);
410 ret = clk_prepare(priv->clk);
414 return pm_runtime_force_resume(dev);
417 static int stm32_dfsdm_core_runtime_suspend(struct device *dev)
419 struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
421 stm32_dfsdm_clk_disable_unprepare(dfsdm);
426 static int stm32_dfsdm_core_runtime_resume(struct device *dev)
428 struct stm32_dfsdm *dfsdm = dev_get_drvdata(dev);
430 return stm32_dfsdm_clk_prepare_enable(dfsdm);
433 static const struct dev_pm_ops stm32_dfsdm_core_pm_ops = {
434 SYSTEM_SLEEP_PM_OPS(stm32_dfsdm_core_suspend, stm32_dfsdm_core_resume)
435 RUNTIME_PM_OPS(stm32_dfsdm_core_runtime_suspend,
436 stm32_dfsdm_core_runtime_resume,
440 static struct platform_driver stm32_dfsdm_driver = {
441 .probe = stm32_dfsdm_probe,
442 .remove = stm32_dfsdm_core_remove,
444 .name = "stm32-dfsdm",
445 .of_match_table = stm32_dfsdm_of_match,
446 .pm = pm_ptr(&stm32_dfsdm_core_pm_ops),
450 module_platform_driver(stm32_dfsdm_driver);
452 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
453 MODULE_DESCRIPTION("STMicroelectronics STM32 dfsdm driver");
454 MODULE_LICENSE("GPL v2");