drivers/iio/adc/stm32-dfsdm-adc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This file is the ADC part of the STM32 DFSDM driver
   4  *
   5  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   6  * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
   7  */
   8
   9 #include <linux/dmaengine.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/iio/adc/stm32-dfsdm-adc.h>
  12 #include <linux/iio/buffer.h>
  13 #include <linux/iio/hw-consumer.h>
  14 #include <linux/iio/sysfs.h>
  15 #include <linux/iio/timer/stm32-lptim-trigger.h>
  16 #include <linux/iio/timer/stm32-timer-trigger.h>
  17 #include <linux/iio/trigger.h>
  18 #include <linux/iio/trigger_consumer.h>
  19 #include <linux/iio/triggered_buffer.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/of_device.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regmap.h>
  25 #include <linux/slab.h>
  26
  27 #include "stm32-dfsdm.h"
  28
  29 #define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
  30
  31 /* Conversion timeout */
  32 #define DFSDM_TIMEOUT_US 100000
  33 #define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
  34
  35 /* Oversampling attribute default */
  36 #define DFSDM_DEFAULT_OVERSAMPLING  100
  37
  38 /* Oversampling max values */
  39 #define DFSDM_MAX_INT_OVERSAMPLING 256
  40 #define DFSDM_MAX_FL_OVERSAMPLING 1024
  41
  42 /* Max sample resolutions */
  43 #define DFSDM_MAX_RES BIT(31)
  44 #define DFSDM_DATA_RES BIT(23)
  45
  46 /* Filter configuration */
  47 #define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \
  48                             DFSDM_CR1_RSYNC_MASK | DFSDM_CR1_JSYNC_MASK | \
  49                             DFSDM_CR1_JSCAN_MASK)
  50
  51 enum sd_converter_type {
  52         DFSDM_AUDIO,
  53         DFSDM_IIO,
  54 };
  55
  56 struct stm32_dfsdm_dev_data {
  57         int type;
  58         int (*init)(struct iio_dev *indio_dev);
  59         unsigned int num_channels;
  60         const struct regmap_config *regmap_cfg;
  61 };
  62
  63 struct stm32_dfsdm_adc {
  64         struct stm32_dfsdm *dfsdm;
  65         const struct stm32_dfsdm_dev_data *dev_data;
  66         unsigned int fl_id;
  67         unsigned int nconv;
  68         unsigned long smask;
  69
  70         /* ADC specific */
  71         unsigned int oversamp;
  72         struct iio_hw_consumer *hwc;
  73         struct completion completion;
  74         u32 *buffer;
  75
  76         /* Audio specific */
  77         unsigned int spi_freq;  /* SPI bus clock frequency */
  78         unsigned int sample_freq; /* Sample frequency after filter decimation */
  79         int (*cb)(const void *data, size_t size, void *cb_priv);
  80         void *cb_priv;
  81
  82         /* DMA */
  83         u8 *rx_buf;
  84         unsigned int bufi; /* Buffer current position */
  85         unsigned int buf_sz; /* Buffer size */
  86         struct dma_chan *dma_chan;
  87         dma_addr_t dma_buf;
  88 };
  89
  90 struct stm32_dfsdm_str2field {
  91         const char      *name;
  92         unsigned int    val;
  93 };
  94
  95 /* DFSDM channel serial interface type */
  96 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
  97         { "SPI_R", 0 }, /* SPI with data on rising edge */
  98         { "SPI_F", 1 }, /* SPI with data on falling edge */
  99         { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
 100         { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
 101         {},
 102 };
 103
 104 /* DFSDM channel clock source */
 105 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
 106         /* External SPI clock (CLKIN x) */
 107         { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
 108         /* Internal SPI clock (CLKOUT) */
 109         { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
 110         /* Internal SPI clock divided by 2 (falling edge) */
 111         { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
 112         /* Internal SPI clock divided by 2 (falling edge) */
 113         { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
 114         {},
 115 };
 116
 117 static int stm32_dfsdm_str2val(const char *str,
 118                                const struct stm32_dfsdm_str2field *list)
 119 {
 120         const struct stm32_dfsdm_str2field *p = list;
 121
 122         for (p = list; p && p->name; p++)
 123                 if (!strcmp(p->name, str))
 124                         return p->val;
 125
 126         return -EINVAL;
 127 }
 128
 129 /**
 130  * struct stm32_dfsdm_trig_info - DFSDM trigger info
 131  * @name:               name of the trigger, corresponding to its source
 132  * @jextsel:            trigger signal selection
 133  */
 134 struct stm32_dfsdm_trig_info {
 135         const char *name;
 136         unsigned int jextsel;
 137 };
 138
 139 /* hardware injected trigger enable, edge selection */
 140 enum stm32_dfsdm_jexten {
 141         STM32_DFSDM_JEXTEN_DISABLED,
 142         STM32_DFSDM_JEXTEN_RISING_EDGE,
 143         STM32_DFSDM_JEXTEN_FALLING_EDGE,
 144         STM32_DFSDM_EXTEN_BOTH_EDGES,
 145 };
 146
 147 static const struct stm32_dfsdm_trig_info stm32_dfsdm_trigs[] = {
 148         { TIM1_TRGO, 0 },
 149         { TIM1_TRGO2, 1 },
 150         { TIM8_TRGO, 2 },
 151         { TIM8_TRGO2, 3 },
 152         { TIM3_TRGO, 4 },
 153         { TIM4_TRGO, 5 },
 154         { TIM16_OC1, 6 },
 155         { TIM6_TRGO, 7 },
 156         { TIM7_TRGO, 8 },
 157         { LPTIM1_OUT, 26 },
 158         { LPTIM2_OUT, 27 },
 159         { LPTIM3_OUT, 28 },
 160         {},
 161 };
 162
 163 static int stm32_dfsdm_get_jextsel(struct iio_dev *indio_dev,
 164                                    struct iio_trigger *trig)
 165 {
 166         int i;
 167
 168         /* lookup triggers registered by stm32 timer trigger driver */
 169         for (i = 0; stm32_dfsdm_trigs[i].name; i++) {
 170                 /**
 171                  * Checking both stm32 timer trigger type and trig name
 172                  * should be safe against arbitrary trigger names.
 173                  */
 174                 if ((is_stm32_timer_trigger(trig) ||
 175                      is_stm32_lptim_trigger(trig)) &&
 176                     !strcmp(stm32_dfsdm_trigs[i].name, trig->name)) {
 177                         return stm32_dfsdm_trigs[i].jextsel;
 178                 }
 179         }
 180
 181         return -EINVAL;
 182 }
 183
 184 static int stm32_dfsdm_set_osrs(struct stm32_dfsdm_filter *fl,
 185                                 unsigned int fast, unsigned int oversamp)
 186 {
 187         unsigned int i, d, fosr, iosr;
 188         u64 res;
 189         s64 delta;
 190         unsigned int m = 1;     /* multiplication factor */
 191         unsigned int p = fl->ford;      /* filter order (ford) */
 192
 193         pr_debug("%s: Requested oversampling: %d\n",  __func__, oversamp);
 194         /*
 195          * This function tries to compute filter oversampling and integrator
 196          * oversampling, base on oversampling ratio requested by user.
 197          *
 198          * Decimation d depends on the filter order and the oversampling ratios.
 199          * ford: filter order
 200          * fosr: filter over sampling ratio
 201          * iosr: integrator over sampling ratio
 202          */
 203         if (fl->ford == DFSDM_FASTSINC_ORDER) {
 204                 m = 2;
 205                 p = 2;
 206         }
 207
 208         /*
 209          * Look for filter and integrator oversampling ratios which allows
 210          * to reach 24 bits data output resolution.
 211          * Leave as soon as if exact resolution if reached.
 212          * Otherwise the higher resolution below 32 bits is kept.
 213          */
 214         fl->res = 0;
 215         for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
 216                 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
 217                         if (fast)
 218                                 d = fosr * iosr;
 219                         else if (fl->ford == DFSDM_FASTSINC_ORDER)
 220                                 d = fosr * (iosr + 3) + 2;
 221                         else
 222                                 d = fosr * (iosr - 1 + p) + p;
 223
 224                         if (d > oversamp)
 225                                 break;
 226                         else if (d != oversamp)
 227                                 continue;
 228                         /*
 229                          * Check resolution (limited to signed 32 bits)
 230                          *   res <= 2^31
 231                          * Sincx filters:
 232                          *   res = m * fosr^p x iosr (with m=1, p=ford)
 233                          * FastSinc filter
 234                          *   res = m * fosr^p x iosr (with m=2, p=2)
 235                          */
 236                         res = fosr;
 237                         for (i = p - 1; i > 0; i--) {
 238                                 res = res * (u64)fosr;
 239                                 if (res > DFSDM_MAX_RES)
 240                                         break;
 241                         }
 242                         if (res > DFSDM_MAX_RES)
 243                                 continue;
 244                         res = res * (u64)m * (u64)iosr;
 245                         if (res > DFSDM_MAX_RES)
 246                                 continue;
 247
 248                         delta = res - DFSDM_DATA_RES;
 249
 250                         if (res >= fl->res) {
 251                                 fl->res = res;
 252                                 fl->fosr = fosr;
 253                                 fl->iosr = iosr;
 254                                 fl->fast = fast;
 255                                 pr_debug("%s: fosr = %d, iosr = %d\n",
 256                                          __func__, fl->fosr, fl->iosr);
 257                         }
 258
 259                         if (!delta)
 260                                 return 0;
 261                 }
 262         }
 263
 264         if (!fl->res)
 265                 return -EINVAL;
 266
 267         return 0;
 268 }
 269
 270 static int stm32_dfsdm_start_channel(struct stm32_dfsdm_adc *adc)
 271 {
 272         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 273         struct regmap *regmap = adc->dfsdm->regmap;
 274         const struct iio_chan_spec *chan;
 275         unsigned int bit;
 276         int ret;
 277
 278         for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
 279                 chan = indio_dev->channels + bit;
 280                 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
 281                                          DFSDM_CHCFGR1_CHEN_MASK,
 282                                          DFSDM_CHCFGR1_CHEN(1));
 283                 if (ret < 0)
 284                         return ret;
 285         }
 286
 287         return 0;
 288 }
 289
 290 static void stm32_dfsdm_stop_channel(struct stm32_dfsdm_adc *adc)
 291 {
 292         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 293         struct regmap *regmap = adc->dfsdm->regmap;
 294         const struct iio_chan_spec *chan;
 295         unsigned int bit;
 296
 297         for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
 298                 chan = indio_dev->channels + bit;
 299                 regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
 300                                    DFSDM_CHCFGR1_CHEN_MASK,
 301                                    DFSDM_CHCFGR1_CHEN(0));
 302         }
 303 }
 304
 305 static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
 306                                       struct stm32_dfsdm_channel *ch)
 307 {
 308         unsigned int id = ch->id;
 309         struct regmap *regmap = dfsdm->regmap;
 310         int ret;
 311
 312         ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
 313                                  DFSDM_CHCFGR1_SITP_MASK,
 314                                  DFSDM_CHCFGR1_SITP(ch->type));
 315         if (ret < 0)
 316                 return ret;
 317         ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
 318                                  DFSDM_CHCFGR1_SPICKSEL_MASK,
 319                                  DFSDM_CHCFGR1_SPICKSEL(ch->src));
 320         if (ret < 0)
 321                 return ret;
 322         return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
 323                                   DFSDM_CHCFGR1_CHINSEL_MASK,
 324                                   DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
 325 }
 326
 327 static int stm32_dfsdm_start_filter(struct stm32_dfsdm_adc *adc,
 328                                     unsigned int fl_id,
 329                                     struct iio_trigger *trig)
 330 {
 331         struct stm32_dfsdm *dfsdm = adc->dfsdm;
 332         int ret;
 333
 334         /* Enable filter */
 335         ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
 336                                  DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
 337         if (ret < 0)
 338                 return ret;
 339
 340         /* Nothing more to do for injected (scan mode/triggered) conversions */
 341         if (adc->nconv > 1 || trig)
 342                 return 0;
 343
 344         /* Software start (single or continuous) regular conversion */
 345         return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
 346                                   DFSDM_CR1_RSWSTART_MASK,
 347                                   DFSDM_CR1_RSWSTART(1));
 348 }
 349
 350 static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
 351                                     unsigned int fl_id)
 352 {
 353         /* Disable conversion */
 354         regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
 355                            DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
 356 }
 357
 358 static int stm32_dfsdm_filter_set_trig(struct stm32_dfsdm_adc *adc,
 359                                        unsigned int fl_id,
 360                                        struct iio_trigger *trig)
 361 {
 362         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 363         struct regmap *regmap = adc->dfsdm->regmap;
 364         u32 jextsel = 0, jexten = STM32_DFSDM_JEXTEN_DISABLED;
 365         int ret;
 366
 367         if (trig) {
 368                 ret = stm32_dfsdm_get_jextsel(indio_dev, trig);
 369                 if (ret < 0)
 370                         return ret;
 371
 372                 /* set trigger source and polarity (default to rising edge) */
 373                 jextsel = ret;
 374                 jexten = STM32_DFSDM_JEXTEN_RISING_EDGE;
 375         }
 376
 377         ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
 378                                  DFSDM_CR1_JEXTSEL_MASK | DFSDM_CR1_JEXTEN_MASK,
 379                                  DFSDM_CR1_JEXTSEL(jextsel) |
 380                                  DFSDM_CR1_JEXTEN(jexten));
 381         if (ret < 0)
 382                 return ret;
 383
 384         return 0;
 385 }
 386
 387 static int stm32_dfsdm_filter_configure(struct stm32_dfsdm_adc *adc,
 388                                         unsigned int fl_id,
 389                                         struct iio_trigger *trig)
 390 {
 391         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
 392         struct regmap *regmap = adc->dfsdm->regmap;
 393         struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
 394         u32 cr1;
 395         const struct iio_chan_spec *chan;
 396         unsigned int bit, jchg = 0;
 397         int ret;
 398
 399         /* Average integrator oversampling */
 400         ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
 401                                  DFSDM_FCR_IOSR(fl->iosr - 1));
 402         if (ret)
 403                 return ret;
 404
 405         /* Filter order and Oversampling */
 406         ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
 407                                  DFSDM_FCR_FOSR(fl->fosr - 1));
 408         if (ret)
 409                 return ret;
 410
 411         ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
 412                                  DFSDM_FCR_FORD(fl->ford));
 413         if (ret)
 414                 return ret;
 415
 416         ret = stm32_dfsdm_filter_set_trig(adc, fl_id, trig);
 417         if (ret)
 418                 return ret;
 419
 420         /*
 421          * DFSDM modes configuration W.R.T audio/iio type modes
 422          * ----------------------------------------------------------------
 423          * Modes         | regular |  regular     | injected | injected   |
 424          *               |         |  continuous  |          | + scan     |
 425          * --------------|---------|--------------|----------|------------|
 426          * single conv   |    x    |              |          |            |
 427          * (1 chan)      |         |              |          |            |
 428          * --------------|---------|--------------|----------|------------|
 429          * 1 Audio chan  |         | sample freq  |          |            |
 430          *               |         | or sync_mode |          |            |
 431          * --------------|---------|--------------|----------|------------|
 432          * 1 IIO chan    |         | sample freq  | trigger  |            |
 433          *               |         | or sync_mode |          |            |
 434          * --------------|---------|--------------|----------|------------|
 435          * 2+ IIO chans  |         |              |          | trigger or |
 436          *               |         |              |          | sync_mode  |
 437          * ----------------------------------------------------------------
 438          */
 439         if (adc->nconv == 1 && !trig) {
 440                 bit = __ffs(adc->smask);
 441                 chan = indio_dev->channels + bit;
 442
 443                 /* Use regular conversion for single channel without trigger */
 444                 cr1 = DFSDM_CR1_RCH(chan->channel);
 445
 446                 /* Continuous conversions triggered by SPI clk in buffer mode */
 447                 if (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)
 448                         cr1 |= DFSDM_CR1_RCONT(1);
 449
 450                 cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode);
 451         } else {
 452                 /* Use injected conversion for multiple channels */
 453                 for_each_set_bit(bit, &adc->smask,
 454                                  sizeof(adc->smask) * BITS_PER_BYTE) {
 455                         chan = indio_dev->channels + bit;
 456                         jchg |= BIT(chan->channel);
 457                 }
 458                 ret = regmap_write(regmap, DFSDM_JCHGR(fl_id), jchg);
 459                 if (ret < 0)
 460                         return ret;
 461
 462                 /* Use scan mode for multiple channels */
 463                 cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0);
 464
 465                 /*
 466                  * Continuous conversions not supported in injected mode,
 467                  * either use:
 468                  * - conversions in sync with filter 0
 469                  * - triggered conversions
 470                  */
 471                 if (!fl->sync_mode && !trig)
 472                         return -EINVAL;
 473                 cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode);
 474         }
 475
 476         return regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_CFG_MASK,
 477                                   cr1);
 478 }
 479
 480 static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
 481                                         struct iio_dev *indio_dev,
 482                                         struct iio_chan_spec *ch)
 483 {
 484         struct stm32_dfsdm_channel *df_ch;
 485         const char *of_str;
 486         int chan_idx = ch->scan_index;
 487         int ret, val;
 488
 489         ret = of_property_read_u32_index(indio_dev->dev.of_node,
 490                                          "st,adc-channels", chan_idx,
 491                                          &ch->channel);
 492         if (ret < 0) {
 493                 dev_err(&indio_dev->dev,
 494                         " Error parsing 'st,adc-channels' for idx %d\n",
 495                         chan_idx);
 496                 return ret;
 497         }
 498         if (ch->channel >= dfsdm->num_chs) {
 499                 dev_err(&indio_dev->dev,
 500                         " Error bad channel number %d (max = %d)\n",
 501                         ch->channel, dfsdm->num_chs);
 502                 return -EINVAL;
 503         }
 504
 505         ret = of_property_read_string_index(indio_dev->dev.of_node,
 506                                             "st,adc-channel-names", chan_idx,
 507                                             &ch->datasheet_name);
 508         if (ret < 0) {
 509                 dev_err(&indio_dev->dev,
 510                         " Error parsing 'st,adc-channel-names' for idx %d\n",
 511                         chan_idx);
 512                 return ret;
 513         }
 514
 515         df_ch =  &dfsdm->ch_list[ch->channel];
 516         df_ch->id = ch->channel;
 517
 518         ret = of_property_read_string_index(indio_dev->dev.of_node,
 519                                             "st,adc-channel-types", chan_idx,
 520                                             &of_str);
 521         if (!ret) {
 522                 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
 523                 if (val < 0)
 524                         return val;
 525         } else {
 526                 val = 0;
 527         }
 528         df_ch->type = val;
 529
 530         ret = of_property_read_string_index(indio_dev->dev.of_node,
 531                                             "st,adc-channel-clk-src", chan_idx,
 532                                             &of_str);
 533         if (!ret) {
 534                 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
 535                 if (val < 0)
 536                         return val;
 537         } else {
 538                 val = 0;
 539         }
 540         df_ch->src = val;
 541
 542         ret = of_property_read_u32_index(indio_dev->dev.of_node,
 543                                          "st,adc-alt-channel", chan_idx,
 544                                          &df_ch->alt_si);
 545         if (ret < 0)
 546                 df_ch->alt_si = 0;
 547
 548         return 0;
 549 }
 550
 551 static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
 552                                           uintptr_t priv,
 553                                           const struct iio_chan_spec *chan,
 554                                           char *buf)
 555 {
 556         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 557
 558         return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
 559 }
 560
 561 static int dfsdm_adc_set_samp_freq(struct iio_dev *indio_dev,
 562                                    unsigned int sample_freq,
 563                                    unsigned int spi_freq)
 564 {
 565         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 566         struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
 567         unsigned int oversamp;
 568         int ret;
 569
 570         oversamp = DIV_ROUND_CLOSEST(spi_freq, sample_freq);
 571         if (spi_freq % sample_freq)
 572                 dev_dbg(&indio_dev->dev,
 573                         "Rate not accurate. requested (%u), actual (%u)\n",
 574                         sample_freq, spi_freq / oversamp);
 575
 576         ret = stm32_dfsdm_set_osrs(fl, 0, oversamp);
 577         if (ret < 0) {
 578                 dev_err(&indio_dev->dev, "No filter parameters that match!\n");
 579                 return ret;
 580         }
 581         adc->sample_freq = spi_freq / oversamp;
 582         adc->oversamp = oversamp;
 583
 584         return 0;
 585 }
 586
 587 static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
 588                                           uintptr_t priv,
 589                                           const struct iio_chan_spec *chan,
 590                                           const char *buf, size_t len)
 591 {
 592         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 593         struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
 594         unsigned int sample_freq = adc->sample_freq;
 595         unsigned int spi_freq;
 596         int ret;
 597
 598         dev_err(&indio_dev->dev, "enter %s\n", __func__);
 599         /* If DFSDM is master on SPI, SPI freq can not be updated */
 600         if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
 601                 return -EPERM;
 602
 603         ret = kstrtoint(buf, 0, &spi_freq);
 604         if (ret)
 605                 return ret;
 606
 607         if (!spi_freq)
 608                 return -EINVAL;
 609
 610         if (sample_freq) {
 611                 ret = dfsdm_adc_set_samp_freq(indio_dev, sample_freq, spi_freq);
 612                 if (ret < 0)
 613                         return ret;
 614         }
 615         adc->spi_freq = spi_freq;
 616
 617         return len;
 618 }
 619
 620 static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc,
 621                                   struct iio_trigger *trig)
 622 {
 623         struct regmap *regmap = adc->dfsdm->regmap;
 624         int ret;
 625
 626         ret = stm32_dfsdm_start_channel(adc);
 627         if (ret < 0)
 628                 return ret;
 629
 630         ret = stm32_dfsdm_filter_configure(adc, adc->fl_id, trig);
 631         if (ret < 0)
 632                 goto stop_channels;
 633
 634         ret = stm32_dfsdm_start_filter(adc, adc->fl_id, trig);
 635         if (ret < 0)
 636                 goto filter_unconfigure;
 637
 638         return 0;
 639
 640 filter_unconfigure:
 641         regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
 642                            DFSDM_CR1_CFG_MASK, 0);
 643 stop_channels:
 644         stm32_dfsdm_stop_channel(adc);
 645
 646         return ret;
 647 }
 648
 649 static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc)
 650 {
 651         struct regmap *regmap = adc->dfsdm->regmap;
 652
 653         stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
 654
 655         regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
 656                            DFSDM_CR1_CFG_MASK, 0);
 657
 658         stm32_dfsdm_stop_channel(adc);
 659 }
 660
 661 static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
 662                                      unsigned int val)
 663 {
 664         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 665         unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
 666         unsigned int rx_buf_sz = DFSDM_DMA_BUFFER_SIZE;
 667
 668         /*
 669          * DMA cyclic transfers are used, buffer is split into two periods.
 670          * There should be :
 671          * - always one buffer (period) DMA is working on
 672          * - one buffer (period) driver pushed to ASoC side.
 673          */
 674         watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
 675         adc->buf_sz = min(rx_buf_sz, watermark * 2 * adc->nconv);
 676
 677         return 0;
 678 }
 679
 680 static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
 681 {
 682         struct dma_tx_state state;
 683         enum dma_status status;
 684
 685         status = dmaengine_tx_status(adc->dma_chan,
 686                                      adc->dma_chan->cookie,
 687                                      &state);
 688         if (status == DMA_IN_PROGRESS) {
 689                 /* Residue is size in bytes from end of buffer */
 690                 unsigned int i = adc->buf_sz - state.residue;
 691                 unsigned int size;
 692
 693                 /* Return available bytes */
 694                 if (i >= adc->bufi)
 695                         size = i - adc->bufi;
 696                 else
 697                         size = adc->buf_sz + i - adc->bufi;
 698
 699                 return size;
 700         }
 701
 702         return 0;
 703 }
 704
 705 static irqreturn_t stm32_dfsdm_adc_trigger_handler(int irq, void *p)
 706 {
 707         struct iio_poll_func *pf = p;
 708         struct iio_dev *indio_dev = pf->indio_dev;
 709         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 710         int available = stm32_dfsdm_adc_dma_residue(adc);
 711
 712         while (available >= indio_dev->scan_bytes) {
 713                 u32 *buffer = (u32 *)&adc->rx_buf[adc->bufi];
 714
 715                 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
 716                                                    pf->timestamp);
 717                 available -= indio_dev->scan_bytes;
 718                 adc->bufi += indio_dev->scan_bytes;
 719                 if (adc->bufi >= adc->buf_sz)
 720                         adc->bufi = 0;
 721         }
 722
 723         iio_trigger_notify_done(indio_dev->trig);
 724
 725         return IRQ_HANDLED;
 726 }
 727
 728 static void stm32_dfsdm_dma_buffer_done(void *data)
 729 {
 730         struct iio_dev *indio_dev = data;
 731         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 732         int available = stm32_dfsdm_adc_dma_residue(adc);
 733         size_t old_pos;
 734
 735         if (indio_dev->currentmode & INDIO_BUFFER_TRIGGERED) {
 736                 iio_trigger_poll_chained(indio_dev->trig);
 737                 return;
 738         }
 739
 740         /*
 741          * FIXME: In Kernel interface does not support cyclic DMA buffer,and
 742          * offers only an interface to push data samples per samples.
 743          * For this reason IIO buffer interface is not used and interface is
 744          * bypassed using a private callback registered by ASoC.
 745          * This should be a temporary solution waiting a cyclic DMA engine
 746          * support in IIO.
 747          */
 748
 749         dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__,
 750                 adc->bufi, available);
 751         old_pos = adc->bufi;
 752
 753         while (available >= indio_dev->scan_bytes) {
 754                 u32 *buffer = (u32 *)&adc->rx_buf[adc->bufi];
 755
 756                 /* Mask 8 LSB that contains the channel ID */
 757                 *buffer = (*buffer & 0xFFFFFF00) << 8;
 758                 available -= indio_dev->scan_bytes;
 759                 adc->bufi += indio_dev->scan_bytes;
 760                 if (adc->bufi >= adc->buf_sz) {
 761                         if (adc->cb)
 762                                 adc->cb(&adc->rx_buf[old_pos],
 763                                          adc->buf_sz - old_pos, adc->cb_priv);
 764                         adc->bufi = 0;
 765                         old_pos = 0;
 766                 }
 767                 /* regular iio buffer without trigger */
 768                 if (adc->dev_data->type == DFSDM_IIO)
 769                         iio_push_to_buffers(indio_dev, buffer);
 770         }
 771         if (adc->cb)
 772                 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
 773                         adc->cb_priv);
 774 }
 775
 776 static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
 777 {
 778         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 779         struct dma_slave_config config = {
 780                 .src_addr = (dma_addr_t)adc->dfsdm->phys_base,
 781                 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
 782         };
 783         struct dma_async_tx_descriptor *desc;
 784         dma_cookie_t cookie;
 785         int ret;
 786
 787         if (!adc->dma_chan)
 788                 return -EINVAL;
 789
 790         dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
 791                 adc->buf_sz, adc->buf_sz / 2);
 792
 793         if (adc->nconv == 1 && !indio_dev->trig)
 794                 config.src_addr += DFSDM_RDATAR(adc->fl_id);
 795         else
 796                 config.src_addr += DFSDM_JDATAR(adc->fl_id);
 797         ret = dmaengine_slave_config(adc->dma_chan, &config);
 798         if (ret)
 799                 return ret;
 800
 801         /* Prepare a DMA cyclic transaction */
 802         desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
 803                                          adc->dma_buf,
 804                                          adc->buf_sz, adc->buf_sz / 2,
 805                                          DMA_DEV_TO_MEM,
 806                                          DMA_PREP_INTERRUPT);
 807         if (!desc)
 808                 return -EBUSY;
 809
 810         desc->callback = stm32_dfsdm_dma_buffer_done;
 811         desc->callback_param = indio_dev;
 812
 813         cookie = dmaengine_submit(desc);
 814         ret = dma_submit_error(cookie);
 815         if (ret)
 816                 goto err_stop_dma;
 817
 818         /* Issue pending DMA requests */
 819         dma_async_issue_pending(adc->dma_chan);
 820
 821         if (adc->nconv == 1 && !indio_dev->trig) {
 822                 /* Enable regular DMA transfer*/
 823                 ret = regmap_update_bits(adc->dfsdm->regmap,
 824                                          DFSDM_CR1(adc->fl_id),
 825                                          DFSDM_CR1_RDMAEN_MASK,
 826                                          DFSDM_CR1_RDMAEN_MASK);
 827         } else {
 828                 /* Enable injected DMA transfer*/
 829                 ret = regmap_update_bits(adc->dfsdm->regmap,
 830                                          DFSDM_CR1(adc->fl_id),
 831                                          DFSDM_CR1_JDMAEN_MASK,
 832                                          DFSDM_CR1_JDMAEN_MASK);
 833         }
 834
 835         if (ret < 0)
 836                 goto err_stop_dma;
 837
 838         return 0;
 839
 840 err_stop_dma:
 841         dmaengine_terminate_all(adc->dma_chan);
 842
 843         return ret;
 844 }
 845
 846 static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev)
 847 {
 848         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 849
 850         if (!adc->dma_chan)
 851                 return;
 852
 853         regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
 854                            DFSDM_CR1_RDMAEN_MASK | DFSDM_CR1_JDMAEN_MASK, 0);
 855         dmaengine_terminate_all(adc->dma_chan);
 856 }
 857
 858 static int stm32_dfsdm_update_scan_mode(struct iio_dev *indio_dev,
 859                                         const unsigned long *scan_mask)
 860 {
 861         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 862
 863         adc->nconv = bitmap_weight(scan_mask, indio_dev->masklength);
 864         adc->smask = *scan_mask;
 865
 866         dev_dbg(&indio_dev->dev, "nconv=%d mask=%lx\n", adc->nconv, *scan_mask);
 867
 868         return 0;
 869 }
 870
 871 static int __stm32_dfsdm_postenable(struct iio_dev *indio_dev)
 872 {
 873         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 874         int ret;
 875
 876         /* Reset adc buffer index */
 877         adc->bufi = 0;
 878
 879         if (adc->hwc) {
 880                 ret = iio_hw_consumer_enable(adc->hwc);
 881                 if (ret < 0)
 882                         return ret;
 883         }
 884
 885         ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
 886         if (ret < 0)
 887                 goto err_stop_hwc;
 888
 889         ret = stm32_dfsdm_adc_dma_start(indio_dev);
 890         if (ret) {
 891                 dev_err(&indio_dev->dev, "Can't start DMA\n");
 892                 goto stop_dfsdm;
 893         }
 894
 895         ret = stm32_dfsdm_start_conv(adc, indio_dev->trig);
 896         if (ret) {
 897                 dev_err(&indio_dev->dev, "Can't start conversion\n");
 898                 goto err_stop_dma;
 899         }
 900
 901         return 0;
 902
 903 err_stop_dma:
 904         stm32_dfsdm_adc_dma_stop(indio_dev);
 905 stop_dfsdm:
 906         stm32_dfsdm_stop_dfsdm(adc->dfsdm);
 907 err_stop_hwc:
 908         if (adc->hwc)
 909                 iio_hw_consumer_disable(adc->hwc);
 910
 911         return ret;
 912 }
 913
 914 static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
 915 {
 916         int ret;
 917
 918         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
 919                 ret = iio_triggered_buffer_postenable(indio_dev);
 920                 if (ret < 0)
 921                         return ret;
 922         }
 923
 924         ret = __stm32_dfsdm_postenable(indio_dev);
 925         if (ret < 0)
 926                 goto err_predisable;
 927
 928         return 0;
 929
 930 err_predisable:
 931         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
 932                 iio_triggered_buffer_predisable(indio_dev);
 933
 934         return ret;
 935 }
 936
 937 static void __stm32_dfsdm_predisable(struct iio_dev *indio_dev)
 938 {
 939         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 940
 941         stm32_dfsdm_stop_conv(adc);
 942
 943         stm32_dfsdm_adc_dma_stop(indio_dev);
 944
 945         stm32_dfsdm_stop_dfsdm(adc->dfsdm);
 946
 947         if (adc->hwc)
 948                 iio_hw_consumer_disable(adc->hwc);
 949 }
 950
 951 static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
 952 {
 953         __stm32_dfsdm_predisable(indio_dev);
 954
 955         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
 956                 iio_triggered_buffer_predisable(indio_dev);
 957
 958         return 0;
 959 }
 960
 961 static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
 962         .postenable = &stm32_dfsdm_postenable,
 963         .predisable = &stm32_dfsdm_predisable,
 964 };
 965
 966 /**
 967  * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
 968  *                             DMA transfer period is achieved.
 969  *
 970  * @iio_dev: Handle to IIO device.
 971  * @cb: Pointer to callback function:
 972  *      - data: pointer to data buffer
 973  *      - size: size in byte of the data buffer
 974  *      - private: pointer to consumer private structure.
 975  * @private: Pointer to consumer private structure.
 976  */
 977 int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
 978                             int (*cb)(const void *data, size_t size,
 979                                       void *private),
 980                             void *private)
 981 {
 982         struct stm32_dfsdm_adc *adc;
 983
 984         if (!iio_dev)
 985                 return -EINVAL;
 986         adc = iio_priv(iio_dev);
 987
 988         adc->cb = cb;
 989         adc->cb_priv = private;
 990
 991         return 0;
 992 }
 993 EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
 994
 995 /**
 996  * stm32_dfsdm_release_buff_cb - unregister buffer callback
 997  *
 998  * @iio_dev: Handle to IIO device.
 999  */
1000 int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
1001 {
1002         struct stm32_dfsdm_adc *adc;
1003
1004         if (!iio_dev)
1005                 return -EINVAL;
1006         adc = iio_priv(iio_dev);
1007
1008         adc->cb = NULL;
1009         adc->cb_priv = NULL;
1010
1011         return 0;
1012 }
1013 EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
1014
1015 static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
1016                                    const struct iio_chan_spec *chan, int *res)
1017 {
1018         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1019         long timeout;
1020         int ret;
1021
1022         reinit_completion(&adc->completion);
1023
1024         adc->buffer = res;
1025
1026         ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1027         if (ret < 0)
1028                 return ret;
1029
1030         ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1031                                  DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
1032         if (ret < 0)
1033                 goto stop_dfsdm;
1034
1035         adc->nconv = 1;
1036         adc->smask = BIT(chan->scan_index);
1037         ret = stm32_dfsdm_start_conv(adc, NULL);
1038         if (ret < 0) {
1039                 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1040                                    DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1041                 goto stop_dfsdm;
1042         }
1043
1044         timeout = wait_for_completion_interruptible_timeout(&adc->completion,
1045                                                             DFSDM_TIMEOUT);
1046
1047         /* Mask IRQ for regular conversion achievement*/
1048         regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1049                            DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1050
1051         if (timeout == 0)
1052                 ret = -ETIMEDOUT;
1053         else if (timeout < 0)
1054                 ret = timeout;
1055         else
1056                 ret = IIO_VAL_INT;
1057
1058         stm32_dfsdm_stop_conv(adc);
1059
1060 stop_dfsdm:
1061         stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1062
1063         return ret;
1064 }
1065
1066 static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
1067                                  struct iio_chan_spec const *chan,
1068                                  int val, int val2, long mask)
1069 {
1070         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1071         struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
1072         struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
1073         unsigned int spi_freq;
1074         int ret = -EINVAL;
1075
1076         switch (mask) {
1077         case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1078                 ret = iio_device_claim_direct_mode(indio_dev);
1079                 if (ret)
1080                         return ret;
1081                 ret = stm32_dfsdm_set_osrs(fl, 0, val);
1082                 if (!ret)
1083                         adc->oversamp = val;
1084                 iio_device_release_direct_mode(indio_dev);
1085                 return ret;
1086
1087         case IIO_CHAN_INFO_SAMP_FREQ:
1088                 if (!val)
1089                         return -EINVAL;
1090
1091                 ret = iio_device_claim_direct_mode(indio_dev);
1092                 if (ret)
1093                         return ret;
1094
1095                 switch (ch->src) {
1096                 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL:
1097                         spi_freq = adc->dfsdm->spi_master_freq;
1098                         break;
1099                 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING:
1100                 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING:
1101                         spi_freq = adc->dfsdm->spi_master_freq / 2;
1102                         break;
1103                 default:
1104                         spi_freq = adc->spi_freq;
1105                 }
1106
1107                 ret = dfsdm_adc_set_samp_freq(indio_dev, val, spi_freq);
1108                 iio_device_release_direct_mode(indio_dev);
1109                 return ret;
1110         }
1111
1112         return -EINVAL;
1113 }
1114
1115 static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
1116                                 struct iio_chan_spec const *chan, int *val,
1117                                 int *val2, long mask)
1118 {
1119         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1120         int ret;
1121
1122         switch (mask) {
1123         case IIO_CHAN_INFO_RAW:
1124                 ret = iio_device_claim_direct_mode(indio_dev);
1125                 if (ret)
1126                         return ret;
1127                 ret = iio_hw_consumer_enable(adc->hwc);
1128                 if (ret < 0) {
1129                         dev_err(&indio_dev->dev,
1130                                 "%s: IIO enable failed (channel %d)\n",
1131                                 __func__, chan->channel);
1132                         iio_device_release_direct_mode(indio_dev);
1133                         return ret;
1134                 }
1135                 ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
1136                 iio_hw_consumer_disable(adc->hwc);
1137                 if (ret < 0) {
1138                         dev_err(&indio_dev->dev,
1139                                 "%s: Conversion failed (channel %d)\n",
1140                                 __func__, chan->channel);
1141                         iio_device_release_direct_mode(indio_dev);
1142                         return ret;
1143                 }
1144                 iio_device_release_direct_mode(indio_dev);
1145                 return IIO_VAL_INT;
1146
1147         case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1148                 *val = adc->oversamp;
1149
1150                 return IIO_VAL_INT;
1151
1152         case IIO_CHAN_INFO_SAMP_FREQ:
1153                 *val = adc->sample_freq;
1154
1155                 return IIO_VAL_INT;
1156         }
1157
1158         return -EINVAL;
1159 }
1160
1161 static int stm32_dfsdm_validate_trigger(struct iio_dev *indio_dev,
1162                                         struct iio_trigger *trig)
1163 {
1164         return stm32_dfsdm_get_jextsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1165 }
1166
1167 static const struct iio_info stm32_dfsdm_info_audio = {
1168         .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1169         .read_raw = stm32_dfsdm_read_raw,
1170         .write_raw = stm32_dfsdm_write_raw,
1171         .update_scan_mode = stm32_dfsdm_update_scan_mode,
1172 };
1173
1174 static const struct iio_info stm32_dfsdm_info_adc = {
1175         .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1176         .read_raw = stm32_dfsdm_read_raw,
1177         .write_raw = stm32_dfsdm_write_raw,
1178         .update_scan_mode = stm32_dfsdm_update_scan_mode,
1179         .validate_trigger = stm32_dfsdm_validate_trigger,
1180 };
1181
1182 static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
1183 {
1184         struct stm32_dfsdm_adc *adc = arg;
1185         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1186         struct regmap *regmap = adc->dfsdm->regmap;
1187         unsigned int status, int_en;
1188
1189         regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
1190         regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
1191
1192         if (status & DFSDM_ISR_REOCF_MASK) {
1193                 /* Read the data register clean the IRQ status */
1194                 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
1195                 complete(&adc->completion);
1196         }
1197
1198         if (status & DFSDM_ISR_ROVRF_MASK) {
1199                 if (int_en & DFSDM_CR2_ROVRIE_MASK)
1200                         dev_warn(&indio_dev->dev, "Overrun detected\n");
1201                 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
1202                                    DFSDM_ICR_CLRROVRF_MASK,
1203                                    DFSDM_ICR_CLRROVRF_MASK);
1204         }
1205
1206         return IRQ_HANDLED;
1207 }
1208
1209 /*
1210  * Define external info for SPI Frequency and audio sampling rate that can be
1211  * configured by ASoC driver through consumer.h API
1212  */
1213 static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
1214         /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
1215         {
1216                 .name = "spi_clk_freq",
1217                 .shared = IIO_SHARED_BY_TYPE,
1218                 .read = dfsdm_adc_audio_get_spiclk,
1219                 .write = dfsdm_adc_audio_set_spiclk,
1220         },
1221         {},
1222 };
1223
1224 static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
1225 {
1226         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1227
1228         if (adc->dma_chan) {
1229                 dma_free_coherent(adc->dma_chan->device->dev,
1230                                   DFSDM_DMA_BUFFER_SIZE,
1231                                   adc->rx_buf, adc->dma_buf);
1232                 dma_release_channel(adc->dma_chan);
1233         }
1234 }
1235
1236 static int stm32_dfsdm_dma_request(struct iio_dev *indio_dev)
1237 {
1238         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1239
1240         adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
1241         if (!adc->dma_chan)
1242                 return -EINVAL;
1243
1244         adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1245                                          DFSDM_DMA_BUFFER_SIZE,
1246                                          &adc->dma_buf, GFP_KERNEL);
1247         if (!adc->rx_buf) {
1248                 dma_release_channel(adc->dma_chan);
1249                 return -ENOMEM;
1250         }
1251
1252         indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1253         indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
1254
1255         return 0;
1256 }
1257
1258 static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
1259                                          struct iio_chan_spec *ch)
1260 {
1261         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1262         int ret;
1263
1264         ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
1265         if (ret < 0)
1266                 return ret;
1267
1268         ch->type = IIO_VOLTAGE;
1269         ch->indexed = 1;
1270
1271         /*
1272          * IIO_CHAN_INFO_RAW: used to compute regular conversion
1273          * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
1274          */
1275         ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1276         ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
1277                                         BIT(IIO_CHAN_INFO_SAMP_FREQ);
1278
1279         if (adc->dev_data->type == DFSDM_AUDIO) {
1280                 ch->scan_type.sign = 's';
1281                 ch->ext_info = dfsdm_adc_audio_ext_info;
1282         } else {
1283                 ch->scan_type.sign = 'u';
1284         }
1285         ch->scan_type.realbits = 24;
1286         ch->scan_type.storagebits = 32;
1287
1288         return stm32_dfsdm_chan_configure(adc->dfsdm,
1289                                           &adc->dfsdm->ch_list[ch->channel]);
1290 }
1291
1292 static int stm32_dfsdm_audio_init(struct iio_dev *indio_dev)
1293 {
1294         struct iio_chan_spec *ch;
1295         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1296         struct stm32_dfsdm_channel *d_ch;
1297         int ret;
1298
1299         ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
1300         if (!ch)
1301                 return -ENOMEM;
1302
1303         ch->scan_index = 0;
1304
1305         ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
1306         if (ret < 0) {
1307                 dev_err(&indio_dev->dev, "Channels init failed\n");
1308                 return ret;
1309         }
1310         ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
1311
1312         d_ch = &adc->dfsdm->ch_list[ch->channel];
1313         if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
1314                 adc->spi_freq = adc->dfsdm->spi_master_freq;
1315
1316         indio_dev->num_channels = 1;
1317         indio_dev->channels = ch;
1318
1319         return stm32_dfsdm_dma_request(indio_dev);
1320 }
1321
1322 static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev)
1323 {
1324         struct iio_chan_spec *ch;
1325         struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1326         int num_ch;
1327         int ret, chan_idx;
1328
1329         adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
1330         ret = stm32_dfsdm_set_osrs(&adc->dfsdm->fl_list[adc->fl_id], 0,
1331                                    adc->oversamp);
1332         if (ret < 0)
1333                 return ret;
1334
1335         num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
1336                                              "st,adc-channels");
1337         if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
1338                 dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
1339                 return num_ch < 0 ? num_ch : -EINVAL;
1340         }
1341
1342         /* Bind to SD modulator IIO device */
1343         adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
1344         if (IS_ERR(adc->hwc))
1345                 return -EPROBE_DEFER;
1346
1347         ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
1348                           GFP_KERNEL);
1349         if (!ch)
1350                 return -ENOMEM;
1351
1352         for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
1353                 ch[chan_idx].scan_index = chan_idx;
1354                 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]);
1355                 if (ret < 0) {
1356                         dev_err(&indio_dev->dev, "Channels init failed\n");
1357                         return ret;
1358                 }
1359         }
1360
1361         indio_dev->num_channels = num_ch;
1362         indio_dev->channels = ch;
1363
1364         init_completion(&adc->completion);
1365
1366         /* Optionally request DMA */
1367         if (stm32_dfsdm_dma_request(indio_dev)) {
1368                 dev_dbg(&indio_dev->dev, "No DMA support\n");
1369                 return 0;
1370         }
1371
1372         ret = iio_triggered_buffer_setup(indio_dev,
1373                                          &iio_pollfunc_store_time,
1374                                          &stm32_dfsdm_adc_trigger_handler,
1375                                          &stm32_dfsdm_buffer_setup_ops);
1376         if (ret) {
1377                 stm32_dfsdm_dma_release(indio_dev);
1378                 dev_err(&indio_dev->dev, "buffer setup failed\n");
1379                 return ret;
1380         }
1381
1382         /* lptimer/timer hardware triggers */
1383         indio_dev->modes |= INDIO_HARDWARE_TRIGGERED;
1384
1385         return 0;
1386 }
1387
1388 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
1389         .type = DFSDM_IIO,
1390         .init = stm32_dfsdm_adc_init,
1391 };
1392
1393 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
1394         .type = DFSDM_AUDIO,
1395         .init = stm32_dfsdm_audio_init,
1396 };
1397
1398 static const struct of_device_id stm32_dfsdm_adc_match[] = {
1399         {
1400                 .compatible = "st,stm32-dfsdm-adc",
1401                 .data = &stm32h7_dfsdm_adc_data,
1402         },
1403         {
1404                 .compatible = "st,stm32-dfsdm-dmic",
1405                 .data = &stm32h7_dfsdm_audio_data,
1406         },
1407         {}
1408 };
1409
1410 static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
1411 {
1412         struct device *dev = &pdev->dev;
1413         struct stm32_dfsdm_adc *adc;
1414         struct device_node *np = dev->of_node;
1415         const struct stm32_dfsdm_dev_data *dev_data;
1416         struct iio_dev *iio;
1417         char *name;
1418         int ret, irq, val;
1419
1420         dev_data = of_device_get_match_data(dev);
1421         iio = devm_iio_device_alloc(dev, sizeof(*adc));
1422         if (!iio) {
1423                 dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
1424                 return -ENOMEM;
1425         }
1426
1427         adc = iio_priv(iio);
1428         adc->dfsdm = dev_get_drvdata(dev->parent);
1429
1430         iio->dev.parent = dev;
1431         iio->dev.of_node = np;
1432         iio->modes = INDIO_DIRECT_MODE;
1433
1434         platform_set_drvdata(pdev, adc);
1435
1436         ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
1437         if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
1438                 dev_err(dev, "Missing or bad reg property\n");
1439                 return -EINVAL;
1440         }
1441
1442         name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
1443         if (!name)
1444                 return -ENOMEM;
1445         if (dev_data->type == DFSDM_AUDIO) {
1446                 iio->info = &stm32_dfsdm_info_audio;
1447                 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
1448         } else {
1449                 iio->info = &stm32_dfsdm_info_adc;
1450                 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
1451         }
1452         iio->name = name;
1453
1454         /*
1455          * In a first step IRQs generated for channels are not treated.
1456          * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
1457          */
1458         irq = platform_get_irq(pdev, 0);
1459         ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
1460                                0, pdev->name, adc);
1461         if (ret < 0) {
1462                 dev_err(dev, "Failed to request IRQ\n");
1463                 return ret;
1464         }
1465
1466         ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
1467         if (ret < 0) {
1468                 dev_err(dev, "Failed to set filter order\n");
1469                 return ret;
1470         }
1471
1472         adc->dfsdm->fl_list[adc->fl_id].ford = val;
1473
1474         ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
1475         if (!ret)
1476                 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
1477
1478         adc->dev_data = dev_data;
1479         ret = dev_data->init(iio);
1480         if (ret < 0)
1481                 return ret;
1482
1483         ret = iio_device_register(iio);
1484         if (ret < 0)
1485                 goto err_cleanup;
1486
1487         if (dev_data->type == DFSDM_AUDIO) {
1488                 ret = of_platform_populate(np, NULL, NULL, dev);
1489                 if (ret < 0) {
1490                         dev_err(dev, "Failed to find an audio DAI\n");
1491                         goto err_unregister;
1492                 }
1493         }
1494
1495         return 0;
1496
1497 err_unregister:
1498         iio_device_unregister(iio);
1499 err_cleanup:
1500         stm32_dfsdm_dma_release(iio);
1501
1502         return ret;
1503 }
1504
1505 static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
1506 {
1507         struct stm32_dfsdm_adc *adc = platform_get_drvdata(pdev);
1508         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1509
1510         if (adc->dev_data->type == DFSDM_AUDIO)
1511                 of_platform_depopulate(&pdev->dev);
1512         iio_device_unregister(indio_dev);
1513         stm32_dfsdm_dma_release(indio_dev);
1514
1515         return 0;
1516 }
1517
1518 static int __maybe_unused stm32_dfsdm_adc_suspend(struct device *dev)
1519 {
1520         struct stm32_dfsdm_adc *adc = dev_get_drvdata(dev);
1521         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1522
1523         if (iio_buffer_enabled(indio_dev))
1524                 __stm32_dfsdm_predisable(indio_dev);
1525
1526         return 0;
1527 }
1528
1529 static int __maybe_unused stm32_dfsdm_adc_resume(struct device *dev)
1530 {
1531         struct stm32_dfsdm_adc *adc = dev_get_drvdata(dev);
1532         struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1533         const struct iio_chan_spec *chan;
1534         struct stm32_dfsdm_channel *ch;
1535         int i, ret;
1536
1537         /* restore channels configuration */
1538         for (i = 0; i < indio_dev->num_channels; i++) {
1539                 chan = indio_dev->channels + i;
1540                 ch = &adc->dfsdm->ch_list[chan->channel];
1541                 ret = stm32_dfsdm_chan_configure(adc->dfsdm, ch);
1542                 if (ret)
1543                         return ret;
1544         }
1545
1546         if (iio_buffer_enabled(indio_dev))
1547                 __stm32_dfsdm_postenable(indio_dev);
1548
1549         return 0;
1550 }
1551
1552 static SIMPLE_DEV_PM_OPS(stm32_dfsdm_adc_pm_ops,
1553                          stm32_dfsdm_adc_suspend, stm32_dfsdm_adc_resume);
1554
1555 static struct platform_driver stm32_dfsdm_adc_driver = {
1556         .driver = {
1557                 .name = "stm32-dfsdm-adc",
1558                 .of_match_table = stm32_dfsdm_adc_match,
1559                 .pm = &stm32_dfsdm_adc_pm_ops,
1560         },
1561         .probe = stm32_dfsdm_adc_probe,
1562         .remove = stm32_dfsdm_adc_remove,
1563 };
1564 module_platform_driver(stm32_dfsdm_adc_driver);
1565
1566 MODULE_DESCRIPTION("STM32 sigma delta ADC");
1567 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
1568 MODULE_LICENSE("GPL v2");