1 // SPDX-License-Identifier: GPL-2.0
3 * This file is part of STM32 ADC driver
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/iio/iio.h>
14 #include <linux/iio/buffer.h>
15 #include <linux/iio/timer/stm32-lptim-trigger.h>
16 #include <linux/iio/timer/stm32-timer-trigger.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/trigger_consumer.h>
19 #include <linux/iio/triggered_buffer.h>
20 #include <linux/interrupt.h>
22 #include <linux/iopoll.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
27 #include <linux/of_device.h>
29 #include "stm32-adc-core.h"
31 /* Number of linear calibration shadow registers / LINCALRDYW control bits */
32 #define STM32H7_LINCALFACT_NUM 6
34 /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
35 #define STM32H7_BOOST_CLKRATE 20000000UL
37 #define STM32_ADC_CH_MAX 20 /* max number of channels */
38 #define STM32_ADC_CH_SZ 10 /* max channel name size */
39 #define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */
40 #define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */
41 #define STM32_ADC_TIMEOUT_US 100000
42 #define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000))
43 #define STM32_ADC_HW_STOP_DELAY_MS 100
45 #define STM32_DMA_BUFFER_SIZE PAGE_SIZE
47 /* External trigger enable */
48 enum stm32_adc_exten {
50 STM32_EXTEN_HWTRIG_RISING_EDGE,
51 STM32_EXTEN_HWTRIG_FALLING_EDGE,
52 STM32_EXTEN_HWTRIG_BOTH_EDGES,
55 /* extsel - trigger mux selection value */
56 enum stm32_adc_extsel {
81 * struct stm32_adc_trig_info - ADC trigger info
82 * @name: name of the trigger, corresponding to its source
83 * @extsel: trigger selection
85 struct stm32_adc_trig_info {
87 enum stm32_adc_extsel extsel;
91 * struct stm32_adc_calib - optional adc calibration data
92 * @calfact_s: Calibration offset for single ended channels
93 * @calfact_d: Calibration offset in differential
94 * @lincalfact: Linearity calibration factor
95 * @calibrated: Indicates calibration status
97 struct stm32_adc_calib {
100 u32 lincalfact[STM32H7_LINCALFACT_NUM];
105 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc
106 * @reg: register offset
107 * @mask: bitfield mask
110 struct stm32_adc_regs {
117 * struct stm32_adc_regspec - stm32 registers definition
118 * @dr: data register offset
119 * @ier_eoc: interrupt enable register & eocie bitfield
120 * @isr_eoc: interrupt status register & eoc bitfield
121 * @sqr: reference to sequence registers array
122 * @exten: trigger control register & bitfield
123 * @extsel: trigger selection register & bitfield
124 * @res: resolution selection register & bitfield
125 * @smpr: smpr1 & smpr2 registers offset array
126 * @smp_bits: smpr1 & smpr2 index and bitfields
128 struct stm32_adc_regspec {
130 const struct stm32_adc_regs ier_eoc;
131 const struct stm32_adc_regs isr_eoc;
132 const struct stm32_adc_regs *sqr;
133 const struct stm32_adc_regs exten;
134 const struct stm32_adc_regs extsel;
135 const struct stm32_adc_regs res;
137 const struct stm32_adc_regs *smp_bits;
143 * struct stm32_adc_cfg - stm32 compatible configuration data
144 * @regs: registers descriptions
145 * @adc_info: per instance input channels definitions
146 * @trigs: external trigger sources
147 * @clk_required: clock is required
148 * @has_vregready: vregready status flag presence
149 * @prepare: optional prepare routine (power-up, enable)
150 * @start_conv: routine to start conversions
151 * @stop_conv: routine to stop conversions
152 * @unprepare: optional unprepare routine (disable, power-down)
153 * @smp_cycles: programmable sampling time (ADC clock cycles)
155 struct stm32_adc_cfg {
156 const struct stm32_adc_regspec *regs;
157 const struct stm32_adc_info *adc_info;
158 struct stm32_adc_trig_info *trigs;
161 int (*prepare)(struct stm32_adc *);
162 void (*start_conv)(struct stm32_adc *, bool dma);
163 void (*stop_conv)(struct stm32_adc *);
164 void (*unprepare)(struct stm32_adc *);
165 const unsigned int *smp_cycles;
169 * struct stm32_adc - private data of each ADC IIO instance
170 * @common: reference to ADC block common data
171 * @offset: ADC instance register offset in ADC block
172 * @cfg: compatible configuration data
173 * @completion: end of single conversion completion
174 * @buffer: data buffer
175 * @clk: clock for this adc instance
176 * @irq: interrupt for this adc instance
178 * @bufi: data buffer index
179 * @num_conv: expected number of scan conversions
180 * @res: data resolution (e.g. RES bitfield value)
181 * @trigger_polarity: external trigger polarity (e.g. exten)
182 * @dma_chan: dma channel
183 * @rx_buf: dma rx buffer cpu address
184 * @rx_dma_buf: dma rx buffer bus address
185 * @rx_buf_sz: dma rx buffer size
186 * @difsel: bitmask to set single-ended/differential channel
187 * @pcsel: bitmask to preselect channels on some devices
188 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2)
189 * @cal: optional calibration data on some devices
190 * @chan_name: channel name array
193 struct stm32_adc_common *common;
195 const struct stm32_adc_cfg *cfg;
196 struct completion completion;
197 u16 buffer[STM32_ADC_MAX_SQ];
200 spinlock_t lock; /* interrupt lock */
202 unsigned int num_conv;
204 u32 trigger_polarity;
205 struct dma_chan *dma_chan;
207 dma_addr_t rx_dma_buf;
208 unsigned int rx_buf_sz;
212 struct stm32_adc_calib cal;
213 char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ];
216 struct stm32_adc_diff_channel {
222 * struct stm32_adc_info - stm32 ADC, per instance config data
223 * @max_channels: Number of channels
224 * @resolutions: available resolutions
225 * @num_res: number of available resolutions
227 struct stm32_adc_info {
229 const unsigned int *resolutions;
230 const unsigned int num_res;
233 static const unsigned int stm32f4_adc_resolutions[] = {
234 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */
238 /* stm32f4 can have up to 16 channels */
239 static const struct stm32_adc_info stm32f4_adc_info = {
241 .resolutions = stm32f4_adc_resolutions,
242 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions),
245 static const unsigned int stm32h7_adc_resolutions[] = {
246 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */
250 /* stm32h7 can have up to 20 channels */
251 static const struct stm32_adc_info stm32h7_adc_info = {
252 .max_channels = STM32_ADC_CH_MAX,
253 .resolutions = stm32h7_adc_resolutions,
254 .num_res = ARRAY_SIZE(stm32h7_adc_resolutions),
258 * stm32f4_sq - describe regular sequence registers
259 * - L: sequence len (register & bit field)
260 * - SQ1..SQ16: sequence entries (register & bit field)
262 static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = {
263 /* L: len bit field description to be kept as first element */
264 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 },
265 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
266 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 },
267 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 },
268 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 },
269 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 },
270 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 },
271 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 },
272 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 },
273 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 },
274 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 },
275 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 },
276 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 },
277 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 },
278 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 },
279 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 },
280 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 },
281 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 },
284 /* STM32F4 external trigger sources for all instances */
285 static struct stm32_adc_trig_info stm32f4_adc_trigs[] = {
286 { TIM1_CH1, STM32_EXT0 },
287 { TIM1_CH2, STM32_EXT1 },
288 { TIM1_CH3, STM32_EXT2 },
289 { TIM2_CH2, STM32_EXT3 },
290 { TIM2_CH3, STM32_EXT4 },
291 { TIM2_CH4, STM32_EXT5 },
292 { TIM2_TRGO, STM32_EXT6 },
293 { TIM3_CH1, STM32_EXT7 },
294 { TIM3_TRGO, STM32_EXT8 },
295 { TIM4_CH4, STM32_EXT9 },
296 { TIM5_CH1, STM32_EXT10 },
297 { TIM5_CH2, STM32_EXT11 },
298 { TIM5_CH3, STM32_EXT12 },
299 { TIM8_CH1, STM32_EXT13 },
300 { TIM8_TRGO, STM32_EXT14 },
305 * stm32f4_smp_bits[] - describe sampling time register index & bit fields
306 * Sorted so it can be indexed by channel number.
308 static const struct stm32_adc_regs stm32f4_smp_bits[] = {
309 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */
310 { 1, GENMASK(2, 0), 0 },
311 { 1, GENMASK(5, 3), 3 },
312 { 1, GENMASK(8, 6), 6 },
313 { 1, GENMASK(11, 9), 9 },
314 { 1, GENMASK(14, 12), 12 },
315 { 1, GENMASK(17, 15), 15 },
316 { 1, GENMASK(20, 18), 18 },
317 { 1, GENMASK(23, 21), 21 },
318 { 1, GENMASK(26, 24), 24 },
319 { 1, GENMASK(29, 27), 27 },
320 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */
321 { 0, GENMASK(2, 0), 0 },
322 { 0, GENMASK(5, 3), 3 },
323 { 0, GENMASK(8, 6), 6 },
324 { 0, GENMASK(11, 9), 9 },
325 { 0, GENMASK(14, 12), 12 },
326 { 0, GENMASK(17, 15), 15 },
327 { 0, GENMASK(20, 18), 18 },
328 { 0, GENMASK(23, 21), 21 },
329 { 0, GENMASK(26, 24), 24 },
332 /* STM32F4 programmable sampling time (ADC clock cycles) */
333 static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
334 3, 15, 28, 56, 84, 112, 144, 480,
337 static const struct stm32_adc_regspec stm32f4_adc_regspec = {
338 .dr = STM32F4_ADC_DR,
339 .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE },
340 .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC },
342 .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT },
343 .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK,
344 STM32F4_EXTSEL_SHIFT },
345 .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT },
346 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 },
347 .smp_bits = stm32f4_smp_bits,
350 static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = {
351 /* L: len bit field description to be kept as first element */
352 { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 },
353 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */
354 { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 },
355 { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 },
356 { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 },
357 { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 },
358 { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 },
359 { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 },
360 { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 },
361 { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 },
362 { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 },
363 { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 },
364 { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 },
365 { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 },
366 { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 },
367 { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 },
368 { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 },
369 { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 },
372 /* STM32H7 external trigger sources for all instances */
373 static struct stm32_adc_trig_info stm32h7_adc_trigs[] = {
374 { TIM1_CH1, STM32_EXT0 },
375 { TIM1_CH2, STM32_EXT1 },
376 { TIM1_CH3, STM32_EXT2 },
377 { TIM2_CH2, STM32_EXT3 },
378 { TIM3_TRGO, STM32_EXT4 },
379 { TIM4_CH4, STM32_EXT5 },
380 { TIM8_TRGO, STM32_EXT7 },
381 { TIM8_TRGO2, STM32_EXT8 },
382 { TIM1_TRGO, STM32_EXT9 },
383 { TIM1_TRGO2, STM32_EXT10 },
384 { TIM2_TRGO, STM32_EXT11 },
385 { TIM4_TRGO, STM32_EXT12 },
386 { TIM6_TRGO, STM32_EXT13 },
387 { TIM15_TRGO, STM32_EXT14 },
388 { TIM3_CH4, STM32_EXT15 },
389 { LPTIM1_OUT, STM32_EXT18 },
390 { LPTIM2_OUT, STM32_EXT19 },
391 { LPTIM3_OUT, STM32_EXT20 },
396 * stm32h7_smp_bits - describe sampling time register index & bit fields
397 * Sorted so it can be indexed by channel number.
399 static const struct stm32_adc_regs stm32h7_smp_bits[] = {
400 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */
401 { 0, GENMASK(2, 0), 0 },
402 { 0, GENMASK(5, 3), 3 },
403 { 0, GENMASK(8, 6), 6 },
404 { 0, GENMASK(11, 9), 9 },
405 { 0, GENMASK(14, 12), 12 },
406 { 0, GENMASK(17, 15), 15 },
407 { 0, GENMASK(20, 18), 18 },
408 { 0, GENMASK(23, 21), 21 },
409 { 0, GENMASK(26, 24), 24 },
410 { 0, GENMASK(29, 27), 27 },
411 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */
412 { 1, GENMASK(2, 0), 0 },
413 { 1, GENMASK(5, 3), 3 },
414 { 1, GENMASK(8, 6), 6 },
415 { 1, GENMASK(11, 9), 9 },
416 { 1, GENMASK(14, 12), 12 },
417 { 1, GENMASK(17, 15), 15 },
418 { 1, GENMASK(20, 18), 18 },
419 { 1, GENMASK(23, 21), 21 },
420 { 1, GENMASK(26, 24), 24 },
421 { 1, GENMASK(29, 27), 27 },
424 /* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */
425 static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = {
426 1, 2, 8, 16, 32, 64, 387, 810,
429 static const struct stm32_adc_regspec stm32h7_adc_regspec = {
430 .dr = STM32H7_ADC_DR,
431 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE },
432 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC },
434 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT },
435 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK,
436 STM32H7_EXTSEL_SHIFT },
437 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT },
438 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 },
439 .smp_bits = stm32h7_smp_bits,
443 * STM32 ADC registers access routines
444 * @adc: stm32 adc instance
445 * @reg: reg offset in adc instance
447 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp.
448 * for adc1, adc2 and adc3.
450 static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg)
452 return readl_relaxed(adc->common->base + adc->offset + reg);
455 #define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr)
457 #define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \
458 readx_poll_timeout(stm32_adc_readl_addr, reg, val, \
459 cond, sleep_us, timeout_us)
461 static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg)
463 return readw_relaxed(adc->common->base + adc->offset + reg);
466 static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val)
468 writel_relaxed(val, adc->common->base + adc->offset + reg);
471 static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits)
475 spin_lock_irqsave(&adc->lock, flags);
476 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits);
477 spin_unlock_irqrestore(&adc->lock, flags);
480 static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits)
484 spin_lock_irqsave(&adc->lock, flags);
485 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits);
486 spin_unlock_irqrestore(&adc->lock, flags);
490 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
491 * @adc: stm32 adc instance
493 static void stm32_adc_conv_irq_enable(struct stm32_adc *adc)
495 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg,
496 adc->cfg->regs->ier_eoc.mask);
500 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
501 * @adc: stm32 adc instance
503 static void stm32_adc_conv_irq_disable(struct stm32_adc *adc)
505 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg,
506 adc->cfg->regs->ier_eoc.mask);
509 static void stm32_adc_set_res(struct stm32_adc *adc)
511 const struct stm32_adc_regs *res = &adc->cfg->regs->res;
514 val = stm32_adc_readl(adc, res->reg);
515 val = (val & ~res->mask) | (adc->res << res->shift);
516 stm32_adc_writel(adc, res->reg, val);
519 static int stm32_adc_hw_stop(struct device *dev)
521 struct stm32_adc *adc = dev_get_drvdata(dev);
523 if (adc->cfg->unprepare)
524 adc->cfg->unprepare(adc);
527 clk_disable_unprepare(adc->clk);
532 static int stm32_adc_hw_start(struct device *dev)
534 struct stm32_adc *adc = dev_get_drvdata(dev);
538 ret = clk_prepare_enable(adc->clk);
543 stm32_adc_set_res(adc);
545 if (adc->cfg->prepare) {
546 ret = adc->cfg->prepare(adc);
555 clk_disable_unprepare(adc->clk);
561 * stm32f4_adc_start_conv() - Start conversions for regular channels.
562 * @adc: stm32 adc instance
563 * @dma: use dma to transfer conversion result
565 * Start conversions for regular channels.
566 * Also take care of normal or DMA mode. Circular DMA may be used for regular
567 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct
568 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA).
570 static void stm32f4_adc_start_conv(struct stm32_adc *adc, bool dma)
572 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
575 stm32_adc_set_bits(adc, STM32F4_ADC_CR2,
576 STM32F4_DMA | STM32F4_DDS);
578 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON);
580 /* Wait for Power-up time (tSTAB from datasheet) */
583 /* Software start ? (e.g. trigger detection disabled ?) */
584 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK))
585 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART);
588 static void stm32f4_adc_stop_conv(struct stm32_adc *adc)
590 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK);
591 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT);
593 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN);
594 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2,
595 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS);
598 static void stm32h7_adc_start_conv(struct stm32_adc *adc, bool dma)
600 enum stm32h7_adc_dmngt dmngt;
605 dmngt = STM32H7_DMNGT_DMA_CIRC;
607 dmngt = STM32H7_DMNGT_DR_ONLY;
609 spin_lock_irqsave(&adc->lock, flags);
610 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR);
611 val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT);
612 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val);
613 spin_unlock_irqrestore(&adc->lock, flags);
615 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART);
618 static void stm32h7_adc_stop_conv(struct stm32_adc *adc)
620 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
624 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP);
626 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
627 !(val & (STM32H7_ADSTART)),
628 100, STM32_ADC_TIMEOUT_US);
630 dev_warn(&indio_dev->dev, "stop failed\n");
632 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
635 static int stm32h7_adc_exit_pwr_down(struct stm32_adc *adc)
637 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
641 /* Exit deep power down, then enable ADC voltage regulator */
642 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
643 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN);
645 if (adc->common->rate > STM32H7_BOOST_CLKRATE)
646 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
648 /* Wait for startup time */
649 if (!adc->cfg->has_vregready) {
650 usleep_range(10, 20);
654 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
655 val & STM32MP1_VREGREADY, 100,
656 STM32_ADC_TIMEOUT_US);
658 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
659 dev_err(&indio_dev->dev, "Failed to exit power down\n");
665 static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc)
667 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
669 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
670 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
673 static int stm32h7_adc_enable(struct stm32_adc *adc)
675 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
679 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN);
681 /* Poll for ADRDY to be set (after adc startup time) */
682 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
684 100, STM32_ADC_TIMEOUT_US);
686 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
687 dev_err(&indio_dev->dev, "Failed to enable ADC\n");
689 /* Clear ADRDY by writing one */
690 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY);
696 static void stm32h7_adc_disable(struct stm32_adc *adc)
698 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
702 /* Disable ADC and wait until it's effectively disabled */
703 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
704 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
705 !(val & STM32H7_ADEN), 100,
706 STM32_ADC_TIMEOUT_US);
708 dev_warn(&indio_dev->dev, "Failed to disable\n");
712 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
713 * @adc: stm32 adc instance
714 * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable
716 static int stm32h7_adc_read_selfcalib(struct stm32_adc *adc)
718 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
720 u32 lincalrdyw_mask, val;
722 /* Read linearity calibration */
723 lincalrdyw_mask = STM32H7_LINCALRDYW6;
724 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
725 /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */
726 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
728 /* Poll: wait calib data to be ready in CALFACT2 register */
729 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
730 !(val & lincalrdyw_mask),
731 100, STM32_ADC_TIMEOUT_US);
733 dev_err(&indio_dev->dev, "Failed to read calfact\n");
737 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
738 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK);
739 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT;
741 lincalrdyw_mask >>= 1;
744 /* Read offset calibration */
745 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT);
746 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK);
747 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT;
748 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK);
749 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT;
750 adc->cal.calibrated = true;
756 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
757 * @adc: stm32 adc instance
758 * Note: ADC must be enabled, with no on-going conversions.
760 static int stm32h7_adc_restore_selfcalib(struct stm32_adc *adc)
762 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
764 u32 lincalrdyw_mask, val;
766 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) |
767 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT);
768 stm32_adc_writel(adc, STM32H7_ADC_CALFACT, val);
770 lincalrdyw_mask = STM32H7_LINCALRDYW6;
771 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) {
773 * Write saved calibration data to shadow registers:
774 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger
775 * data write. Then poll to wait for complete transfer.
777 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT;
778 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val);
779 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
780 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
781 val & lincalrdyw_mask,
782 100, STM32_ADC_TIMEOUT_US);
784 dev_err(&indio_dev->dev, "Failed to write calfact\n");
789 * Read back calibration data, has two effects:
790 * - It ensures bits LINCALRDYW[6..1] are kept cleared
791 * for next time calibration needs to be restored.
792 * - BTW, bit clear triggers a read, then check data has been
795 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask);
796 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
797 !(val & lincalrdyw_mask),
798 100, STM32_ADC_TIMEOUT_US);
800 dev_err(&indio_dev->dev, "Failed to read calfact\n");
803 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2);
804 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) {
805 dev_err(&indio_dev->dev, "calfact not consistent\n");
809 lincalrdyw_mask >>= 1;
816 * Fixed timeout value for ADC calibration.
818 * - low clock frequency
819 * - maximum prescalers
820 * Calibration requires:
821 * - 131,072 ADC clock cycle for the linear calibration
822 * - 20 ADC clock cycle for the offset calibration
824 * Set to 100ms for now
826 #define STM32H7_ADC_CALIB_TIMEOUT_US 100000
829 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC
830 * @adc: stm32 adc instance
831 * Note: Must be called once ADC is out of power down.
833 static int stm32h7_adc_selfcalib(struct stm32_adc *adc)
835 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
839 if (adc->cal.calibrated)
843 * Select calibration mode:
844 * - Offset calibration for single ended inputs
845 * - No linearity calibration (do it later, before reading it)
847 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF);
848 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN);
850 /* Start calibration, then wait for completion */
851 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
852 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
853 !(val & STM32H7_ADCAL), 100,
854 STM32H7_ADC_CALIB_TIMEOUT_US);
856 dev_err(&indio_dev->dev, "calibration failed\n");
861 * Select calibration mode, then start calibration:
862 * - Offset calibration for differential input
863 * - Linearity calibration (needs to be done only once for single/diff)
864 * will run simultaneously with offset calibration.
866 stm32_adc_set_bits(adc, STM32H7_ADC_CR,
867 STM32H7_ADCALDIF | STM32H7_ADCALLIN);
868 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL);
869 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
870 !(val & STM32H7_ADCAL), 100,
871 STM32H7_ADC_CALIB_TIMEOUT_US);
873 dev_err(&indio_dev->dev, "calibration failed\n");
878 stm32_adc_clr_bits(adc, STM32H7_ADC_CR,
879 STM32H7_ADCALDIF | STM32H7_ADCALLIN);
885 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
886 * @adc: stm32 adc instance
887 * Leave power down mode.
888 * Configure channels as single ended or differential before enabling ADC.
890 * Restore calibration data.
891 * Pre-select channels that may be used in PCSEL (required by input MUX / IO):
892 * - Only one input is selected for single ended (e.g. 'vinp')
893 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn')
895 static int stm32h7_adc_prepare(struct stm32_adc *adc)
899 ret = stm32h7_adc_exit_pwr_down(adc);
903 ret = stm32h7_adc_selfcalib(adc);
908 stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel);
910 ret = stm32h7_adc_enable(adc);
914 /* Either restore or read calibration result for future reference */
916 ret = stm32h7_adc_restore_selfcalib(adc);
918 ret = stm32h7_adc_read_selfcalib(adc);
922 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel);
927 stm32h7_adc_disable(adc);
929 stm32h7_adc_enter_pwr_down(adc);
934 static void stm32h7_adc_unprepare(struct stm32_adc *adc)
936 stm32h7_adc_disable(adc);
937 stm32h7_adc_enter_pwr_down(adc);
941 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
942 * @indio_dev: IIO device
943 * @scan_mask: channels to be converted
945 * Conversion sequence :
946 * Apply sampling time settings for all channels.
947 * Configure ADC scan sequence based on selected channels in scan_mask.
948 * Add channels to SQR registers, from scan_mask LSB to MSB, then
949 * program sequence len.
951 static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev,
952 const unsigned long *scan_mask)
954 struct stm32_adc *adc = iio_priv(indio_dev);
955 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr;
956 const struct iio_chan_spec *chan;
960 /* Apply sampling time settings */
961 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]);
962 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]);
964 for_each_set_bit(bit, scan_mask, indio_dev->masklength) {
965 chan = indio_dev->channels + bit;
967 * Assign one channel per SQ entry in regular
968 * sequence, starting with SQ1.
971 if (i > STM32_ADC_MAX_SQ)
974 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n",
975 __func__, chan->channel, i);
977 val = stm32_adc_readl(adc, sqr[i].reg);
979 val |= chan->channel << sqr[i].shift;
980 stm32_adc_writel(adc, sqr[i].reg, val);
987 val = stm32_adc_readl(adc, sqr[0].reg);
989 val |= ((i - 1) << sqr[0].shift);
990 stm32_adc_writel(adc, sqr[0].reg, val);
996 * stm32_adc_get_trig_extsel() - Get external trigger selection
997 * @indio_dev: IIO device structure
1000 * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
1002 static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev,
1003 struct iio_trigger *trig)
1005 struct stm32_adc *adc = iio_priv(indio_dev);
1008 /* lookup triggers registered by stm32 timer trigger driver */
1009 for (i = 0; adc->cfg->trigs[i].name; i++) {
1011 * Checking both stm32 timer trigger type and trig name
1012 * should be safe against arbitrary trigger names.
1014 if ((is_stm32_timer_trigger(trig) ||
1015 is_stm32_lptim_trigger(trig)) &&
1016 !strcmp(adc->cfg->trigs[i].name, trig->name)) {
1017 return adc->cfg->trigs[i].extsel;
1025 * stm32_adc_set_trig() - Set a regular trigger
1026 * @indio_dev: IIO device
1027 * @trig: IIO trigger
1029 * Set trigger source/polarity (e.g. SW, or HW with polarity) :
1030 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
1031 * - if HW trigger enabled, set source & polarity
1033 static int stm32_adc_set_trig(struct iio_dev *indio_dev,
1034 struct iio_trigger *trig)
1036 struct stm32_adc *adc = iio_priv(indio_dev);
1037 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG;
1038 unsigned long flags;
1042 ret = stm32_adc_get_trig_extsel(indio_dev, trig);
1046 /* set trigger source and polarity (default to rising edge) */
1048 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE;
1051 spin_lock_irqsave(&adc->lock, flags);
1052 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg);
1053 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask);
1054 val |= exten << adc->cfg->regs->exten.shift;
1055 val |= extsel << adc->cfg->regs->extsel.shift;
1056 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val);
1057 spin_unlock_irqrestore(&adc->lock, flags);
1062 static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev,
1063 const struct iio_chan_spec *chan,
1066 struct stm32_adc *adc = iio_priv(indio_dev);
1068 adc->trigger_polarity = type;
1073 static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev,
1074 const struct iio_chan_spec *chan)
1076 struct stm32_adc *adc = iio_priv(indio_dev);
1078 return adc->trigger_polarity;
1081 static const char * const stm32_trig_pol_items[] = {
1082 "rising-edge", "falling-edge", "both-edges",
1085 static const struct iio_enum stm32_adc_trig_pol = {
1086 .items = stm32_trig_pol_items,
1087 .num_items = ARRAY_SIZE(stm32_trig_pol_items),
1088 .get = stm32_adc_get_trig_pol,
1089 .set = stm32_adc_set_trig_pol,
1093 * stm32_adc_single_conv() - Performs a single conversion
1094 * @indio_dev: IIO device
1095 * @chan: IIO channel
1096 * @res: conversion result
1098 * The function performs a single conversion on a given channel:
1099 * - Apply sampling time settings
1100 * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
1102 * - Start conversion, then wait for interrupt completion.
1104 static int stm32_adc_single_conv(struct iio_dev *indio_dev,
1105 const struct iio_chan_spec *chan,
1108 struct stm32_adc *adc = iio_priv(indio_dev);
1109 struct device *dev = indio_dev->dev.parent;
1110 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1115 reinit_completion(&adc->completion);
1119 ret = pm_runtime_get_sync(dev);
1121 pm_runtime_put_noidle(dev);
1125 /* Apply sampling time settings */
1126 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]);
1127 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]);
1129 /* Program chan number in regular sequence (SQ1) */
1130 val = stm32_adc_readl(adc, regs->sqr[1].reg);
1131 val &= ~regs->sqr[1].mask;
1132 val |= chan->channel << regs->sqr[1].shift;
1133 stm32_adc_writel(adc, regs->sqr[1].reg, val);
1135 /* Set regular sequence len (0 for 1 conversion) */
1136 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask);
1138 /* Trigger detection disabled (conversion can be launched in SW) */
1139 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask);
1141 stm32_adc_conv_irq_enable(adc);
1143 adc->cfg->start_conv(adc, false);
1145 timeout = wait_for_completion_interruptible_timeout(
1146 &adc->completion, STM32_ADC_TIMEOUT);
1149 } else if (timeout < 0) {
1152 *res = adc->buffer[0];
1156 adc->cfg->stop_conv(adc);
1158 stm32_adc_conv_irq_disable(adc);
1160 pm_runtime_mark_last_busy(dev);
1161 pm_runtime_put_autosuspend(dev);
1166 static int stm32_adc_read_raw(struct iio_dev *indio_dev,
1167 struct iio_chan_spec const *chan,
1168 int *val, int *val2, long mask)
1170 struct stm32_adc *adc = iio_priv(indio_dev);
1174 case IIO_CHAN_INFO_RAW:
1175 ret = iio_device_claim_direct_mode(indio_dev);
1178 if (chan->type == IIO_VOLTAGE)
1179 ret = stm32_adc_single_conv(indio_dev, chan, val);
1182 iio_device_release_direct_mode(indio_dev);
1185 case IIO_CHAN_INFO_SCALE:
1186 if (chan->differential) {
1187 *val = adc->common->vref_mv * 2;
1188 *val2 = chan->scan_type.realbits;
1190 *val = adc->common->vref_mv;
1191 *val2 = chan->scan_type.realbits;
1193 return IIO_VAL_FRACTIONAL_LOG2;
1195 case IIO_CHAN_INFO_OFFSET:
1196 if (chan->differential)
1197 /* ADC_full_scale / 2 */
1198 *val = -((1 << chan->scan_type.realbits) / 2);
1208 static irqreturn_t stm32_adc_isr(int irq, void *data)
1210 struct stm32_adc *adc = data;
1211 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1212 const struct stm32_adc_regspec *regs = adc->cfg->regs;
1213 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg);
1215 if (status & regs->isr_eoc.mask) {
1216 /* Reading DR also clears EOC status flag */
1217 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr);
1218 if (iio_buffer_enabled(indio_dev)) {
1220 if (adc->bufi >= adc->num_conv) {
1221 stm32_adc_conv_irq_disable(adc);
1222 iio_trigger_poll(indio_dev->trig);
1225 complete(&adc->completion);
1234 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1235 * @indio_dev: IIO device
1236 * @trig: new trigger
1238 * Returns: 0 if trig matches one of the triggers registered by stm32 adc
1239 * driver, -EINVAL otherwise.
1241 static int stm32_adc_validate_trigger(struct iio_dev *indio_dev,
1242 struct iio_trigger *trig)
1244 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1247 static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1249 struct stm32_adc *adc = iio_priv(indio_dev);
1250 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2;
1251 unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE;
1254 * dma cyclic transfers are used, buffer is split into two periods.
1256 * - always one buffer (period) dma is working on
1257 * - one buffer (period) driver can push with iio_trigger_poll().
1259 watermark = min(watermark, val * (unsigned)(sizeof(u16)));
1260 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv);
1265 static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev,
1266 const unsigned long *scan_mask)
1268 struct stm32_adc *adc = iio_priv(indio_dev);
1269 struct device *dev = indio_dev->dev.parent;
1272 ret = pm_runtime_get_sync(dev);
1274 pm_runtime_put_noidle(dev);
1278 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength);
1280 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
1281 pm_runtime_mark_last_busy(dev);
1282 pm_runtime_put_autosuspend(dev);
1287 static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
1288 const struct of_phandle_args *iiospec)
1292 for (i = 0; i < indio_dev->num_channels; i++)
1293 if (indio_dev->channels[i].channel == iiospec->args[0])
1300 * stm32_adc_debugfs_reg_access - read or write register value
1301 * @indio_dev: IIO device structure
1302 * @reg: register offset
1303 * @writeval: value to write
1304 * @readval: value to read
1306 * To read a value from an ADC register:
1307 * echo [ADC reg offset] > direct_reg_access
1308 * cat direct_reg_access
1310 * To write a value in a ADC register:
1311 * echo [ADC_reg_offset] [value] > direct_reg_access
1313 static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev,
1314 unsigned reg, unsigned writeval,
1317 struct stm32_adc *adc = iio_priv(indio_dev);
1318 struct device *dev = indio_dev->dev.parent;
1321 ret = pm_runtime_get_sync(dev);
1323 pm_runtime_put_noidle(dev);
1328 stm32_adc_writel(adc, reg, writeval);
1330 *readval = stm32_adc_readl(adc, reg);
1332 pm_runtime_mark_last_busy(dev);
1333 pm_runtime_put_autosuspend(dev);
1338 static const struct iio_info stm32_adc_iio_info = {
1339 .read_raw = stm32_adc_read_raw,
1340 .validate_trigger = stm32_adc_validate_trigger,
1341 .hwfifo_set_watermark = stm32_adc_set_watermark,
1342 .update_scan_mode = stm32_adc_update_scan_mode,
1343 .debugfs_reg_access = stm32_adc_debugfs_reg_access,
1344 .of_xlate = stm32_adc_of_xlate,
1347 static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
1349 struct dma_tx_state state;
1350 enum dma_status status;
1352 status = dmaengine_tx_status(adc->dma_chan,
1353 adc->dma_chan->cookie,
1355 if (status == DMA_IN_PROGRESS) {
1356 /* Residue is size in bytes from end of buffer */
1357 unsigned int i = adc->rx_buf_sz - state.residue;
1360 /* Return available bytes */
1362 size = i - adc->bufi;
1364 size = adc->rx_buf_sz + i - adc->bufi;
1372 static void stm32_adc_dma_buffer_done(void *data)
1374 struct iio_dev *indio_dev = data;
1376 iio_trigger_poll_chained(indio_dev->trig);
1379 static int stm32_adc_dma_start(struct iio_dev *indio_dev)
1381 struct stm32_adc *adc = iio_priv(indio_dev);
1382 struct dma_async_tx_descriptor *desc;
1383 dma_cookie_t cookie;
1389 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
1390 adc->rx_buf_sz, adc->rx_buf_sz / 2);
1392 /* Prepare a DMA cyclic transaction */
1393 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
1395 adc->rx_buf_sz, adc->rx_buf_sz / 2,
1397 DMA_PREP_INTERRUPT);
1401 desc->callback = stm32_adc_dma_buffer_done;
1402 desc->callback_param = indio_dev;
1404 cookie = dmaengine_submit(desc);
1405 ret = dma_submit_error(cookie);
1407 dmaengine_terminate_sync(adc->dma_chan);
1411 /* Issue pending DMA requests */
1412 dma_async_issue_pending(adc->dma_chan);
1417 static int __stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
1419 struct stm32_adc *adc = iio_priv(indio_dev);
1420 struct device *dev = indio_dev->dev.parent;
1423 ret = pm_runtime_get_sync(dev);
1425 pm_runtime_put_noidle(dev);
1429 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig);
1431 dev_err(&indio_dev->dev, "Can't set trigger\n");
1435 ret = stm32_adc_dma_start(indio_dev);
1437 dev_err(&indio_dev->dev, "Can't start dma\n");
1441 /* Reset adc buffer index */
1445 stm32_adc_conv_irq_enable(adc);
1447 adc->cfg->start_conv(adc, !!adc->dma_chan);
1452 stm32_adc_set_trig(indio_dev, NULL);
1454 pm_runtime_mark_last_busy(dev);
1455 pm_runtime_put_autosuspend(dev);
1460 static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev)
1464 ret = iio_triggered_buffer_postenable(indio_dev);
1468 ret = __stm32_adc_buffer_postenable(indio_dev);
1470 iio_triggered_buffer_predisable(indio_dev);
1475 static void __stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
1477 struct stm32_adc *adc = iio_priv(indio_dev);
1478 struct device *dev = indio_dev->dev.parent;
1480 adc->cfg->stop_conv(adc);
1482 stm32_adc_conv_irq_disable(adc);
1485 dmaengine_terminate_sync(adc->dma_chan);
1487 if (stm32_adc_set_trig(indio_dev, NULL))
1488 dev_err(&indio_dev->dev, "Can't clear trigger\n");
1490 pm_runtime_mark_last_busy(dev);
1491 pm_runtime_put_autosuspend(dev);
1494 static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev)
1498 __stm32_adc_buffer_predisable(indio_dev);
1500 ret = iio_triggered_buffer_predisable(indio_dev);
1502 dev_err(&indio_dev->dev, "predisable failed\n");
1507 static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = {
1508 .postenable = &stm32_adc_buffer_postenable,
1509 .predisable = &stm32_adc_buffer_predisable,
1512 static irqreturn_t stm32_adc_trigger_handler(int irq, void *p)
1514 struct iio_poll_func *pf = p;
1515 struct iio_dev *indio_dev = pf->indio_dev;
1516 struct stm32_adc *adc = iio_priv(indio_dev);
1518 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi);
1520 if (!adc->dma_chan) {
1521 /* reset buffer index */
1523 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer,
1526 int residue = stm32_adc_dma_residue(adc);
1528 while (residue >= indio_dev->scan_bytes) {
1529 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi];
1531 iio_push_to_buffers_with_timestamp(indio_dev, buffer,
1533 residue -= indio_dev->scan_bytes;
1534 adc->bufi += indio_dev->scan_bytes;
1535 if (adc->bufi >= adc->rx_buf_sz)
1540 iio_trigger_notify_done(indio_dev->trig);
1542 /* re-enable eoc irq */
1544 stm32_adc_conv_irq_enable(adc);
1549 static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = {
1550 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol),
1552 .name = "trigger_polarity_available",
1553 .shared = IIO_SHARED_BY_ALL,
1554 .read = iio_enum_available_read,
1555 .private = (uintptr_t)&stm32_adc_trig_pol,
1560 static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev)
1562 struct device_node *node = indio_dev->dev.of_node;
1563 struct stm32_adc *adc = iio_priv(indio_dev);
1567 if (of_property_read_u32(node, "assigned-resolution-bits", &res))
1568 res = adc->cfg->adc_info->resolutions[0];
1570 for (i = 0; i < adc->cfg->adc_info->num_res; i++)
1571 if (res == adc->cfg->adc_info->resolutions[i])
1573 if (i >= adc->cfg->adc_info->num_res) {
1574 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);
1578 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res);
1584 static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns)
1586 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel];
1587 u32 period_ns, shift = smpr->shift, mask = smpr->mask;
1588 unsigned int smp, r = smpr->reg;
1590 /* Determine sampling time (ADC clock cycles) */
1591 period_ns = NSEC_PER_SEC / adc->common->rate;
1592 for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++)
1593 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns)
1595 if (smp > STM32_ADC_MAX_SMP)
1596 smp = STM32_ADC_MAX_SMP;
1598 /* pre-build sampling time registers (e.g. smpr1, smpr2) */
1599 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift);
1602 static void stm32_adc_chan_init_one(struct iio_dev *indio_dev,
1603 struct iio_chan_spec *chan, u32 vinp,
1604 u32 vinn, int scan_index, bool differential)
1606 struct stm32_adc *adc = iio_priv(indio_dev);
1607 char *name = adc->chan_name[vinp];
1609 chan->type = IIO_VOLTAGE;
1610 chan->channel = vinp;
1612 chan->differential = 1;
1613 chan->channel2 = vinn;
1614 snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn);
1616 snprintf(name, STM32_ADC_CH_SZ, "in%d", vinp);
1618 chan->datasheet_name = name;
1619 chan->scan_index = scan_index;
1621 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1622 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
1623 BIT(IIO_CHAN_INFO_OFFSET);
1624 chan->scan_type.sign = 'u';
1625 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res];
1626 chan->scan_type.storagebits = 16;
1627 chan->ext_info = stm32_adc_ext_info;
1629 /* pre-build selected channels mask */
1630 adc->pcsel |= BIT(chan->channel);
1632 /* pre-build diff channels mask */
1633 adc->difsel |= BIT(chan->channel);
1634 /* Also add negative input to pre-selected channels */
1635 adc->pcsel |= BIT(chan->channel2);
1639 static int stm32_adc_chan_of_init(struct iio_dev *indio_dev)
1641 struct device_node *node = indio_dev->dev.of_node;
1642 struct stm32_adc *adc = iio_priv(indio_dev);
1643 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
1644 struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX];
1645 struct property *prop;
1647 struct iio_chan_spec *channels;
1648 int scan_index = 0, num_channels = 0, num_diff = 0, ret, i;
1651 ret = of_property_count_u32_elems(node, "st,adc-channels");
1652 if (ret > adc_info->max_channels) {
1653 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
1655 } else if (ret > 0) {
1656 num_channels += ret;
1659 ret = of_property_count_elems_of_size(node, "st,adc-diff-channels",
1661 if (ret > adc_info->max_channels) {
1662 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n");
1664 } else if (ret > 0) {
1665 int size = ret * sizeof(*diff) / sizeof(u32);
1668 num_channels += ret;
1669 ret = of_property_read_u32_array(node, "st,adc-diff-channels",
1675 if (!num_channels) {
1676 dev_err(&indio_dev->dev, "No channels configured\n");
1680 /* Optional sample time is provided either for each, or all channels */
1681 ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs");
1682 if (ret > 1 && ret != num_channels) {
1683 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n");
1687 channels = devm_kcalloc(&indio_dev->dev, num_channels,
1688 sizeof(struct iio_chan_spec), GFP_KERNEL);
1692 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
1693 if (val >= adc_info->max_channels) {
1694 dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
1698 /* Channel can't be configured both as single-ended & diff */
1699 for (i = 0; i < num_diff; i++) {
1700 if (val == diff[i].vinp) {
1701 dev_err(&indio_dev->dev,
1702 "channel %d miss-configured\n", val);
1706 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val,
1707 0, scan_index, false);
1711 for (i = 0; i < num_diff; i++) {
1712 if (diff[i].vinp >= adc_info->max_channels ||
1713 diff[i].vinn >= adc_info->max_channels) {
1714 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n",
1715 diff[i].vinp, diff[i].vinn);
1718 stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
1719 diff[i].vinp, diff[i].vinn, scan_index,
1724 for (i = 0; i < scan_index; i++) {
1726 * Using of_property_read_u32_index(), smp value will only be
1727 * modified if valid u32 value can be decoded. This allows to
1728 * get either no value, 1 shared value for all indexes, or one
1729 * value per channel.
1731 of_property_read_u32_index(node, "st,min-sample-time-nsecs",
1733 /* Prepare sampling time settings */
1734 stm32_adc_smpr_init(adc, channels[i].channel, smp);
1737 indio_dev->num_channels = scan_index;
1738 indio_dev->channels = channels;
1743 static int stm32_adc_dma_request(struct iio_dev *indio_dev)
1745 struct stm32_adc *adc = iio_priv(indio_dev);
1746 struct dma_slave_config config;
1749 adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
1753 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1754 STM32_DMA_BUFFER_SIZE,
1755 &adc->rx_dma_buf, GFP_KERNEL);
1761 /* Configure DMA channel to read data register */
1762 memset(&config, 0, sizeof(config));
1763 config.src_addr = (dma_addr_t)adc->common->phys_base;
1764 config.src_addr += adc->offset + adc->cfg->regs->dr;
1765 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1767 ret = dmaengine_slave_config(adc->dma_chan, &config);
1774 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE,
1775 adc->rx_buf, adc->rx_dma_buf);
1777 dma_release_channel(adc->dma_chan);
1782 static int stm32_adc_probe(struct platform_device *pdev)
1784 struct iio_dev *indio_dev;
1785 struct device *dev = &pdev->dev;
1786 struct stm32_adc *adc;
1789 if (!pdev->dev.of_node)
1792 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
1796 adc = iio_priv(indio_dev);
1797 adc->common = dev_get_drvdata(pdev->dev.parent);
1798 spin_lock_init(&adc->lock);
1799 init_completion(&adc->completion);
1800 adc->cfg = (const struct stm32_adc_cfg *)
1801 of_match_device(dev->driver->of_match_table, dev)->data;
1803 indio_dev->name = dev_name(&pdev->dev);
1804 indio_dev->dev.parent = &pdev->dev;
1805 indio_dev->dev.of_node = pdev->dev.of_node;
1806 indio_dev->info = &stm32_adc_iio_info;
1807 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED;
1809 platform_set_drvdata(pdev, adc);
1811 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
1813 dev_err(&pdev->dev, "missing reg property\n");
1817 adc->irq = platform_get_irq(pdev, 0);
1821 ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr,
1822 0, pdev->name, adc);
1824 dev_err(&pdev->dev, "failed to request IRQ\n");
1828 adc->clk = devm_clk_get(&pdev->dev, NULL);
1829 if (IS_ERR(adc->clk)) {
1830 ret = PTR_ERR(adc->clk);
1831 if (ret == -ENOENT && !adc->cfg->clk_required) {
1834 dev_err(&pdev->dev, "Can't get clock\n");
1839 ret = stm32_adc_of_get_resolution(indio_dev);
1843 ret = stm32_adc_chan_of_init(indio_dev);
1847 ret = stm32_adc_dma_request(indio_dev);
1851 ret = iio_triggered_buffer_setup(indio_dev,
1852 &iio_pollfunc_store_time,
1853 &stm32_adc_trigger_handler,
1854 &stm32_adc_buffer_setup_ops);
1856 dev_err(&pdev->dev, "buffer setup failed\n");
1857 goto err_dma_disable;
1860 /* Get stm32-adc-core PM online */
1861 pm_runtime_get_noresume(dev);
1862 pm_runtime_set_active(dev);
1863 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_HW_STOP_DELAY_MS);
1864 pm_runtime_use_autosuspend(dev);
1865 pm_runtime_enable(dev);
1867 ret = stm32_adc_hw_start(dev);
1869 goto err_buffer_cleanup;
1871 ret = iio_device_register(indio_dev);
1873 dev_err(&pdev->dev, "iio dev register failed\n");
1877 pm_runtime_mark_last_busy(dev);
1878 pm_runtime_put_autosuspend(dev);
1883 stm32_adc_hw_stop(dev);
1886 pm_runtime_disable(dev);
1887 pm_runtime_set_suspended(dev);
1888 pm_runtime_put_noidle(dev);
1889 iio_triggered_buffer_cleanup(indio_dev);
1892 if (adc->dma_chan) {
1893 dma_free_coherent(adc->dma_chan->device->dev,
1894 STM32_DMA_BUFFER_SIZE,
1895 adc->rx_buf, adc->rx_dma_buf);
1896 dma_release_channel(adc->dma_chan);
1902 static int stm32_adc_remove(struct platform_device *pdev)
1904 struct stm32_adc *adc = platform_get_drvdata(pdev);
1905 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1907 pm_runtime_get_sync(&pdev->dev);
1908 iio_device_unregister(indio_dev);
1909 stm32_adc_hw_stop(&pdev->dev);
1910 pm_runtime_disable(&pdev->dev);
1911 pm_runtime_set_suspended(&pdev->dev);
1912 pm_runtime_put_noidle(&pdev->dev);
1913 iio_triggered_buffer_cleanup(indio_dev);
1914 if (adc->dma_chan) {
1915 dma_free_coherent(adc->dma_chan->device->dev,
1916 STM32_DMA_BUFFER_SIZE,
1917 adc->rx_buf, adc->rx_dma_buf);
1918 dma_release_channel(adc->dma_chan);
1924 #if defined(CONFIG_PM_SLEEP)
1925 static int stm32_adc_suspend(struct device *dev)
1927 struct stm32_adc *adc = dev_get_drvdata(dev);
1928 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1930 if (iio_buffer_enabled(indio_dev))
1931 __stm32_adc_buffer_predisable(indio_dev);
1933 return pm_runtime_force_suspend(dev);
1936 static int stm32_adc_resume(struct device *dev)
1938 struct stm32_adc *adc = dev_get_drvdata(dev);
1939 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1942 ret = pm_runtime_force_resume(dev);
1946 if (!iio_buffer_enabled(indio_dev))
1949 ret = stm32_adc_update_scan_mode(indio_dev,
1950 indio_dev->active_scan_mask);
1954 return __stm32_adc_buffer_postenable(indio_dev);
1958 #if defined(CONFIG_PM)
1959 static int stm32_adc_runtime_suspend(struct device *dev)
1961 return stm32_adc_hw_stop(dev);
1964 static int stm32_adc_runtime_resume(struct device *dev)
1966 return stm32_adc_hw_start(dev);
1970 static const struct dev_pm_ops stm32_adc_pm_ops = {
1971 SET_SYSTEM_SLEEP_PM_OPS(stm32_adc_suspend, stm32_adc_resume)
1972 SET_RUNTIME_PM_OPS(stm32_adc_runtime_suspend, stm32_adc_runtime_resume,
1976 static const struct stm32_adc_cfg stm32f4_adc_cfg = {
1977 .regs = &stm32f4_adc_regspec,
1978 .adc_info = &stm32f4_adc_info,
1979 .trigs = stm32f4_adc_trigs,
1980 .clk_required = true,
1981 .start_conv = stm32f4_adc_start_conv,
1982 .stop_conv = stm32f4_adc_stop_conv,
1983 .smp_cycles = stm32f4_adc_smp_cycles,
1986 static const struct stm32_adc_cfg stm32h7_adc_cfg = {
1987 .regs = &stm32h7_adc_regspec,
1988 .adc_info = &stm32h7_adc_info,
1989 .trigs = stm32h7_adc_trigs,
1990 .start_conv = stm32h7_adc_start_conv,
1991 .stop_conv = stm32h7_adc_stop_conv,
1992 .prepare = stm32h7_adc_prepare,
1993 .unprepare = stm32h7_adc_unprepare,
1994 .smp_cycles = stm32h7_adc_smp_cycles,
1997 static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
1998 .regs = &stm32h7_adc_regspec,
1999 .adc_info = &stm32h7_adc_info,
2000 .trigs = stm32h7_adc_trigs,
2001 .has_vregready = true,
2002 .start_conv = stm32h7_adc_start_conv,
2003 .stop_conv = stm32h7_adc_stop_conv,
2004 .prepare = stm32h7_adc_prepare,
2005 .unprepare = stm32h7_adc_unprepare,
2006 .smp_cycles = stm32h7_adc_smp_cycles,
2009 static const struct of_device_id stm32_adc_of_match[] = {
2010 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
2011 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
2012 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
2015 MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
2017 static struct platform_driver stm32_adc_driver = {
2018 .probe = stm32_adc_probe,
2019 .remove = stm32_adc_remove,
2021 .name = "stm32-adc",
2022 .of_match_table = stm32_adc_of_match,
2023 .pm = &stm32_adc_pm_ops,
2026 module_platform_driver(stm32_adc_driver);
2028 MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
2029 MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver");
2030 MODULE_LICENSE("GPL v2");
2031 MODULE_ALIAS("platform:stm32-adc");