1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Spreadtrum Communications Inc.
4 #include <linux/hwspinlock.h>
5 #include <linux/iio/iio.h>
6 #include <linux/interrupt.h>
7 #include <linux/module.h>
8 #include <linux/nvmem-consumer.h>
10 #include <linux/of_device.h>
11 #include <linux/platform_device.h>
12 #include <linux/regmap.h>
13 #include <linux/slab.h>
15 /* PMIC global registers definition */
16 #define SC27XX_MODULE_EN 0xc08
17 #define SC27XX_MODULE_ADC_EN BIT(5)
18 #define SC27XX_ARM_CLK_EN 0xc10
19 #define SC27XX_CLK_ADC_EN BIT(5)
20 #define SC27XX_CLK_ADC_CLK_EN BIT(6)
22 /* ADC controller registers definition */
23 #define SC27XX_ADC_CTL 0x0
24 #define SC27XX_ADC_CH_CFG 0x4
25 #define SC27XX_ADC_DATA 0x4c
26 #define SC27XX_ADC_INT_EN 0x50
27 #define SC27XX_ADC_INT_CLR 0x54
28 #define SC27XX_ADC_INT_STS 0x58
29 #define SC27XX_ADC_INT_RAW 0x5c
31 /* Bits and mask definition for SC27XX_ADC_CTL register */
32 #define SC27XX_ADC_EN BIT(0)
33 #define SC27XX_ADC_CHN_RUN BIT(1)
34 #define SC27XX_ADC_12BIT_MODE BIT(2)
35 #define SC27XX_ADC_RUN_NUM_MASK GENMASK(7, 4)
36 #define SC27XX_ADC_RUN_NUM_SHIFT 4
38 /* Bits and mask definition for SC27XX_ADC_CH_CFG register */
39 #define SC27XX_ADC_CHN_ID_MASK GENMASK(4, 0)
40 #define SC27XX_ADC_SCALE_MASK GENMASK(10, 8)
41 #define SC27XX_ADC_SCALE_SHIFT 8
43 /* Bits definitions for SC27XX_ADC_INT_EN registers */
44 #define SC27XX_ADC_IRQ_EN BIT(0)
46 /* Bits definitions for SC27XX_ADC_INT_CLR registers */
47 #define SC27XX_ADC_IRQ_CLR BIT(0)
49 /* Mask definition for SC27XX_ADC_DATA register */
50 #define SC27XX_ADC_DATA_MASK GENMASK(11, 0)
52 /* Timeout (ms) for the trylock of hardware spinlocks */
53 #define SC27XX_ADC_HWLOCK_TIMEOUT 5000
55 /* Timeout (ms) for ADC data conversion according to ADC datasheet */
56 #define SC27XX_ADC_RDY_TIMEOUT 100
58 /* Maximum ADC channel number */
59 #define SC27XX_ADC_CHANNEL_MAX 32
61 /* ADC voltage ratio definition */
62 #define SC27XX_VOLT_RATIO(n, d) \
63 (((n) << SC27XX_RATIO_NUMERATOR_OFFSET) | (d))
64 #define SC27XX_RATIO_NUMERATOR_OFFSET 16
65 #define SC27XX_RATIO_DENOMINATOR_MASK GENMASK(15, 0)
67 struct sc27xx_adc_data {
69 struct regmap *regmap;
71 * One hardware spinlock to synchronize between the multiple
72 * subsystems which will access the unique ADC controller.
74 struct hwspinlock *hwlock;
75 struct completion completion;
76 int channel_scale[SC27XX_ADC_CHANNEL_MAX];
82 struct sc27xx_adc_linear_graph {
90 * According to the datasheet, we can convert one ADC value to one voltage value
91 * through 2 points in the linear graph. If the voltage is less than 1.2v, we
92 * should use the small-scale graph, and if more than 1.2v, we should use the
95 static struct sc27xx_adc_linear_graph big_scale_graph = {
100 static struct sc27xx_adc_linear_graph small_scale_graph = {
105 static const struct sc27xx_adc_linear_graph big_scale_graph_calib = {
110 static const struct sc27xx_adc_linear_graph small_scale_graph_calib = {
115 static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc)
117 return ((calib_data & 0xff) + calib_adc - 128) * 4;
120 static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data,
123 const struct sc27xx_adc_linear_graph *calib_graph;
124 struct sc27xx_adc_linear_graph *graph;
125 struct nvmem_cell *cell;
126 const char *cell_name;
132 calib_graph = &big_scale_graph_calib;
133 graph = &big_scale_graph;
134 cell_name = "big_scale_calib";
136 calib_graph = &small_scale_graph_calib;
137 graph = &small_scale_graph;
138 cell_name = "small_scale_calib";
141 cell = nvmem_cell_get(data->dev, cell_name);
143 return PTR_ERR(cell);
145 buf = nvmem_cell_read(cell, &len);
146 nvmem_cell_put(cell);
151 memcpy(&calib_data, buf, min(len, sizeof(u32)));
153 /* Only need to calibrate the adc values in the linear graph. */
154 graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0);
155 graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8,
162 static int sc27xx_adc_get_ratio(int channel, int scale)
169 return scale ? SC27XX_VOLT_RATIO(400, 1025) :
170 SC27XX_VOLT_RATIO(1, 1);
172 return SC27XX_VOLT_RATIO(7, 29);
174 return SC27XX_VOLT_RATIO(375, 9000);
177 return scale ? SC27XX_VOLT_RATIO(100, 125) :
178 SC27XX_VOLT_RATIO(1, 1);
180 return SC27XX_VOLT_RATIO(1, 3);
182 return SC27XX_VOLT_RATIO(1, 1);
184 return SC27XX_VOLT_RATIO(1, 1);
187 static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel,
193 reinit_completion(&data->completion);
195 ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT);
197 dev_err(data->dev, "timeout to get the hwspinlock\n");
201 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
202 SC27XX_ADC_EN, SC27XX_ADC_EN);
206 /* Configure the channel id and scale */
207 tmp = (scale << SC27XX_ADC_SCALE_SHIFT) & SC27XX_ADC_SCALE_MASK;
208 tmp |= channel & SC27XX_ADC_CHN_ID_MASK;
209 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG,
210 SC27XX_ADC_CHN_ID_MASK | SC27XX_ADC_SCALE_MASK,
215 /* Select 12bit conversion mode, and only sample 1 time */
216 tmp = SC27XX_ADC_12BIT_MODE;
217 tmp |= (0 << SC27XX_ADC_RUN_NUM_SHIFT) & SC27XX_ADC_RUN_NUM_MASK;
218 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
219 SC27XX_ADC_RUN_NUM_MASK | SC27XX_ADC_12BIT_MODE,
224 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
225 SC27XX_ADC_CHN_RUN, SC27XX_ADC_CHN_RUN);
229 ret = wait_for_completion_timeout(&data->completion,
230 msecs_to_jiffies(SC27XX_ADC_RDY_TIMEOUT));
232 dev_err(data->dev, "read ADC data timeout\n");
239 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
242 hwspin_unlock_raw(data->hwlock);
250 static irqreturn_t sc27xx_adc_isr(int irq, void *dev_id)
252 struct sc27xx_adc_data *data = dev_id;
255 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR,
256 SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR);
258 return IRQ_RETVAL(ret);
260 ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA,
263 return IRQ_RETVAL(ret);
265 data->value &= SC27XX_ADC_DATA_MASK;
266 complete(&data->completion);
271 static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data,
272 int channel, int scale,
273 u32 *div_numerator, u32 *div_denominator)
275 u32 ratio = sc27xx_adc_get_ratio(channel, scale);
277 *div_numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET;
278 *div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK;
281 static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph,
286 tmp = (graph->volt0 - graph->volt1) * (raw_adc - graph->adc1);
287 tmp /= (graph->adc0 - graph->adc1);
290 return tmp < 0 ? 0 : tmp;
293 static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel,
294 int scale, int raw_adc)
296 u32 numerator, denominator;
300 * Convert ADC values to voltage values according to the linear graph,
301 * and channel 5 and channel 1 has been calibrated, so we can just
302 * return the voltage values calculated by the linear graph. But other
303 * channels need be calculated to the real voltage values with the
308 return sc27xx_adc_to_volt(&big_scale_graph, raw_adc);
311 return sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
314 volt = sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
318 sc27xx_adc_volt_ratio(data, channel, scale, &numerator, &denominator);
320 return (volt * denominator + numerator / 2) / numerator;
323 static int sc27xx_adc_read_processed(struct sc27xx_adc_data *data,
324 int channel, int scale, int *val)
328 ret = sc27xx_adc_read(data, channel, scale, &raw_adc);
332 *val = sc27xx_adc_convert_volt(data, channel, scale, raw_adc);
336 static int sc27xx_adc_read_raw(struct iio_dev *indio_dev,
337 struct iio_chan_spec const *chan,
338 int *val, int *val2, long mask)
340 struct sc27xx_adc_data *data = iio_priv(indio_dev);
341 int scale = data->channel_scale[chan->channel];
345 case IIO_CHAN_INFO_RAW:
346 mutex_lock(&indio_dev->mlock);
347 ret = sc27xx_adc_read(data, chan->channel, scale, &tmp);
348 mutex_unlock(&indio_dev->mlock);
356 case IIO_CHAN_INFO_PROCESSED:
357 mutex_lock(&indio_dev->mlock);
358 ret = sc27xx_adc_read_processed(data, chan->channel, scale,
360 mutex_unlock(&indio_dev->mlock);
368 case IIO_CHAN_INFO_SCALE:
377 static int sc27xx_adc_write_raw(struct iio_dev *indio_dev,
378 struct iio_chan_spec const *chan,
379 int val, int val2, long mask)
381 struct sc27xx_adc_data *data = iio_priv(indio_dev);
384 case IIO_CHAN_INFO_SCALE:
385 data->channel_scale[chan->channel] = val;
393 static const struct iio_info sc27xx_info = {
394 .read_raw = &sc27xx_adc_read_raw,
395 .write_raw = &sc27xx_adc_write_raw,
398 #define SC27XX_ADC_CHANNEL(index, mask) { \
399 .type = IIO_VOLTAGE, \
401 .info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE), \
402 .datasheet_name = "CH##index", \
406 static const struct iio_chan_spec sc27xx_channels[] = {
407 SC27XX_ADC_CHANNEL(0, BIT(IIO_CHAN_INFO_PROCESSED)),
408 SC27XX_ADC_CHANNEL(1, BIT(IIO_CHAN_INFO_PROCESSED)),
409 SC27XX_ADC_CHANNEL(2, BIT(IIO_CHAN_INFO_PROCESSED)),
410 SC27XX_ADC_CHANNEL(3, BIT(IIO_CHAN_INFO_PROCESSED)),
411 SC27XX_ADC_CHANNEL(4, BIT(IIO_CHAN_INFO_PROCESSED)),
412 SC27XX_ADC_CHANNEL(5, BIT(IIO_CHAN_INFO_PROCESSED)),
413 SC27XX_ADC_CHANNEL(6, BIT(IIO_CHAN_INFO_PROCESSED)),
414 SC27XX_ADC_CHANNEL(7, BIT(IIO_CHAN_INFO_PROCESSED)),
415 SC27XX_ADC_CHANNEL(8, BIT(IIO_CHAN_INFO_PROCESSED)),
416 SC27XX_ADC_CHANNEL(9, BIT(IIO_CHAN_INFO_PROCESSED)),
417 SC27XX_ADC_CHANNEL(10, BIT(IIO_CHAN_INFO_PROCESSED)),
418 SC27XX_ADC_CHANNEL(11, BIT(IIO_CHAN_INFO_PROCESSED)),
419 SC27XX_ADC_CHANNEL(12, BIT(IIO_CHAN_INFO_PROCESSED)),
420 SC27XX_ADC_CHANNEL(13, BIT(IIO_CHAN_INFO_PROCESSED)),
421 SC27XX_ADC_CHANNEL(14, BIT(IIO_CHAN_INFO_PROCESSED)),
422 SC27XX_ADC_CHANNEL(15, BIT(IIO_CHAN_INFO_PROCESSED)),
423 SC27XX_ADC_CHANNEL(16, BIT(IIO_CHAN_INFO_PROCESSED)),
424 SC27XX_ADC_CHANNEL(17, BIT(IIO_CHAN_INFO_PROCESSED)),
425 SC27XX_ADC_CHANNEL(18, BIT(IIO_CHAN_INFO_PROCESSED)),
426 SC27XX_ADC_CHANNEL(19, BIT(IIO_CHAN_INFO_PROCESSED)),
427 SC27XX_ADC_CHANNEL(20, BIT(IIO_CHAN_INFO_RAW)),
428 SC27XX_ADC_CHANNEL(21, BIT(IIO_CHAN_INFO_PROCESSED)),
429 SC27XX_ADC_CHANNEL(22, BIT(IIO_CHAN_INFO_PROCESSED)),
430 SC27XX_ADC_CHANNEL(23, BIT(IIO_CHAN_INFO_PROCESSED)),
431 SC27XX_ADC_CHANNEL(24, BIT(IIO_CHAN_INFO_PROCESSED)),
432 SC27XX_ADC_CHANNEL(25, BIT(IIO_CHAN_INFO_PROCESSED)),
433 SC27XX_ADC_CHANNEL(26, BIT(IIO_CHAN_INFO_PROCESSED)),
434 SC27XX_ADC_CHANNEL(27, BIT(IIO_CHAN_INFO_PROCESSED)),
435 SC27XX_ADC_CHANNEL(28, BIT(IIO_CHAN_INFO_PROCESSED)),
436 SC27XX_ADC_CHANNEL(29, BIT(IIO_CHAN_INFO_PROCESSED)),
437 SC27XX_ADC_CHANNEL(30, BIT(IIO_CHAN_INFO_PROCESSED)),
438 SC27XX_ADC_CHANNEL(31, BIT(IIO_CHAN_INFO_PROCESSED)),
441 static int sc27xx_adc_enable(struct sc27xx_adc_data *data)
445 ret = regmap_update_bits(data->regmap, SC27XX_MODULE_EN,
446 SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN);
450 /* Enable ADC work clock and controller clock */
451 ret = regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN,
452 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN,
453 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN);
457 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_EN,
458 SC27XX_ADC_IRQ_EN, SC27XX_ADC_IRQ_EN);
462 /* ADC channel scales' calibration from nvmem device */
463 ret = sc27xx_adc_scale_calibration(data, true);
467 ret = sc27xx_adc_scale_calibration(data, false);
474 regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN,
475 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
477 regmap_update_bits(data->regmap, SC27XX_MODULE_EN,
478 SC27XX_MODULE_ADC_EN, 0);
483 static void sc27xx_adc_disable(void *_data)
485 struct sc27xx_adc_data *data = _data;
487 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_EN,
488 SC27XX_ADC_IRQ_EN, 0);
490 /* Disable ADC work clock and controller clock */
491 regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN,
492 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
494 regmap_update_bits(data->regmap, SC27XX_MODULE_EN,
495 SC27XX_MODULE_ADC_EN, 0);
498 static void sc27xx_adc_free_hwlock(void *_data)
500 struct hwspinlock *hwlock = _data;
502 hwspin_lock_free(hwlock);
505 static int sc27xx_adc_probe(struct platform_device *pdev)
507 struct device_node *np = pdev->dev.of_node;
508 struct sc27xx_adc_data *sc27xx_data;
509 struct iio_dev *indio_dev;
512 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*sc27xx_data));
516 sc27xx_data = iio_priv(indio_dev);
518 sc27xx_data->regmap = dev_get_regmap(pdev->dev.parent, NULL);
519 if (!sc27xx_data->regmap) {
520 dev_err(&pdev->dev, "failed to get ADC regmap\n");
524 ret = of_property_read_u32(np, "reg", &sc27xx_data->base);
526 dev_err(&pdev->dev, "failed to get ADC base address\n");
530 sc27xx_data->irq = platform_get_irq(pdev, 0);
531 if (sc27xx_data->irq < 0) {
532 dev_err(&pdev->dev, "failed to get ADC irq number\n");
533 return sc27xx_data->irq;
536 ret = of_hwspin_lock_get_id(np, 0);
538 dev_err(&pdev->dev, "failed to get hwspinlock id\n");
542 sc27xx_data->hwlock = hwspin_lock_request_specific(ret);
543 if (!sc27xx_data->hwlock) {
544 dev_err(&pdev->dev, "failed to request hwspinlock\n");
548 ret = devm_add_action(&pdev->dev, sc27xx_adc_free_hwlock,
549 sc27xx_data->hwlock);
551 sc27xx_adc_free_hwlock(sc27xx_data->hwlock);
552 dev_err(&pdev->dev, "failed to add hwspinlock action\n");
556 init_completion(&sc27xx_data->completion);
557 sc27xx_data->dev = &pdev->dev;
559 ret = sc27xx_adc_enable(sc27xx_data);
561 dev_err(&pdev->dev, "failed to enable ADC module\n");
565 ret = devm_add_action(&pdev->dev, sc27xx_adc_disable, sc27xx_data);
567 sc27xx_adc_disable(sc27xx_data);
568 dev_err(&pdev->dev, "failed to add ADC disable action\n");
572 ret = devm_request_threaded_irq(&pdev->dev, sc27xx_data->irq, NULL,
573 sc27xx_adc_isr, IRQF_ONESHOT,
574 pdev->name, sc27xx_data);
576 dev_err(&pdev->dev, "failed to request ADC irq\n");
580 indio_dev->dev.parent = &pdev->dev;
581 indio_dev->name = dev_name(&pdev->dev);
582 indio_dev->modes = INDIO_DIRECT_MODE;
583 indio_dev->info = &sc27xx_info;
584 indio_dev->channels = sc27xx_channels;
585 indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels);
586 ret = devm_iio_device_register(&pdev->dev, indio_dev);
588 dev_err(&pdev->dev, "could not register iio (ADC)");
593 static const struct of_device_id sc27xx_adc_of_match[] = {
594 { .compatible = "sprd,sc2731-adc", },
598 static struct platform_driver sc27xx_adc_driver = {
599 .probe = sc27xx_adc_probe,
601 .name = "sc27xx-adc",
602 .of_match_table = sc27xx_adc_of_match,
606 module_platform_driver(sc27xx_adc_driver);
608 MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
609 MODULE_DESCRIPTION("Spreadtrum SC27XX ADC Driver");
610 MODULE_LICENSE("GPL v2");