1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Spreadtrum Communications Inc.
4 #include <linux/hwspinlock.h>
5 #include <linux/iio/iio.h>
6 #include <linux/module.h>
7 #include <linux/nvmem-consumer.h>
9 #include <linux/of_device.h>
10 #include <linux/platform_device.h>
11 #include <linux/regmap.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/slab.h>
15 /* PMIC global registers definition */
16 #define SC2730_MODULE_EN 0x1808
17 #define SC2731_MODULE_EN 0xc08
18 #define SC27XX_MODULE_ADC_EN BIT(5)
19 #define SC2721_ARM_CLK_EN 0xc0c
20 #define SC2730_ARM_CLK_EN 0x180c
21 #define SC2731_ARM_CLK_EN 0xc10
22 #define SC27XX_CLK_ADC_EN BIT(5)
23 #define SC27XX_CLK_ADC_CLK_EN BIT(6)
25 /* ADC controller registers definition */
26 #define SC27XX_ADC_CTL 0x0
27 #define SC27XX_ADC_CH_CFG 0x4
28 #define SC27XX_ADC_DATA 0x4c
29 #define SC27XX_ADC_INT_EN 0x50
30 #define SC27XX_ADC_INT_CLR 0x54
31 #define SC27XX_ADC_INT_STS 0x58
32 #define SC27XX_ADC_INT_RAW 0x5c
34 /* Bits and mask definition for SC27XX_ADC_CTL register */
35 #define SC27XX_ADC_EN BIT(0)
36 #define SC27XX_ADC_CHN_RUN BIT(1)
37 #define SC27XX_ADC_12BIT_MODE BIT(2)
38 #define SC27XX_ADC_RUN_NUM_MASK GENMASK(7, 4)
39 #define SC27XX_ADC_RUN_NUM_SHIFT 4
41 /* Bits and mask definition for SC27XX_ADC_CH_CFG register */
42 #define SC27XX_ADC_CHN_ID_MASK GENMASK(4, 0)
43 #define SC27XX_ADC_SCALE_MASK GENMASK(10, 9)
44 #define SC2721_ADC_SCALE_MASK BIT(5)
45 #define SC27XX_ADC_SCALE_SHIFT 9
46 #define SC2721_ADC_SCALE_SHIFT 5
48 /* Bits definitions for SC27XX_ADC_INT_EN registers */
49 #define SC27XX_ADC_IRQ_EN BIT(0)
51 /* Bits definitions for SC27XX_ADC_INT_CLR registers */
52 #define SC27XX_ADC_IRQ_CLR BIT(0)
54 /* Bits definitions for SC27XX_ADC_INT_RAW registers */
55 #define SC27XX_ADC_IRQ_RAW BIT(0)
57 /* Mask definition for SC27XX_ADC_DATA register */
58 #define SC27XX_ADC_DATA_MASK GENMASK(11, 0)
60 /* Timeout (ms) for the trylock of hardware spinlocks */
61 #define SC27XX_ADC_HWLOCK_TIMEOUT 5000
63 /* Timeout (us) for ADC data conversion according to ADC datasheet */
64 #define SC27XX_ADC_RDY_TIMEOUT 1000000
65 #define SC27XX_ADC_POLL_RAW_STATUS 500
67 /* Maximum ADC channel number */
68 #define SC27XX_ADC_CHANNEL_MAX 32
70 /* ADC voltage ratio definition */
71 #define SC27XX_VOLT_RATIO(n, d) \
72 (((n) << SC27XX_RATIO_NUMERATOR_OFFSET) | (d))
73 #define SC27XX_RATIO_NUMERATOR_OFFSET 16
74 #define SC27XX_RATIO_DENOMINATOR_MASK GENMASK(15, 0)
76 /* ADC specific channel reference voltage 3.5V */
77 #define SC27XX_ADC_REFVOL_VDD35 3500000
79 /* ADC default channel reference voltage is 2.8V */
80 #define SC27XX_ADC_REFVOL_VDD28 2800000
82 struct sc27xx_adc_data {
84 struct regulator *volref;
85 struct regmap *regmap;
87 * One hardware spinlock to synchronize between the multiple
88 * subsystems which will access the unique ADC controller.
90 struct hwspinlock *hwlock;
91 int channel_scale[SC27XX_ADC_CHANNEL_MAX];
94 const struct sc27xx_adc_variant_data *var_data;
98 * Since different PMICs of SC27xx series can have different
99 * address and ratio, we should save ratio config and base
100 * in the device data structure.
102 struct sc27xx_adc_variant_data {
107 const struct sc27xx_adc_linear_graph *bscale_cal;
108 const struct sc27xx_adc_linear_graph *sscale_cal;
109 void (*init_scale)(struct sc27xx_adc_data *data);
110 int (*get_ratio)(int channel, int scale);
114 struct sc27xx_adc_linear_graph {
122 * According to the datasheet, we can convert one ADC value to one voltage value
123 * through 2 points in the linear graph. If the voltage is less than 1.2v, we
124 * should use the small-scale graph, and if more than 1.2v, we should use the
127 static struct sc27xx_adc_linear_graph big_scale_graph = {
132 static struct sc27xx_adc_linear_graph small_scale_graph = {
137 static const struct sc27xx_adc_linear_graph sc2731_big_scale_graph_calib = {
142 static const struct sc27xx_adc_linear_graph sc2731_small_scale_graph_calib = {
147 static const struct sc27xx_adc_linear_graph big_scale_graph_calib = {
152 static const struct sc27xx_adc_linear_graph small_scale_graph_calib = {
157 static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc)
159 return ((calib_data & 0xff) + calib_adc - 128) * 4;
162 /* get the adc nvmem cell calibration data */
163 static int adc_nvmem_cell_calib_data(struct sc27xx_adc_data *data, const char *cell_name)
165 struct nvmem_cell *cell;
167 u32 origin_calib_data = 0;
173 cell = nvmem_cell_get(data->dev, cell_name);
175 return PTR_ERR(cell);
177 buf = nvmem_cell_read(cell, &len);
179 nvmem_cell_put(cell);
183 memcpy(&origin_calib_data, buf, min(len, sizeof(u32)));
186 nvmem_cell_put(cell);
187 return origin_calib_data;
190 static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data,
193 const struct sc27xx_adc_linear_graph *calib_graph;
194 struct sc27xx_adc_linear_graph *graph;
195 const char *cell_name;
199 calib_graph = data->var_data->bscale_cal;
200 graph = &big_scale_graph;
201 cell_name = "big_scale_calib";
203 calib_graph = data->var_data->sscale_cal;
204 graph = &small_scale_graph;
205 cell_name = "small_scale_calib";
208 calib_data = adc_nvmem_cell_calib_data(data, cell_name);
210 /* Only need to calibrate the adc values in the linear graph. */
211 graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0);
212 graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8,
218 static int sc2720_adc_get_ratio(int channel, int scale)
224 return SC27XX_VOLT_RATIO(68, 900);
226 return SC27XX_VOLT_RATIO(68, 1760);
228 return SC27XX_VOLT_RATIO(68, 2327);
230 return SC27XX_VOLT_RATIO(68, 3654);
232 return SC27XX_VOLT_RATIO(1, 1);
237 return SC27XX_VOLT_RATIO(48, 100);
239 return SC27XX_VOLT_RATIO(480, 1955);
241 return SC27XX_VOLT_RATIO(480, 2586);
243 return SC27XX_VOLT_RATIO(48, 406);
245 return SC27XX_VOLT_RATIO(1, 1);
252 return SC27XX_VOLT_RATIO(3, 8);
254 return SC27XX_VOLT_RATIO(375, 1955);
256 return SC27XX_VOLT_RATIO(375, 2586);
258 return SC27XX_VOLT_RATIO(300, 3248);
260 return SC27XX_VOLT_RATIO(1, 1);
265 return SC27XX_VOLT_RATIO(1, 1);
267 return SC27XX_VOLT_RATIO(1000, 1955);
269 return SC27XX_VOLT_RATIO(1000, 2586);
271 return SC27XX_VOLT_RATIO(100, 406);
273 return SC27XX_VOLT_RATIO(1, 1);
276 return SC27XX_VOLT_RATIO(1, 1);
279 static int sc2721_adc_get_ratio(int channel, int scale)
286 return scale ? SC27XX_VOLT_RATIO(400, 1025) :
287 SC27XX_VOLT_RATIO(1, 1);
289 return SC27XX_VOLT_RATIO(7, 29);
292 return scale ? SC27XX_VOLT_RATIO(100, 125) :
293 SC27XX_VOLT_RATIO(1, 1);
295 return SC27XX_VOLT_RATIO(68, 900);
297 return SC27XX_VOLT_RATIO(48, 100);
299 return SC27XX_VOLT_RATIO(1, 3);
301 return SC27XX_VOLT_RATIO(1, 1);
303 return SC27XX_VOLT_RATIO(1, 1);
306 static int sc2730_adc_get_ratio(int channel, int scale)
312 return SC27XX_VOLT_RATIO(68, 900);
314 return SC27XX_VOLT_RATIO(68, 1760);
316 return SC27XX_VOLT_RATIO(68, 2327);
318 return SC27XX_VOLT_RATIO(68, 3654);
320 return SC27XX_VOLT_RATIO(1, 1);
325 return SC27XX_VOLT_RATIO(1, 3);
327 return SC27XX_VOLT_RATIO(1000, 5865);
329 return SC27XX_VOLT_RATIO(500, 3879);
331 return SC27XX_VOLT_RATIO(500, 6090);
333 return SC27XX_VOLT_RATIO(1, 1);
338 return SC27XX_VOLT_RATIO(48, 100);
340 return SC27XX_VOLT_RATIO(480, 1955);
342 return SC27XX_VOLT_RATIO(480, 2586);
344 return SC27XX_VOLT_RATIO(48, 406);
346 return SC27XX_VOLT_RATIO(1, 1);
353 return SC27XX_VOLT_RATIO(3, 8);
355 return SC27XX_VOLT_RATIO(375, 1955);
357 return SC27XX_VOLT_RATIO(375, 2586);
359 return SC27XX_VOLT_RATIO(300, 3248);
361 return SC27XX_VOLT_RATIO(1, 1);
366 return SC27XX_VOLT_RATIO(1, 1);
368 return SC27XX_VOLT_RATIO(1000, 1955);
370 return SC27XX_VOLT_RATIO(1000, 2586);
372 return SC27XX_VOLT_RATIO(1000, 4060);
374 return SC27XX_VOLT_RATIO(1, 1);
377 return SC27XX_VOLT_RATIO(1, 1);
380 static int sc2731_adc_get_ratio(int channel, int scale)
387 return scale ? SC27XX_VOLT_RATIO(400, 1025) :
388 SC27XX_VOLT_RATIO(1, 1);
390 return SC27XX_VOLT_RATIO(7, 29);
392 return SC27XX_VOLT_RATIO(375, 9000);
395 return scale ? SC27XX_VOLT_RATIO(100, 125) :
396 SC27XX_VOLT_RATIO(1, 1);
398 return SC27XX_VOLT_RATIO(1, 3);
400 return SC27XX_VOLT_RATIO(1, 1);
402 return SC27XX_VOLT_RATIO(1, 1);
406 * According to the datasheet set specific value on some channel.
408 static void sc2720_adc_scale_init(struct sc27xx_adc_data *data)
412 for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) {
415 data->channel_scale[i] = 3;
419 data->channel_scale[i] = 2;
422 data->channel_scale[i] = 1;
427 data->channel_scale[i] = 3;
430 data->channel_scale[i] = 0;
436 static void sc2730_adc_scale_init(struct sc27xx_adc_data *data)
440 for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) {
447 data->channel_scale[i] = 3;
451 data->channel_scale[i] = 2;
454 data->channel_scale[i] = 1;
457 data->channel_scale[i] = 0;
463 static void sc2731_adc_scale_init(struct sc27xx_adc_data *data)
467 * In the current software design, SC2731 support 2 scales,
468 * channels 5 uses big scale, others use smale.
470 for (i = 0; i < SC27XX_ADC_CHANNEL_MAX; i++) {
473 data->channel_scale[i] = 1;
476 data->channel_scale[i] = 0;
482 static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel,
486 u32 tmp, value, status;
488 ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT);
490 dev_err(data->dev, "timeout to get the hwspinlock\n");
495 * According to the sc2721 chip data sheet, the reference voltage of
496 * specific channel 30 and channel 31 in ADC module needs to be set from
497 * the default 2.8v to 3.5v.
499 if ((data->var_data->set_volref) && (channel == 30 || channel == 31)) {
500 ret = regulator_set_voltage(data->volref,
501 SC27XX_ADC_REFVOL_VDD35,
502 SC27XX_ADC_REFVOL_VDD35);
504 dev_err(data->dev, "failed to set the volref 3.5v\n");
509 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
510 SC27XX_ADC_EN, SC27XX_ADC_EN);
512 goto regulator_restore;
514 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR,
515 SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR);
519 /* Configure the channel id and scale */
520 tmp = (scale << data->var_data->scale_shift) & data->var_data->scale_mask;
521 tmp |= channel & SC27XX_ADC_CHN_ID_MASK;
522 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG,
523 SC27XX_ADC_CHN_ID_MASK |
524 data->var_data->scale_mask,
529 /* Select 12bit conversion mode, and only sample 1 time */
530 tmp = SC27XX_ADC_12BIT_MODE;
531 tmp |= (0 << SC27XX_ADC_RUN_NUM_SHIFT) & SC27XX_ADC_RUN_NUM_MASK;
532 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
533 SC27XX_ADC_RUN_NUM_MASK | SC27XX_ADC_12BIT_MODE,
538 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
539 SC27XX_ADC_CHN_RUN, SC27XX_ADC_CHN_RUN);
543 ret = regmap_read_poll_timeout(data->regmap,
544 data->base + SC27XX_ADC_INT_RAW,
545 status, (status & SC27XX_ADC_IRQ_RAW),
546 SC27XX_ADC_POLL_RAW_STATUS,
547 SC27XX_ADC_RDY_TIMEOUT);
549 dev_err(data->dev, "read adc timeout, status = 0x%x\n", status);
553 ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, &value);
557 value &= SC27XX_ADC_DATA_MASK;
560 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
563 if ((data->var_data->set_volref) && (channel == 30 || channel == 31)) {
564 ret_volref = regulator_set_voltage(data->volref,
565 SC27XX_ADC_REFVOL_VDD28,
566 SC27XX_ADC_REFVOL_VDD28);
568 dev_err(data->dev, "failed to set the volref 2.8v,ret_volref = 0x%x\n",
570 ret = ret || ret_volref;
574 hwspin_unlock_raw(data->hwlock);
582 static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data,
583 int channel, int scale,
584 u32 *div_numerator, u32 *div_denominator)
588 ratio = data->var_data->get_ratio(channel, scale);
589 *div_numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET;
590 *div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK;
593 static int adc_to_volt(struct sc27xx_adc_linear_graph *graph,
598 tmp = (graph->volt0 - graph->volt1) * (raw_adc - graph->adc1);
599 tmp /= (graph->adc0 - graph->adc1);
605 static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph,
610 tmp = adc_to_volt(graph, raw_adc);
612 return tmp < 0 ? 0 : tmp;
615 static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel,
616 int scale, int raw_adc)
618 u32 numerator, denominator;
622 * Convert ADC values to voltage values according to the linear graph,
623 * and channel 5 and channel 1 has been calibrated, so we can just
624 * return the voltage values calculated by the linear graph. But other
625 * channels need be calculated to the real voltage values with the
630 return sc27xx_adc_to_volt(&big_scale_graph, raw_adc);
633 return sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
636 volt = sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
640 sc27xx_adc_volt_ratio(data, channel, scale, &numerator, &denominator);
642 return DIV_ROUND_CLOSEST(volt * denominator, numerator);
645 static int sc27xx_adc_read_processed(struct sc27xx_adc_data *data,
646 int channel, int scale, int *val)
650 ret = sc27xx_adc_read(data, channel, scale, &raw_adc);
654 *val = sc27xx_adc_convert_volt(data, channel, scale, raw_adc);
658 static int sc27xx_adc_read_raw(struct iio_dev *indio_dev,
659 struct iio_chan_spec const *chan,
660 int *val, int *val2, long mask)
662 struct sc27xx_adc_data *data = iio_priv(indio_dev);
663 int scale = data->channel_scale[chan->channel];
667 case IIO_CHAN_INFO_RAW:
668 mutex_lock(&indio_dev->mlock);
669 ret = sc27xx_adc_read(data, chan->channel, scale, &tmp);
670 mutex_unlock(&indio_dev->mlock);
678 case IIO_CHAN_INFO_PROCESSED:
679 mutex_lock(&indio_dev->mlock);
680 ret = sc27xx_adc_read_processed(data, chan->channel, scale,
682 mutex_unlock(&indio_dev->mlock);
690 case IIO_CHAN_INFO_SCALE:
699 static int sc27xx_adc_write_raw(struct iio_dev *indio_dev,
700 struct iio_chan_spec const *chan,
701 int val, int val2, long mask)
703 struct sc27xx_adc_data *data = iio_priv(indio_dev);
706 case IIO_CHAN_INFO_SCALE:
707 data->channel_scale[chan->channel] = val;
715 static const struct iio_info sc27xx_info = {
716 .read_raw = &sc27xx_adc_read_raw,
717 .write_raw = &sc27xx_adc_write_raw,
720 #define SC27XX_ADC_CHANNEL(index, mask) { \
721 .type = IIO_VOLTAGE, \
723 .info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE), \
724 .datasheet_name = "CH##index", \
728 static const struct iio_chan_spec sc27xx_channels[] = {
729 SC27XX_ADC_CHANNEL(0, BIT(IIO_CHAN_INFO_PROCESSED)),
730 SC27XX_ADC_CHANNEL(1, BIT(IIO_CHAN_INFO_PROCESSED)),
731 SC27XX_ADC_CHANNEL(2, BIT(IIO_CHAN_INFO_PROCESSED)),
732 SC27XX_ADC_CHANNEL(3, BIT(IIO_CHAN_INFO_PROCESSED)),
733 SC27XX_ADC_CHANNEL(4, BIT(IIO_CHAN_INFO_PROCESSED)),
734 SC27XX_ADC_CHANNEL(5, BIT(IIO_CHAN_INFO_PROCESSED)),
735 SC27XX_ADC_CHANNEL(6, BIT(IIO_CHAN_INFO_PROCESSED)),
736 SC27XX_ADC_CHANNEL(7, BIT(IIO_CHAN_INFO_PROCESSED)),
737 SC27XX_ADC_CHANNEL(8, BIT(IIO_CHAN_INFO_PROCESSED)),
738 SC27XX_ADC_CHANNEL(9, BIT(IIO_CHAN_INFO_PROCESSED)),
739 SC27XX_ADC_CHANNEL(10, BIT(IIO_CHAN_INFO_PROCESSED)),
740 SC27XX_ADC_CHANNEL(11, BIT(IIO_CHAN_INFO_PROCESSED)),
741 SC27XX_ADC_CHANNEL(12, BIT(IIO_CHAN_INFO_PROCESSED)),
742 SC27XX_ADC_CHANNEL(13, BIT(IIO_CHAN_INFO_PROCESSED)),
743 SC27XX_ADC_CHANNEL(14, BIT(IIO_CHAN_INFO_PROCESSED)),
744 SC27XX_ADC_CHANNEL(15, BIT(IIO_CHAN_INFO_PROCESSED)),
745 SC27XX_ADC_CHANNEL(16, BIT(IIO_CHAN_INFO_PROCESSED)),
746 SC27XX_ADC_CHANNEL(17, BIT(IIO_CHAN_INFO_PROCESSED)),
747 SC27XX_ADC_CHANNEL(18, BIT(IIO_CHAN_INFO_PROCESSED)),
748 SC27XX_ADC_CHANNEL(19, BIT(IIO_CHAN_INFO_PROCESSED)),
749 SC27XX_ADC_CHANNEL(20, BIT(IIO_CHAN_INFO_RAW)),
750 SC27XX_ADC_CHANNEL(21, BIT(IIO_CHAN_INFO_PROCESSED)),
751 SC27XX_ADC_CHANNEL(22, BIT(IIO_CHAN_INFO_PROCESSED)),
752 SC27XX_ADC_CHANNEL(23, BIT(IIO_CHAN_INFO_PROCESSED)),
753 SC27XX_ADC_CHANNEL(24, BIT(IIO_CHAN_INFO_PROCESSED)),
754 SC27XX_ADC_CHANNEL(25, BIT(IIO_CHAN_INFO_PROCESSED)),
755 SC27XX_ADC_CHANNEL(26, BIT(IIO_CHAN_INFO_PROCESSED)),
756 SC27XX_ADC_CHANNEL(27, BIT(IIO_CHAN_INFO_PROCESSED)),
757 SC27XX_ADC_CHANNEL(28, BIT(IIO_CHAN_INFO_PROCESSED)),
758 SC27XX_ADC_CHANNEL(29, BIT(IIO_CHAN_INFO_PROCESSED)),
759 SC27XX_ADC_CHANNEL(30, BIT(IIO_CHAN_INFO_PROCESSED)),
760 SC27XX_ADC_CHANNEL(31, BIT(IIO_CHAN_INFO_PROCESSED)),
763 static int sc27xx_adc_enable(struct sc27xx_adc_data *data)
767 ret = regmap_update_bits(data->regmap, data->var_data->module_en,
768 SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN);
772 /* Enable ADC work clock and controller clock */
773 ret = regmap_update_bits(data->regmap, data->var_data->clk_en,
774 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN,
775 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN);
779 /* ADC channel scales' calibration from nvmem device */
780 ret = sc27xx_adc_scale_calibration(data, true);
784 ret = sc27xx_adc_scale_calibration(data, false);
791 regmap_update_bits(data->regmap, data->var_data->clk_en,
792 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
794 regmap_update_bits(data->regmap, data->var_data->module_en,
795 SC27XX_MODULE_ADC_EN, 0);
800 static void sc27xx_adc_disable(void *_data)
802 struct sc27xx_adc_data *data = _data;
804 /* Disable ADC work clock and controller clock */
805 regmap_update_bits(data->regmap, data->var_data->clk_en,
806 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
808 regmap_update_bits(data->regmap, data->var_data->module_en,
809 SC27XX_MODULE_ADC_EN, 0);
812 static const struct sc27xx_adc_variant_data sc2731_data = {
813 .module_en = SC2731_MODULE_EN,
814 .clk_en = SC2731_ARM_CLK_EN,
815 .scale_shift = SC27XX_ADC_SCALE_SHIFT,
816 .scale_mask = SC27XX_ADC_SCALE_MASK,
817 .bscale_cal = &sc2731_big_scale_graph_calib,
818 .sscale_cal = &sc2731_small_scale_graph_calib,
819 .init_scale = sc2731_adc_scale_init,
820 .get_ratio = sc2731_adc_get_ratio,
824 static const struct sc27xx_adc_variant_data sc2730_data = {
825 .module_en = SC2730_MODULE_EN,
826 .clk_en = SC2730_ARM_CLK_EN,
827 .scale_shift = SC27XX_ADC_SCALE_SHIFT,
828 .scale_mask = SC27XX_ADC_SCALE_MASK,
829 .bscale_cal = &big_scale_graph_calib,
830 .sscale_cal = &small_scale_graph_calib,
831 .init_scale = sc2730_adc_scale_init,
832 .get_ratio = sc2730_adc_get_ratio,
836 static const struct sc27xx_adc_variant_data sc2721_data = {
837 .module_en = SC2731_MODULE_EN,
838 .clk_en = SC2721_ARM_CLK_EN,
839 .scale_shift = SC2721_ADC_SCALE_SHIFT,
840 .scale_mask = SC2721_ADC_SCALE_MASK,
841 .bscale_cal = &sc2731_big_scale_graph_calib,
842 .sscale_cal = &sc2731_small_scale_graph_calib,
843 .init_scale = sc2731_adc_scale_init,
844 .get_ratio = sc2721_adc_get_ratio,
848 static const struct sc27xx_adc_variant_data sc2720_data = {
849 .module_en = SC2731_MODULE_EN,
850 .clk_en = SC2721_ARM_CLK_EN,
851 .scale_shift = SC27XX_ADC_SCALE_SHIFT,
852 .scale_mask = SC27XX_ADC_SCALE_MASK,
853 .bscale_cal = &big_scale_graph_calib,
854 .sscale_cal = &small_scale_graph_calib,
855 .init_scale = sc2720_adc_scale_init,
856 .get_ratio = sc2720_adc_get_ratio,
860 static int sc27xx_adc_probe(struct platform_device *pdev)
862 struct device *dev = &pdev->dev;
863 struct device_node *np = dev->of_node;
864 struct sc27xx_adc_data *sc27xx_data;
865 const struct sc27xx_adc_variant_data *pdata;
866 struct iio_dev *indio_dev;
869 pdata = of_device_get_match_data(dev);
871 dev_err(dev, "No matching driver data found\n");
875 indio_dev = devm_iio_device_alloc(dev, sizeof(*sc27xx_data));
879 sc27xx_data = iio_priv(indio_dev);
881 sc27xx_data->regmap = dev_get_regmap(dev->parent, NULL);
882 if (!sc27xx_data->regmap) {
883 dev_err(dev, "failed to get ADC regmap\n");
887 ret = of_property_read_u32(np, "reg", &sc27xx_data->base);
889 dev_err(dev, "failed to get ADC base address\n");
893 sc27xx_data->irq = platform_get_irq(pdev, 0);
894 if (sc27xx_data->irq < 0)
895 return sc27xx_data->irq;
897 ret = of_hwspin_lock_get_id(np, 0);
899 dev_err(dev, "failed to get hwspinlock id\n");
903 sc27xx_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
904 if (!sc27xx_data->hwlock) {
905 dev_err(dev, "failed to request hwspinlock\n");
909 sc27xx_data->dev = dev;
910 if (pdata->set_volref) {
911 sc27xx_data->volref = devm_regulator_get(dev, "vref");
912 if (IS_ERR(sc27xx_data->volref)) {
913 ret = PTR_ERR(sc27xx_data->volref);
914 return dev_err_probe(dev, ret, "failed to get ADC volref\n");
918 sc27xx_data->var_data = pdata;
919 sc27xx_data->var_data->init_scale(sc27xx_data);
921 ret = sc27xx_adc_enable(sc27xx_data);
923 dev_err(dev, "failed to enable ADC module\n");
927 ret = devm_add_action_or_reset(dev, sc27xx_adc_disable, sc27xx_data);
929 dev_err(dev, "failed to add ADC disable action\n");
933 indio_dev->name = dev_name(dev);
934 indio_dev->modes = INDIO_DIRECT_MODE;
935 indio_dev->info = &sc27xx_info;
936 indio_dev->channels = sc27xx_channels;
937 indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels);
938 ret = devm_iio_device_register(dev, indio_dev);
940 dev_err(dev, "could not register iio (ADC)");
945 static const struct of_device_id sc27xx_adc_of_match[] = {
946 { .compatible = "sprd,sc2731-adc", .data = &sc2731_data},
947 { .compatible = "sprd,sc2730-adc", .data = &sc2730_data},
948 { .compatible = "sprd,sc2721-adc", .data = &sc2721_data},
949 { .compatible = "sprd,sc2720-adc", .data = &sc2720_data},
952 MODULE_DEVICE_TABLE(of, sc27xx_adc_of_match);
954 static struct platform_driver sc27xx_adc_driver = {
955 .probe = sc27xx_adc_probe,
957 .name = "sc27xx-adc",
958 .of_match_table = sc27xx_adc_of_match,
962 module_platform_driver(sc27xx_adc_driver);
964 MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
965 MODULE_DESCRIPTION("Spreadtrum SC27XX ADC Driver");
966 MODULE_LICENSE("GPL v2");