1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip Successive Approximation Register (SAR) A/D Converter
4 * Copyright (C) 2014 ROCKCHIP, Inc.
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/interrupt.h>
12 #include <linux/of_device.h>
13 #include <linux/clk.h>
14 #include <linux/completion.h>
15 #include <linux/delay.h>
16 #include <linux/reset.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/iio/buffer.h>
19 #include <linux/iio/iio.h>
20 #include <linux/iio/trigger_consumer.h>
21 #include <linux/iio/triggered_buffer.h>
23 #define SARADC_DATA 0x00
25 #define SARADC_STAS 0x04
26 #define SARADC_STAS_BUSY BIT(0)
28 #define SARADC_CTRL 0x08
29 #define SARADC_CTRL_IRQ_STATUS BIT(6)
30 #define SARADC_CTRL_IRQ_ENABLE BIT(5)
31 #define SARADC_CTRL_POWER_CTRL BIT(3)
32 #define SARADC_CTRL_CHN_MASK 0x7
34 #define SARADC_DLY_PU_SOC 0x0c
35 #define SARADC_DLY_PU_SOC_MASK 0x3f
37 #define SARADC_TIMEOUT msecs_to_jiffies(100)
38 #define SARADC_MAX_CHANNELS 8
40 struct rockchip_saradc_data {
41 const struct iio_chan_spec *channels;
43 unsigned long clk_rate;
46 struct rockchip_saradc {
50 struct completion completion;
51 struct regulator *vref;
53 struct reset_control *reset;
54 const struct rockchip_saradc_data *data;
56 const struct iio_chan_spec *last_chan;
57 struct notifier_block nb;
60 static void rockchip_saradc_power_down(struct rockchip_saradc *info)
62 /* Clear irq & power down adc */
63 writel_relaxed(0, info->regs + SARADC_CTRL);
66 static int rockchip_saradc_conversion(struct rockchip_saradc *info,
67 struct iio_chan_spec const *chan)
69 reinit_completion(&info->completion);
71 /* 8 clock periods as delay between power up and start cmd */
72 writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
74 info->last_chan = chan;
76 /* Select the channel to be used and trigger conversion */
77 writel(SARADC_CTRL_POWER_CTRL
78 | (chan->channel & SARADC_CTRL_CHN_MASK)
79 | SARADC_CTRL_IRQ_ENABLE,
80 info->regs + SARADC_CTRL);
82 if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
88 static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
89 struct iio_chan_spec const *chan,
90 int *val, int *val2, long mask)
92 struct rockchip_saradc *info = iio_priv(indio_dev);
96 case IIO_CHAN_INFO_RAW:
97 mutex_lock(&indio_dev->mlock);
99 ret = rockchip_saradc_conversion(info, chan);
101 rockchip_saradc_power_down(info);
102 mutex_unlock(&indio_dev->mlock);
106 *val = info->last_val;
107 mutex_unlock(&indio_dev->mlock);
109 case IIO_CHAN_INFO_SCALE:
110 *val = info->uv_vref / 1000;
111 *val2 = chan->scan_type.realbits;
112 return IIO_VAL_FRACTIONAL_LOG2;
118 static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
120 struct rockchip_saradc *info = dev_id;
123 info->last_val = readl_relaxed(info->regs + SARADC_DATA);
124 info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
126 rockchip_saradc_power_down(info);
128 complete(&info->completion);
133 static const struct iio_info rockchip_saradc_iio_info = {
134 .read_raw = rockchip_saradc_read_raw,
137 #define SARADC_CHANNEL(_index, _id, _res) { \
138 .type = IIO_VOLTAGE, \
141 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
142 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
143 .datasheet_name = _id, \
144 .scan_index = _index, \
149 .endianness = IIO_CPU, \
153 static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
154 SARADC_CHANNEL(0, "adc0", 10),
155 SARADC_CHANNEL(1, "adc1", 10),
156 SARADC_CHANNEL(2, "adc2", 10),
159 static const struct rockchip_saradc_data saradc_data = {
160 .channels = rockchip_saradc_iio_channels,
161 .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
165 static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
166 SARADC_CHANNEL(0, "adc0", 12),
167 SARADC_CHANNEL(1, "adc1", 12),
170 static const struct rockchip_saradc_data rk3066_tsadc_data = {
171 .channels = rockchip_rk3066_tsadc_iio_channels,
172 .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
176 static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
177 SARADC_CHANNEL(0, "adc0", 10),
178 SARADC_CHANNEL(1, "adc1", 10),
179 SARADC_CHANNEL(2, "adc2", 10),
180 SARADC_CHANNEL(3, "adc3", 10),
181 SARADC_CHANNEL(4, "adc4", 10),
182 SARADC_CHANNEL(5, "adc5", 10),
185 static const struct rockchip_saradc_data rk3399_saradc_data = {
186 .channels = rockchip_rk3399_saradc_iio_channels,
187 .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
191 static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
192 SARADC_CHANNEL(0, "adc0", 10),
193 SARADC_CHANNEL(1, "adc1", 10),
194 SARADC_CHANNEL(2, "adc2", 10),
195 SARADC_CHANNEL(3, "adc3", 10),
196 SARADC_CHANNEL(4, "adc4", 10),
197 SARADC_CHANNEL(5, "adc5", 10),
198 SARADC_CHANNEL(6, "adc6", 10),
199 SARADC_CHANNEL(7, "adc7", 10),
202 static const struct rockchip_saradc_data rk3568_saradc_data = {
203 .channels = rockchip_rk3568_saradc_iio_channels,
204 .num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
208 static const struct of_device_id rockchip_saradc_match[] = {
210 .compatible = "rockchip,saradc",
211 .data = &saradc_data,
213 .compatible = "rockchip,rk3066-tsadc",
214 .data = &rk3066_tsadc_data,
216 .compatible = "rockchip,rk3399-saradc",
217 .data = &rk3399_saradc_data,
219 .compatible = "rockchip,rk3568-saradc",
220 .data = &rk3568_saradc_data,
224 MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
227 * Reset SARADC Controller.
229 static void rockchip_saradc_reset_controller(struct reset_control *reset)
231 reset_control_assert(reset);
232 usleep_range(10, 20);
233 reset_control_deassert(reset);
236 static void rockchip_saradc_clk_disable(void *data)
238 struct rockchip_saradc *info = data;
240 clk_disable_unprepare(info->clk);
243 static void rockchip_saradc_pclk_disable(void *data)
245 struct rockchip_saradc *info = data;
247 clk_disable_unprepare(info->pclk);
250 static void rockchip_saradc_regulator_disable(void *data)
252 struct rockchip_saradc *info = data;
254 regulator_disable(info->vref);
257 static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p)
259 struct iio_poll_func *pf = p;
260 struct iio_dev *i_dev = pf->indio_dev;
261 struct rockchip_saradc *info = iio_priv(i_dev);
263 * @values: each channel takes an u16 value
264 * @timestamp: will be 8-byte aligned automatically
267 u16 values[SARADC_MAX_CHANNELS];
273 mutex_lock(&i_dev->mlock);
275 for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) {
276 const struct iio_chan_spec *chan = &i_dev->channels[i];
278 ret = rockchip_saradc_conversion(info, chan);
280 rockchip_saradc_power_down(info);
284 data.values[j] = info->last_val;
288 iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev));
290 mutex_unlock(&i_dev->mlock);
292 iio_trigger_notify_done(i_dev->trig);
297 static int rockchip_saradc_volt_notify(struct notifier_block *nb,
301 struct rockchip_saradc *info =
302 container_of(nb, struct rockchip_saradc, nb);
304 if (event & REGULATOR_EVENT_VOLTAGE_CHANGE)
305 info->uv_vref = (unsigned long)data;
310 static void rockchip_saradc_regulator_unreg_notifier(void *data)
312 struct rockchip_saradc *info = data;
314 regulator_unregister_notifier(info->vref, &info->nb);
317 static int rockchip_saradc_probe(struct platform_device *pdev)
319 struct rockchip_saradc *info = NULL;
320 struct device_node *np = pdev->dev.of_node;
321 struct iio_dev *indio_dev = NULL;
322 const struct of_device_id *match;
329 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
331 dev_err(&pdev->dev, "failed allocating iio device\n");
334 info = iio_priv(indio_dev);
336 match = of_match_device(rockchip_saradc_match, &pdev->dev);
338 dev_err(&pdev->dev, "failed to match device\n");
342 info->data = match->data;
344 /* Sanity check for possible later IP variants with more channels */
345 if (info->data->num_channels > SARADC_MAX_CHANNELS) {
346 dev_err(&pdev->dev, "max channels exceeded");
350 info->regs = devm_platform_ioremap_resource(pdev, 0);
351 if (IS_ERR(info->regs))
352 return PTR_ERR(info->regs);
355 * The reset should be an optional property, as it should work
356 * with old devicetrees as well
358 info->reset = devm_reset_control_get_exclusive(&pdev->dev,
360 if (IS_ERR(info->reset)) {
361 ret = PTR_ERR(info->reset);
363 return dev_err_probe(&pdev->dev, ret,
364 "failed to get saradc-apb\n");
366 dev_dbg(&pdev->dev, "no reset control found\n");
370 init_completion(&info->completion);
372 irq = platform_get_irq(pdev, 0);
374 return dev_err_probe(&pdev->dev, irq, "failed to get irq\n");
376 ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
377 0, dev_name(&pdev->dev), info);
379 dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
383 info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
384 if (IS_ERR(info->pclk))
385 return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
386 "failed to get pclk\n");
388 info->clk = devm_clk_get(&pdev->dev, "saradc");
389 if (IS_ERR(info->clk))
390 return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
391 "failed to get adc clock\n");
393 info->vref = devm_regulator_get(&pdev->dev, "vref");
394 if (IS_ERR(info->vref))
395 return dev_err_probe(&pdev->dev, PTR_ERR(info->vref),
396 "failed to get regulator\n");
399 rockchip_saradc_reset_controller(info->reset);
402 * Use a default value for the converter clock.
403 * This may become user-configurable in the future.
405 ret = clk_set_rate(info->clk, info->data->clk_rate);
407 dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
411 ret = regulator_enable(info->vref);
413 dev_err(&pdev->dev, "failed to enable vref regulator\n");
416 ret = devm_add_action_or_reset(&pdev->dev,
417 rockchip_saradc_regulator_disable, info);
419 dev_err(&pdev->dev, "failed to register devm action, %d\n",
424 ret = regulator_get_voltage(info->vref);
430 ret = clk_prepare_enable(info->pclk);
432 dev_err(&pdev->dev, "failed to enable pclk\n");
435 ret = devm_add_action_or_reset(&pdev->dev,
436 rockchip_saradc_pclk_disable, info);
438 dev_err(&pdev->dev, "failed to register devm action, %d\n",
443 ret = clk_prepare_enable(info->clk);
445 dev_err(&pdev->dev, "failed to enable converter clock\n");
448 ret = devm_add_action_or_reset(&pdev->dev,
449 rockchip_saradc_clk_disable, info);
451 dev_err(&pdev->dev, "failed to register devm action, %d\n",
456 platform_set_drvdata(pdev, indio_dev);
458 indio_dev->name = dev_name(&pdev->dev);
459 indio_dev->info = &rockchip_saradc_iio_info;
460 indio_dev->modes = INDIO_DIRECT_MODE;
462 indio_dev->channels = info->data->channels;
463 indio_dev->num_channels = info->data->num_channels;
464 ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL,
465 rockchip_saradc_trigger_handler,
470 info->nb.notifier_call = rockchip_saradc_volt_notify;
471 ret = regulator_register_notifier(info->vref, &info->nb);
475 ret = devm_add_action_or_reset(&pdev->dev,
476 rockchip_saradc_regulator_unreg_notifier,
481 return devm_iio_device_register(&pdev->dev, indio_dev);
484 static int rockchip_saradc_suspend(struct device *dev)
486 struct iio_dev *indio_dev = dev_get_drvdata(dev);
487 struct rockchip_saradc *info = iio_priv(indio_dev);
489 clk_disable_unprepare(info->clk);
490 clk_disable_unprepare(info->pclk);
491 regulator_disable(info->vref);
496 static int rockchip_saradc_resume(struct device *dev)
498 struct iio_dev *indio_dev = dev_get_drvdata(dev);
499 struct rockchip_saradc *info = iio_priv(indio_dev);
502 ret = regulator_enable(info->vref);
506 ret = clk_prepare_enable(info->pclk);
510 ret = clk_prepare_enable(info->clk);
512 clk_disable_unprepare(info->pclk);
517 static DEFINE_SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
518 rockchip_saradc_suspend,
519 rockchip_saradc_resume);
521 static struct platform_driver rockchip_saradc_driver = {
522 .probe = rockchip_saradc_probe,
524 .name = "rockchip-saradc",
525 .of_match_table = rockchip_saradc_match,
526 .pm = pm_sleep_ptr(&rockchip_saradc_pm_ops),
530 module_platform_driver(rockchip_saradc_driver);
532 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
533 MODULE_DESCRIPTION("Rockchip SARADC driver");
534 MODULE_LICENSE("GPL v2");