1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2017, 2019, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022 Linaro Limited.
5 * Author: Caleb Connolly <caleb.connolly@linaro.org>
7 * This driver is for the Round Robin ADC found in the pmi8998 and pm660 PMICs.
10 #include <linux/bitfield.h>
11 #include <linux/delay.h>
12 #include <linux/kernel.h>
13 #include <linux/math64.h>
14 #include <linux/module.h>
15 #include <linux/mod_devicetable.h>
16 #include <linux/platform_device.h>
17 #include <linux/property.h>
18 #include <linux/regmap.h>
19 #include <linux/spmi.h>
20 #include <linux/types.h>
21 #include <linux/units.h>
23 #include <asm/unaligned.h>
25 #include <linux/iio/iio.h>
26 #include <linux/iio/types.h>
28 #include <soc/qcom/qcom-spmi-pmic.h>
30 #define DRIVER_NAME "qcom-spmi-rradc"
32 #define RR_ADC_EN_CTL 0x46
33 #define RR_ADC_SKIN_TEMP_LSB 0x50
34 #define RR_ADC_SKIN_TEMP_MSB 0x51
35 #define RR_ADC_CTL 0x52
36 #define RR_ADC_CTL_CONTINUOUS_SEL BIT(3)
37 #define RR_ADC_LOG 0x53
38 #define RR_ADC_LOG_CLR_CTRL BIT(0)
40 #define RR_ADC_FAKE_BATT_LOW_LSB 0x58
41 #define RR_ADC_FAKE_BATT_LOW_MSB 0x59
42 #define RR_ADC_FAKE_BATT_HIGH_LSB 0x5A
43 #define RR_ADC_FAKE_BATT_HIGH_MSB 0x5B
45 #define RR_ADC_BATT_ID_CTRL 0x60
46 #define RR_ADC_BATT_ID_CTRL_CHANNEL_CONV BIT(0)
47 #define RR_ADC_BATT_ID_TRIGGER 0x61
48 #define RR_ADC_BATT_ID_STS 0x62
49 #define RR_ADC_BATT_ID_CFG 0x63
50 #define BATT_ID_SETTLE_MASK GENMASK(7, 5)
51 #define RR_ADC_BATT_ID_5_LSB 0x66
52 #define RR_ADC_BATT_ID_5_MSB 0x67
53 #define RR_ADC_BATT_ID_15_LSB 0x68
54 #define RR_ADC_BATT_ID_15_MSB 0x69
55 #define RR_ADC_BATT_ID_150_LSB 0x6A
56 #define RR_ADC_BATT_ID_150_MSB 0x6B
58 #define RR_ADC_BATT_THERM_CTRL 0x70
59 #define RR_ADC_BATT_THERM_TRIGGER 0x71
60 #define RR_ADC_BATT_THERM_STS 0x72
61 #define RR_ADC_BATT_THERM_CFG 0x73
62 #define RR_ADC_BATT_THERM_LSB 0x74
63 #define RR_ADC_BATT_THERM_MSB 0x75
64 #define RR_ADC_BATT_THERM_FREQ 0x76
66 #define RR_ADC_AUX_THERM_CTRL 0x80
67 #define RR_ADC_AUX_THERM_TRIGGER 0x81
68 #define RR_ADC_AUX_THERM_STS 0x82
69 #define RR_ADC_AUX_THERM_CFG 0x83
70 #define RR_ADC_AUX_THERM_LSB 0x84
71 #define RR_ADC_AUX_THERM_MSB 0x85
73 #define RR_ADC_SKIN_HOT 0x86
74 #define RR_ADC_SKIN_TOO_HOT 0x87
76 #define RR_ADC_AUX_THERM_C1 0x88
77 #define RR_ADC_AUX_THERM_C2 0x89
78 #define RR_ADC_AUX_THERM_C3 0x8A
79 #define RR_ADC_AUX_THERM_HALF_RANGE 0x8B
81 #define RR_ADC_USB_IN_V_CTRL 0x90
82 #define RR_ADC_USB_IN_V_TRIGGER 0x91
83 #define RR_ADC_USB_IN_V_STS 0x92
84 #define RR_ADC_USB_IN_V_LSB 0x94
85 #define RR_ADC_USB_IN_V_MSB 0x95
86 #define RR_ADC_USB_IN_I_CTRL 0x98
87 #define RR_ADC_USB_IN_I_TRIGGER 0x99
88 #define RR_ADC_USB_IN_I_STS 0x9A
89 #define RR_ADC_USB_IN_I_LSB 0x9C
90 #define RR_ADC_USB_IN_I_MSB 0x9D
92 #define RR_ADC_DC_IN_V_CTRL 0xA0
93 #define RR_ADC_DC_IN_V_TRIGGER 0xA1
94 #define RR_ADC_DC_IN_V_STS 0xA2
95 #define RR_ADC_DC_IN_V_LSB 0xA4
96 #define RR_ADC_DC_IN_V_MSB 0xA5
97 #define RR_ADC_DC_IN_I_CTRL 0xA8
98 #define RR_ADC_DC_IN_I_TRIGGER 0xA9
99 #define RR_ADC_DC_IN_I_STS 0xAA
100 #define RR_ADC_DC_IN_I_LSB 0xAC
101 #define RR_ADC_DC_IN_I_MSB 0xAD
103 #define RR_ADC_PMI_DIE_TEMP_CTRL 0xB0
104 #define RR_ADC_PMI_DIE_TEMP_TRIGGER 0xB1
105 #define RR_ADC_PMI_DIE_TEMP_STS 0xB2
106 #define RR_ADC_PMI_DIE_TEMP_CFG 0xB3
107 #define RR_ADC_PMI_DIE_TEMP_LSB 0xB4
108 #define RR_ADC_PMI_DIE_TEMP_MSB 0xB5
110 #define RR_ADC_CHARGER_TEMP_CTRL 0xB8
111 #define RR_ADC_CHARGER_TEMP_TRIGGER 0xB9
112 #define RR_ADC_CHARGER_TEMP_STS 0xBA
113 #define RR_ADC_CHARGER_TEMP_CFG 0xBB
114 #define RR_ADC_CHARGER_TEMP_LSB 0xBC
115 #define RR_ADC_CHARGER_TEMP_MSB 0xBD
116 #define RR_ADC_CHARGER_HOT 0xBE
117 #define RR_ADC_CHARGER_TOO_HOT 0xBF
119 #define RR_ADC_GPIO_CTRL 0xC0
120 #define RR_ADC_GPIO_TRIGGER 0xC1
121 #define RR_ADC_GPIO_STS 0xC2
122 #define RR_ADC_GPIO_LSB 0xC4
123 #define RR_ADC_GPIO_MSB 0xC5
125 #define RR_ADC_ATEST_CTRL 0xC8
126 #define RR_ADC_ATEST_TRIGGER 0xC9
127 #define RR_ADC_ATEST_STS 0xCA
128 #define RR_ADC_ATEST_LSB 0xCC
129 #define RR_ADC_ATEST_MSB 0xCD
130 #define RR_ADC_SEC_ACCESS 0xD0
132 #define RR_ADC_PERPH_RESET_CTL2 0xD9
133 #define RR_ADC_PERPH_RESET_CTL3 0xDA
134 #define RR_ADC_PERPH_RESET_CTL4 0xDB
135 #define RR_ADC_INT_TEST1 0xE0
136 #define RR_ADC_INT_TEST_VAL 0xE1
138 #define RR_ADC_TM_TRIGGER_CTRLS 0xE2
139 #define RR_ADC_TM_ADC_CTRLS 0xE3
140 #define RR_ADC_TM_CNL_CTRL 0xE4
141 #define RR_ADC_TM_BATT_ID_CTRL 0xE5
142 #define RR_ADC_TM_THERM_CTRL 0xE6
143 #define RR_ADC_TM_CONV_STS 0xE7
144 #define RR_ADC_TM_ADC_READ_LSB 0xE8
145 #define RR_ADC_TM_ADC_READ_MSB 0xE9
146 #define RR_ADC_TM_ATEST_MUX_1 0xEA
147 #define RR_ADC_TM_ATEST_MUX_2 0xEB
148 #define RR_ADC_TM_REFERENCES 0xED
149 #define RR_ADC_TM_MISC_CTL 0xEE
150 #define RR_ADC_TM_RR_CTRL 0xEF
152 #define RR_ADC_TRIGGER_EVERY_CYCLE BIT(7)
153 #define RR_ADC_TRIGGER_CTL BIT(0)
155 #define RR_ADC_BATT_ID_RANGE 820
157 #define RR_ADC_BITS 10
158 #define RR_ADC_CHAN_MSB (1 << RR_ADC_BITS)
159 #define RR_ADC_FS_VOLTAGE_MV 2500
161 /* BATT_THERM 0.25K/LSB */
162 #define RR_ADC_BATT_THERM_LSB_K 4
164 #define RR_ADC_TEMP_FS_VOLTAGE_NUM 5000000
165 #define RR_ADC_TEMP_FS_VOLTAGE_DEN 3
166 #define RR_ADC_DIE_TEMP_OFFSET 601400
167 #define RR_ADC_DIE_TEMP_SLOPE 2
168 #define RR_ADC_DIE_TEMP_OFFSET_MILLI_DEGC 25000
170 #define RR_ADC_CHG_TEMP_GF_OFFSET_UV 1303168
171 #define RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C 3784
172 #define RR_ADC_CHG_TEMP_SMIC_OFFSET_UV 1338433
173 #define RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C 3655
174 #define RR_ADC_CHG_TEMP_660_GF_OFFSET_UV 1309001
175 #define RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C 3403
176 #define RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV 1295898
177 #define RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C 3596
178 #define RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV 1314779
179 #define RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C 3496
180 #define RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC 25000
181 #define RR_ADC_CHG_THRESHOLD_SCALE 4
183 #define RR_ADC_VOLT_INPUT_FACTOR 8
184 #define RR_ADC_CURR_INPUT_FACTOR 2000
185 #define RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL 1886
186 #define RR_ADC_CURR_USBIN_660_FACTOR_MIL 9
187 #define RR_ADC_CURR_USBIN_660_UV_VAL 579500
189 #define RR_ADC_GPIO_FS_RANGE 5000
190 #define RR_ADC_COHERENT_CHECK_RETRY 5
191 #define RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN 16
193 #define RR_ADC_STS_CHANNEL_READING_MASK GENMASK(1, 0)
194 #define RR_ADC_STS_CHANNEL_STS BIT(1)
196 #define RR_ADC_TP_REV_VERSION1 21
197 #define RR_ADC_TP_REV_VERSION2 29
198 #define RR_ADC_TP_REV_VERSION3 32
200 #define RRADC_BATT_ID_DELAY_MAX 8
202 enum rradc_channel_id {
219 * struct rradc_channel - rradc channel data
220 * @label: channel label
221 * @lsb: Channel least significant byte
222 * @status: Channel status address
223 * @size: number of bytes to read
224 * @trigger_addr: Trigger address, trigger is only used on some channels
225 * @trigger_mask: Trigger mask
226 * @scale_fn: Post process callback for channels which can't be exposed
229 struct rradc_channel {
236 int (*scale_fn)(struct rradc_chip *chip, u16 adc_code, int *result);
241 const struct qcom_spmi_pmic *pmic;
243 * Lock held while doing channel conversion
244 * involving multiple register read/writes
246 struct mutex conversion_lock;
247 struct regmap *regmap;
253 static const int batt_id_delays[] = { 0, 1, 4, 12, 20, 40, 60, 80 };
254 static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX];
255 static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX];
257 static int rradc_read(struct rradc_chip *chip, u16 addr, __le16 *buf, int len)
259 int ret, retry_cnt = 0;
260 __le16 data_check[RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN / 2];
262 if (len > RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN) {
264 "Can't read more than %d bytes, but asked to read %d bytes.\n",
265 RR_ADC_CHAN_MAX_CONTINUOUS_BUFFER_LEN, len);
269 while (retry_cnt < RR_ADC_COHERENT_CHECK_RETRY) {
270 ret = regmap_bulk_read(chip->regmap, chip->base + addr, buf,
273 dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr,
278 ret = regmap_bulk_read(chip->regmap, chip->base + addr,
281 dev_err(chip->dev, "rr_adc reg 0x%x failed :%d\n", addr,
286 if (memcmp(buf, data_check, len) != 0) {
289 "coherent read error, retry_cnt:%d\n",
297 if (retry_cnt == RR_ADC_COHERENT_CHECK_RETRY)
298 dev_err(chip->dev, "Retry exceeded for coherency check\n");
303 static int rradc_get_fab_coeff(struct rradc_chip *chip, int64_t *offset,
306 if (chip->pmic->subtype == PM660_SUBTYPE) {
307 switch (chip->pmic->fab_id) {
308 case PM660_FAB_ID_GF:
309 *offset = RR_ADC_CHG_TEMP_660_GF_OFFSET_UV;
310 *slope = RR_ADC_CHG_TEMP_660_GF_SLOPE_UV_PER_C;
312 case PM660_FAB_ID_TSMC:
313 *offset = RR_ADC_CHG_TEMP_660_SMIC_OFFSET_UV;
314 *slope = RR_ADC_CHG_TEMP_660_SMIC_SLOPE_UV_PER_C;
317 *offset = RR_ADC_CHG_TEMP_660_MGNA_OFFSET_UV;
318 *slope = RR_ADC_CHG_TEMP_660_MGNA_SLOPE_UV_PER_C;
320 } else if (chip->pmic->subtype == PMI8998_SUBTYPE) {
321 switch (chip->pmic->fab_id) {
322 case PMI8998_FAB_ID_GF:
323 *offset = RR_ADC_CHG_TEMP_GF_OFFSET_UV;
324 *slope = RR_ADC_CHG_TEMP_GF_SLOPE_UV_PER_C;
326 case PMI8998_FAB_ID_SMIC:
327 *offset = RR_ADC_CHG_TEMP_SMIC_OFFSET_UV;
328 *slope = RR_ADC_CHG_TEMP_SMIC_SLOPE_UV_PER_C;
339 * These functions explicitly cast int64_t to int.
340 * They will never overflow, as the values are small enough.
342 static int rradc_post_process_batt_id(struct rradc_chip *chip, u16 adc_code,
345 uint32_t current_value;
348 current_value = chip->batt_id_data;
349 r_id = ((int64_t)adc_code * RR_ADC_FS_VOLTAGE_MV);
350 r_id = div64_s64(r_id, (RR_ADC_CHAN_MSB * current_value));
351 *result_ohms = (int)(r_id * MILLI);
356 static int rradc_enable_continuous_mode(struct rradc_chip *chip)
360 /* Clear channel log */
361 ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG,
362 RR_ADC_LOG_CLR_CTRL, RR_ADC_LOG_CLR_CTRL);
364 dev_err(chip->dev, "log ctrl update to clear failed:%d\n", ret);
368 ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_LOG,
369 RR_ADC_LOG_CLR_CTRL, 0);
371 dev_err(chip->dev, "log ctrl update to not clear failed:%d\n",
376 /* Switch to continuous mode */
377 ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL,
378 RR_ADC_CTL_CONTINUOUS_SEL,
379 RR_ADC_CTL_CONTINUOUS_SEL);
381 dev_err(chip->dev, "Update to continuous mode failed:%d\n",
387 static int rradc_disable_continuous_mode(struct rradc_chip *chip)
391 /* Switch to non continuous mode */
392 ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_CTL,
393 RR_ADC_CTL_CONTINUOUS_SEL, 0);
395 dev_err(chip->dev, "Update to non-continuous mode failed:%d\n",
401 static bool rradc_is_ready(struct rradc_chip *chip,
402 enum rradc_channel_id chan_address)
404 const struct rradc_channel *chan = &rradc_chans[chan_address];
406 unsigned int status, mask;
408 /* BATT_ID STS bit does not get set initially */
409 switch (chan_address) {
411 mask = RR_ADC_STS_CHANNEL_STS;
414 mask = RR_ADC_STS_CHANNEL_READING_MASK;
418 ret = regmap_read(chip->regmap, chip->base + chan->status, &status);
419 if (ret < 0 || !(status & mask))
425 static int rradc_read_status_in_cont_mode(struct rradc_chip *chip,
426 enum rradc_channel_id chan_address)
428 const struct rradc_channel *chan = &rradc_chans[chan_address];
429 const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address];
432 if (chan->trigger_mask == 0) {
433 dev_err(chip->dev, "Channel doesn't have a trigger mask\n");
437 ret = regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr,
438 chan->trigger_mask, chan->trigger_mask);
441 "Failed to apply trigger for channel '%s' ret=%d\n",
442 iio_chan->extend_name, ret);
446 ret = rradc_enable_continuous_mode(chip);
448 dev_err(chip->dev, "Failed to switch to continuous mode\n");
449 goto disable_trigger;
453 * The wait/sleep values were found through trial and error,
454 * this is mostly for the battery ID channel which takes some
457 for (i = 0; i < 5; i++) {
458 if (rradc_is_ready(chip, chan_address))
460 usleep_range(50000, 50000 + 500);
464 dev_err(chip->dev, "Channel '%s' is not ready\n",
465 iio_chan->extend_name);
469 rradc_disable_continuous_mode(chip);
472 regmap_update_bits(chip->regmap, chip->base + chan->trigger_addr,
473 chan->trigger_mask, 0);
478 static int rradc_prepare_batt_id_conversion(struct rradc_chip *chip,
479 enum rradc_channel_id chan_address,
484 ret = regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL,
485 RR_ADC_BATT_ID_CTRL_CHANNEL_CONV,
486 RR_ADC_BATT_ID_CTRL_CHANNEL_CONV);
488 dev_err(chip->dev, "Enabling BATT ID channel failed:%d\n", ret);
492 ret = regmap_update_bits(chip->regmap,
493 chip->base + RR_ADC_BATT_ID_TRIGGER,
494 RR_ADC_TRIGGER_CTL, RR_ADC_TRIGGER_CTL);
496 dev_err(chip->dev, "BATT_ID trigger set failed:%d\n", ret);
497 goto out_disable_batt_id;
500 ret = rradc_read_status_in_cont_mode(chip, chan_address);
502 /* Reset registers back to default values */
503 regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_TRIGGER,
504 RR_ADC_TRIGGER_CTL, 0);
507 regmap_update_bits(chip->regmap, chip->base + RR_ADC_BATT_ID_CTRL,
508 RR_ADC_BATT_ID_CTRL_CHANNEL_CONV, 0);
513 static int rradc_do_conversion(struct rradc_chip *chip,
514 enum rradc_channel_id chan_address, u16 *data)
516 const struct rradc_channel *chan = &rradc_chans[chan_address];
517 const struct iio_chan_spec *iio_chan = &rradc_iio_chans[chan_address];
521 mutex_lock(&chip->conversion_lock);
523 switch (chan_address) {
525 ret = rradc_prepare_batt_id_conversion(chip, chan_address, data);
527 dev_err(chip->dev, "Battery ID conversion failed:%d\n",
534 case RR_ADC_DIE_TEMP:
535 ret = rradc_read_status_in_cont_mode(chip, chan_address);
538 "Error reading in continuous mode:%d\n", ret);
543 if (!rradc_is_ready(chip, chan_address)) {
545 * Usually this means the channel isn't attached, for example
546 * the in_voltage_usbin_v_input channel will not be ready if
547 * no USB cable is attached
549 dev_dbg(chip->dev, "channel '%s' is not ready\n",
550 iio_chan->extend_name);
557 ret = rradc_read(chip, chan->lsb, buf, chan->size);
559 dev_err(chip->dev, "read data failed\n");
564 * For the battery ID we read the register for every ID ADC and then
565 * see which one is actually connected.
567 if (chan_address == RR_ADC_BATT_ID) {
568 u16 batt_id_150 = le16_to_cpu(buf[2]);
569 u16 batt_id_15 = le16_to_cpu(buf[1]);
570 u16 batt_id_5 = le16_to_cpu(buf[0]);
572 if (!batt_id_150 && !batt_id_15 && !batt_id_5) {
574 "Invalid batt_id values with all zeros\n");
579 if (batt_id_150 <= RR_ADC_BATT_ID_RANGE) {
581 chip->batt_id_data = 150;
582 } else if (batt_id_15 <= RR_ADC_BATT_ID_RANGE) {
584 chip->batt_id_data = 15;
587 chip->batt_id_data = 5;
591 * All of the other channels are either 1 or 2 bytes.
592 * We can rely on the second byte being 0 for 1-byte channels.
594 *data = le16_to_cpu(buf[0]);
598 mutex_unlock(&chip->conversion_lock);
603 static int rradc_read_scale(struct rradc_chip *chip, int chan_address, int *val,
606 int64_t fab_offset, fab_slope;
609 ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope);
611 dev_err(chip->dev, "Unable to get fab id coefficients\n");
615 switch (chan_address) {
616 case RR_ADC_SKIN_TEMP:
618 *val2 = RR_ADC_BATT_THERM_LSB_K;
619 return IIO_VAL_FRACTIONAL;
621 *val = RR_ADC_CURR_USBIN_INPUT_FACTOR_MIL *
622 RR_ADC_FS_VOLTAGE_MV;
623 *val2 = RR_ADC_CHAN_MSB;
624 return IIO_VAL_FRACTIONAL;
626 *val = RR_ADC_CURR_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV;
627 *val2 = RR_ADC_CHAN_MSB;
628 return IIO_VAL_FRACTIONAL;
631 *val = RR_ADC_VOLT_INPUT_FACTOR * RR_ADC_FS_VOLTAGE_MV * MILLI;
632 *val2 = RR_ADC_CHAN_MSB;
633 return IIO_VAL_FRACTIONAL;
635 *val = RR_ADC_GPIO_FS_RANGE;
636 *val2 = RR_ADC_CHAN_MSB;
637 return IIO_VAL_FRACTIONAL;
638 case RR_ADC_CHG_TEMP:
640 * We divide val2 by MILLI instead of multiplying val
641 * to avoid an integer overflow.
643 *val = -RR_ADC_TEMP_FS_VOLTAGE_NUM;
644 *val2 = div64_s64(RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
648 return IIO_VAL_FRACTIONAL;
649 case RR_ADC_DIE_TEMP:
650 *val = RR_ADC_TEMP_FS_VOLTAGE_NUM;
651 *val2 = RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
652 RR_ADC_DIE_TEMP_SLOPE;
654 return IIO_VAL_FRACTIONAL;
660 static int rradc_read_offset(struct rradc_chip *chip, int chan_address, int *val)
662 int64_t fab_offset, fab_slope;
663 int64_t offset1, offset2;
666 switch (chan_address) {
667 case RR_ADC_SKIN_TEMP:
669 * Offset from kelvin to degC, divided by the
670 * scale factor (250). We lose some precision here.
671 * 273150 / 250 = 1092.6
673 *val = div64_s64(ABSOLUTE_ZERO_MILLICELSIUS,
674 (MILLI / RR_ADC_BATT_THERM_LSB_K));
676 case RR_ADC_CHG_TEMP:
677 ret = rradc_get_fab_coeff(chip, &fab_offset, &fab_slope);
680 "Unable to get fab id coefficients\n");
683 offset1 = -(fab_offset * RR_ADC_TEMP_FS_VOLTAGE_DEN *
685 offset1 += (int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM / 2ULL;
686 offset1 = div64_s64(offset1,
687 (int64_t)(RR_ADC_TEMP_FS_VOLTAGE_NUM));
689 offset2 = (int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC *
690 RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
692 offset2 += ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM) / 2;
694 offset2, ((int64_t)MILLI * RR_ADC_TEMP_FS_VOLTAGE_NUM));
697 * The -1 is to compensate for lost precision.
698 * It should actually be -0.7906976744186046.
699 * This works out to every value being off
700 * by about +0.091 degrees C after applying offset and scale.
702 *val = (int)(offset1 - offset2 - 1);
704 case RR_ADC_DIE_TEMP:
705 offset1 = -RR_ADC_DIE_TEMP_OFFSET *
706 (int64_t)RR_ADC_TEMP_FS_VOLTAGE_DEN *
707 (int64_t)RR_ADC_CHAN_MSB;
708 offset1 = div64_s64(offset1, RR_ADC_TEMP_FS_VOLTAGE_NUM);
710 offset2 = -(int64_t)RR_ADC_CHG_TEMP_OFFSET_MILLI_DEGC *
711 RR_ADC_TEMP_FS_VOLTAGE_DEN * RR_ADC_CHAN_MSB *
712 RR_ADC_DIE_TEMP_SLOPE;
713 offset2 = div64_s64(offset2,
714 ((int64_t)RR_ADC_TEMP_FS_VOLTAGE_NUM));
717 * The result is -339, it should be -338.69789, this results
718 * in the calculated die temp being off by
719 * -0.004 - -0.0175 degrees C
721 *val = (int)(offset1 - offset2);
729 static int rradc_read_raw(struct iio_dev *indio_dev,
730 struct iio_chan_spec const *chan_spec, int *val,
731 int *val2, long mask)
733 struct rradc_chip *chip = iio_priv(indio_dev);
734 const struct rradc_channel *chan;
738 if (chan_spec->address >= RR_ADC_CHAN_MAX) {
739 dev_err(chip->dev, "Invalid channel index:%lu\n",
745 case IIO_CHAN_INFO_SCALE:
746 return rradc_read_scale(chip, chan_spec->address, val, val2);
747 case IIO_CHAN_INFO_OFFSET:
748 return rradc_read_offset(chip, chan_spec->address, val);
749 case IIO_CHAN_INFO_RAW:
750 ret = rradc_do_conversion(chip, chan_spec->address, &adc_code);
756 case IIO_CHAN_INFO_PROCESSED:
757 chan = &rradc_chans[chan_spec->address];
760 ret = rradc_do_conversion(chip, chan_spec->address, &adc_code);
764 *val = chan->scale_fn(chip, adc_code, val);
771 static int rradc_read_label(struct iio_dev *indio_dev,
772 struct iio_chan_spec const *chan, char *label)
774 return snprintf(label, PAGE_SIZE, "%s\n",
775 rradc_chans[chan->address].label);
778 static const struct iio_info rradc_info = {
779 .read_raw = rradc_read_raw,
780 .read_label = rradc_read_label,
783 static const struct rradc_channel rradc_chans[RR_ADC_CHAN_MAX] = {
786 .scale_fn = rradc_post_process_batt_id,
787 .lsb = RR_ADC_BATT_ID_5_LSB,
788 .status = RR_ADC_BATT_ID_STS,
790 .trigger_addr = RR_ADC_BATT_ID_TRIGGER,
791 .trigger_mask = BIT(0),
794 .lsb = RR_ADC_BATT_THERM_LSB,
795 .status = RR_ADC_BATT_THERM_STS,
797 .trigger_addr = RR_ADC_BATT_THERM_TRIGGER,
799 .label = "pmi8998_skin",
800 .lsb = RR_ADC_SKIN_TEMP_LSB,
801 .status = RR_ADC_AUX_THERM_STS,
803 .trigger_addr = RR_ADC_AUX_THERM_TRIGGER,
806 .lsb = RR_ADC_USB_IN_I_LSB,
807 .status = RR_ADC_USB_IN_I_STS,
809 .trigger_addr = RR_ADC_USB_IN_I_TRIGGER,
812 .lsb = RR_ADC_USB_IN_V_LSB,
813 .status = RR_ADC_USB_IN_V_STS,
815 .trigger_addr = RR_ADC_USB_IN_V_TRIGGER,
816 .trigger_mask = BIT(7),
819 .lsb = RR_ADC_DC_IN_I_LSB,
820 .status = RR_ADC_DC_IN_I_STS,
822 .trigger_addr = RR_ADC_DC_IN_I_TRIGGER,
825 .lsb = RR_ADC_DC_IN_V_LSB,
826 .status = RR_ADC_DC_IN_V_STS,
828 .trigger_addr = RR_ADC_DC_IN_V_TRIGGER,
830 .label = "pmi8998_die",
831 .lsb = RR_ADC_PMI_DIE_TEMP_LSB,
832 .status = RR_ADC_PMI_DIE_TEMP_STS,
834 .trigger_addr = RR_ADC_PMI_DIE_TEMP_TRIGGER,
835 .trigger_mask = RR_ADC_TRIGGER_EVERY_CYCLE,
838 .lsb = RR_ADC_CHARGER_TEMP_LSB,
839 .status = RR_ADC_CHARGER_TEMP_STS,
841 .trigger_addr = RR_ADC_CHARGER_TEMP_TRIGGER,
844 .lsb = RR_ADC_GPIO_LSB,
845 .status = RR_ADC_GPIO_STS,
847 .trigger_addr = RR_ADC_GPIO_TRIGGER,
851 static const struct iio_chan_spec rradc_iio_chans[RR_ADC_CHAN_MAX] = {
853 .type = IIO_RESISTANCE,
854 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
855 .address = RR_ADC_BATT_ID,
860 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
861 .address = RR_ADC_BATT_THERM,
866 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
867 BIT(IIO_CHAN_INFO_SCALE) |
868 BIT(IIO_CHAN_INFO_OFFSET),
869 .address = RR_ADC_SKIN_TEMP,
874 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
875 BIT(IIO_CHAN_INFO_SCALE),
876 .address = RR_ADC_USBIN_I,
881 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
882 BIT(IIO_CHAN_INFO_SCALE),
883 .address = RR_ADC_USBIN_V,
888 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
889 BIT(IIO_CHAN_INFO_SCALE),
890 .address = RR_ADC_DCIN_I,
895 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
896 BIT(IIO_CHAN_INFO_SCALE),
897 .address = RR_ADC_DCIN_V,
902 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
903 BIT(IIO_CHAN_INFO_SCALE) |
904 BIT(IIO_CHAN_INFO_OFFSET),
905 .address = RR_ADC_DIE_TEMP,
910 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
911 BIT(IIO_CHAN_INFO_OFFSET) |
912 BIT(IIO_CHAN_INFO_SCALE),
913 .address = RR_ADC_CHG_TEMP,
918 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
919 BIT(IIO_CHAN_INFO_SCALE),
920 .address = RR_ADC_GPIO,
926 static int rradc_probe(struct platform_device *pdev)
928 struct device *dev = &pdev->dev;
929 struct iio_dev *indio_dev;
930 struct rradc_chip *chip;
931 int ret, i, batt_id_delay;
933 indio_dev = devm_iio_device_alloc(dev, sizeof(*chip));
937 chip = iio_priv(indio_dev);
938 chip->regmap = dev_get_regmap(pdev->dev.parent, NULL);
940 dev_err(dev, "Couldn't get parent's regmap\n");
945 mutex_init(&chip->conversion_lock);
947 ret = device_property_read_u32(dev, "reg", &chip->base);
949 dev_err(chip->dev, "Couldn't find reg address, ret = %d\n",
955 ret = device_property_read_u32(dev, "qcom,batt-id-delay-ms",
958 for (i = 0; i < RRADC_BATT_ID_DELAY_MAX; i++) {
959 if (batt_id_delay == batt_id_delays[i])
962 if (i == RRADC_BATT_ID_DELAY_MAX)
966 if (batt_id_delay >= 0) {
967 batt_id_delay = FIELD_PREP(BATT_ID_SETTLE_MASK, batt_id_delay);
968 ret = regmap_update_bits(chip->regmap,
969 chip->base + RR_ADC_BATT_ID_CFG,
970 batt_id_delay, batt_id_delay);
973 "BATT_ID settling time config failed:%d\n",
978 /* Get the PMIC revision, we need it to handle some varying coefficients */
979 chip->pmic = qcom_pmic_get(chip->dev);
980 if (IS_ERR(chip->pmic)) {
981 dev_err(chip->dev, "Unable to get reference to PMIC device\n");
982 return PTR_ERR(chip->pmic);
985 switch (chip->pmic->subtype) {
986 case PMI8998_SUBTYPE:
987 indio_dev->name = "pmi8998-rradc";
990 indio_dev->name = "pm660-rradc";
993 indio_dev->name = DRIVER_NAME;
996 indio_dev->modes = INDIO_DIRECT_MODE;
997 indio_dev->info = &rradc_info;
998 indio_dev->channels = rradc_iio_chans;
999 indio_dev->num_channels = ARRAY_SIZE(rradc_iio_chans);
1001 return devm_iio_device_register(dev, indio_dev);
1004 static const struct of_device_id rradc_match_table[] = {
1005 { .compatible = "qcom,pm660-rradc" },
1006 { .compatible = "qcom,pmi8998-rradc" },
1009 MODULE_DEVICE_TABLE(of, rradc_match_table);
1011 static struct platform_driver rradc_driver = {
1013 .name = DRIVER_NAME,
1014 .of_match_table = rradc_match_table,
1016 .probe = rradc_probe,
1018 module_platform_driver(rradc_driver);
1020 MODULE_DESCRIPTION("QCOM SPMI PMIC RR ADC driver");
1021 MODULE_AUTHOR("Caleb Connolly <caleb.connolly@linaro.org>");
1022 MODULE_LICENSE("GPL");