drivers/iio/adc/palmas_gpadc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * palmas-adc.c -- TI PALMAS GPADC.
   4  *
   5  * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
   6  *
   7  * Author: Pradeep Goudagunta <pgoudagunta@nvidia.com>
   8  */
   9
  10 #include <linux/module.h>
  11 #include <linux/err.h>
  12 #include <linux/irq.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16 #include <linux/delay.h>
  17 #include <linux/i2c.h>
  18 #include <linux/pm.h>
  19 #include <linux/mfd/palmas.h>
  20 #include <linux/completion.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/iio/iio.h>
  24 #include <linux/iio/machine.h>
  25 #include <linux/iio/driver.h>
  26
  27 #define MOD_NAME "palmas-gpadc"
  28 #define PALMAS_ADC_CONVERSION_TIMEOUT   (msecs_to_jiffies(5000))
  29 #define PALMAS_TO_BE_CALCULATED 0
  30 #define PALMAS_GPADC_TRIMINVALID        -1
  31
  32 struct palmas_gpadc_info {
  33 /* calibration codes and regs */
  34         int x1; /* lower ideal code */
  35         int x2; /* higher ideal code */
  36         int v1; /* expected lower volt reading */
  37         int v2; /* expected higher volt reading */
  38         u8 trim1_reg;   /* register number for lower trim */
  39         u8 trim2_reg;   /* register number for upper trim */
  40         int gain;       /* calculated from above (after reading trim regs) */
  41         int offset;     /* calculated from above (after reading trim regs) */
  42         int gain_error; /* calculated from above (after reading trim regs) */
  43         bool is_uncalibrated;   /* if channel has calibration data */
  44 };
  45
  46 #define PALMAS_ADC_INFO(_chan, _x1, _x2, _v1, _v2, _t1, _t2, _is_uncalibrated) \
  47         [PALMAS_ADC_CH_##_chan] = { \
  48                 .x1 = _x1, \
  49                 .x2 = _x2, \
  50                 .v1 = _v1, \
  51                 .v2 = _v2, \
  52                 .gain = PALMAS_TO_BE_CALCULATED, \
  53                 .offset = PALMAS_TO_BE_CALCULATED, \
  54                 .gain_error = PALMAS_TO_BE_CALCULATED, \
  55                 .trim1_reg = PALMAS_GPADC_TRIM##_t1, \
  56                 .trim2_reg = PALMAS_GPADC_TRIM##_t2,  \
  57                 .is_uncalibrated = _is_uncalibrated \
  58         }
  59
  60 static struct palmas_gpadc_info palmas_gpadc_info[] = {
  61         PALMAS_ADC_INFO(IN0, 2064, 3112, 630, 950, 1, 2, false),
  62         PALMAS_ADC_INFO(IN1, 2064, 3112, 630, 950, 1, 2, false),
  63         PALMAS_ADC_INFO(IN2, 2064, 3112, 1260, 1900, 3, 4, false),
  64         PALMAS_ADC_INFO(IN3, 2064, 3112, 630, 950, 1, 2, false),
  65         PALMAS_ADC_INFO(IN4, 2064, 3112, 630, 950, 1, 2, false),
  66         PALMAS_ADC_INFO(IN5, 2064, 3112, 630, 950, 1, 2, false),
  67         PALMAS_ADC_INFO(IN6, 2064, 3112, 2520, 3800, 5, 6, false),
  68         PALMAS_ADC_INFO(IN7, 2064, 3112, 2520, 3800, 7, 8, false),
  69         PALMAS_ADC_INFO(IN8, 2064, 3112, 3150, 4750, 9, 10, false),
  70         PALMAS_ADC_INFO(IN9, 2064, 3112, 5670, 8550, 11, 12, false),
  71         PALMAS_ADC_INFO(IN10, 2064, 3112, 3465, 5225, 13, 14, false),
  72         PALMAS_ADC_INFO(IN11, 0, 0, 0, 0, INVALID, INVALID, true),
  73         PALMAS_ADC_INFO(IN12, 0, 0, 0, 0, INVALID, INVALID, true),
  74         PALMAS_ADC_INFO(IN13, 0, 0, 0, 0, INVALID, INVALID, true),
  75         PALMAS_ADC_INFO(IN14, 2064, 3112, 3645, 5225, 15, 16, false),
  76         PALMAS_ADC_INFO(IN15, 0, 0, 0, 0, INVALID, INVALID, true),
  77 };
  78
  79 /*
  80  * struct palmas_gpadc - the palmas_gpadc structure
  81  * @ch0_current:        channel 0 current source setting
  82  *                      0: 0 uA
  83  *                      1: 5 uA
  84  *                      2: 15 uA
  85  *                      3: 20 uA
  86  * @ch3_current:        channel 0 current source setting
  87  *                      0: 0 uA
  88  *                      1: 10 uA
  89  *                      2: 400 uA
  90  *                      3: 800 uA
  91  * @extended_delay:     enable the gpadc extended delay mode
  92  * @auto_conversion_period:     define the auto_conversion_period
  93  *
  94  * This is the palmas_gpadc structure to store run-time information
  95  * and pointers for this driver instance.
  96  */
  97 struct palmas_gpadc {
  98         struct device                   *dev;
  99         struct palmas                   *palmas;
 100         u8                              ch0_current;
 101         u8                              ch3_current;
 102         bool                            extended_delay;
 103         int                             irq;
 104         int                             irq_auto_0;
 105         int                             irq_auto_1;
 106         struct palmas_gpadc_info        *adc_info;
 107         struct completion               conv_completion;
 108         struct palmas_adc_wakeup_property wakeup1_data;
 109         struct palmas_adc_wakeup_property wakeup2_data;
 110         bool                            wakeup1_enable;
 111         bool                            wakeup2_enable;
 112         int                             auto_conversion_period;
 113 };
 114
 115 /*
 116  * GPADC lock issue in AUTO mode.
 117  * Impact: In AUTO mode, GPADC conversion can be locked after disabling AUTO
 118  *         mode feature.
 119  * Details:
 120  *      When the AUTO mode is the only conversion mode enabled, if the AUTO
 121  *      mode feature is disabled with bit GPADC_AUTO_CTRL.  AUTO_CONV1_EN = 0
 122  *      or bit GPADC_AUTO_CTRL.  AUTO_CONV0_EN = 0 during a conversion, the
 123  *      conversion mechanism can be seen as locked meaning that all following
 124  *      conversion will give 0 as a result.  Bit GPADC_STATUS.GPADC_AVAILABLE
 125  *      will stay at 0 meaning that GPADC is busy.  An RT conversion can unlock
 126  *      the GPADC.
 127  *
 128  * Workaround(s):
 129  *      To avoid the lock mechanism, the workaround to follow before any stop
 130  *      conversion request is:
 131  *      Force the GPADC state machine to be ON by using the GPADC_CTRL1.
 132  *              GPADC_FORCE bit = 1
 133  *      Shutdown the GPADC AUTO conversion using
 134  *              GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0.
 135  *      After 100us, force the GPADC state machine to be OFF by using the
 136  *              GPADC_CTRL1.  GPADC_FORCE bit = 0
 137  */
 138
 139 static int palmas_disable_auto_conversion(struct palmas_gpadc *adc)
 140 {
 141         int ret;
 142
 143         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 144                         PALMAS_GPADC_CTRL1,
 145                         PALMAS_GPADC_CTRL1_GPADC_FORCE,
 146                         PALMAS_GPADC_CTRL1_GPADC_FORCE);
 147         if (ret < 0) {
 148                 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
 149                 return ret;
 150         }
 151
 152         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 153                         PALMAS_GPADC_AUTO_CTRL,
 154                         PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 |
 155                         PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0,
 156                         0);
 157         if (ret < 0) {
 158                 dev_err(adc->dev, "AUTO_CTRL update failed: %d\n", ret);
 159                 return ret;
 160         }
 161
 162         udelay(100);
 163
 164         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 165                         PALMAS_GPADC_CTRL1,
 166                         PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
 167         if (ret < 0)
 168                 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
 169
 170         return ret;
 171 }
 172
 173 static irqreturn_t palmas_gpadc_irq(int irq, void *data)
 174 {
 175         struct palmas_gpadc *adc = data;
 176
 177         complete(&adc->conv_completion);
 178
 179         return IRQ_HANDLED;
 180 }
 181
 182 static irqreturn_t palmas_gpadc_irq_auto(int irq, void *data)
 183 {
 184         struct palmas_gpadc *adc = data;
 185
 186         dev_dbg(adc->dev, "Threshold interrupt %d occurs\n", irq);
 187         palmas_disable_auto_conversion(adc);
 188
 189         return IRQ_HANDLED;
 190 }
 191
 192 static int palmas_gpadc_start_mask_interrupt(struct palmas_gpadc *adc,
 193                                                 bool mask)
 194 {
 195         int ret;
 196
 197         if (!mask)
 198                 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
 199                                         PALMAS_INT3_MASK,
 200                                         PALMAS_INT3_MASK_GPADC_EOC_SW, 0);
 201         else
 202                 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
 203                                         PALMAS_INT3_MASK,
 204                                         PALMAS_INT3_MASK_GPADC_EOC_SW,
 205                                         PALMAS_INT3_MASK_GPADC_EOC_SW);
 206         if (ret < 0)
 207                 dev_err(adc->dev, "GPADC INT MASK update failed: %d\n", ret);
 208
 209         return ret;
 210 }
 211
 212 static int palmas_gpadc_enable(struct palmas_gpadc *adc, int adc_chan,
 213                                int enable)
 214 {
 215         unsigned int mask, val;
 216         int ret;
 217
 218         if (enable) {
 219                 val = (adc->extended_delay
 220                         << PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT);
 221                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 222                                         PALMAS_GPADC_RT_CTRL,
 223                                         PALMAS_GPADC_RT_CTRL_EXTEND_DELAY, val);
 224                 if (ret < 0) {
 225                         dev_err(adc->dev, "RT_CTRL update failed: %d\n", ret);
 226                         return ret;
 227                 }
 228
 229                 mask = (PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK |
 230                         PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK |
 231                         PALMAS_GPADC_CTRL1_GPADC_FORCE);
 232                 val = (adc->ch0_current
 233                         << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT);
 234                 val |= (adc->ch3_current
 235                         << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT);
 236                 val |= PALMAS_GPADC_CTRL1_GPADC_FORCE;
 237                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 238                                 PALMAS_GPADC_CTRL1, mask, val);
 239                 if (ret < 0) {
 240                         dev_err(adc->dev,
 241                                 "Failed to update current setting: %d\n", ret);
 242                         return ret;
 243                 }
 244
 245                 mask = (PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK |
 246                         PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
 247                 val = (adc_chan | PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
 248                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 249                                 PALMAS_GPADC_SW_SELECT, mask, val);
 250                 if (ret < 0) {
 251                         dev_err(adc->dev, "SW_SELECT update failed: %d\n", ret);
 252                         return ret;
 253                 }
 254         } else {
 255                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 256                                 PALMAS_GPADC_SW_SELECT, 0);
 257                 if (ret < 0)
 258                         dev_err(adc->dev, "SW_SELECT write failed: %d\n", ret);
 259
 260                 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 261                                 PALMAS_GPADC_CTRL1,
 262                                 PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
 263                 if (ret < 0) {
 264                         dev_err(adc->dev, "CTRL1 update failed: %d\n", ret);
 265                         return ret;
 266                 }
 267         }
 268
 269         return ret;
 270 }
 271
 272 static int palmas_gpadc_read_prepare(struct palmas_gpadc *adc, int adc_chan)
 273 {
 274         int ret;
 275
 276         ret = palmas_gpadc_enable(adc, adc_chan, true);
 277         if (ret < 0)
 278                 return ret;
 279
 280         return palmas_gpadc_start_mask_interrupt(adc, 0);
 281 }
 282
 283 static void palmas_gpadc_read_done(struct palmas_gpadc *adc, int adc_chan)
 284 {
 285         palmas_gpadc_start_mask_interrupt(adc, 1);
 286         palmas_gpadc_enable(adc, adc_chan, false);
 287 }
 288
 289 static int palmas_gpadc_calibrate(struct palmas_gpadc *adc, int adc_chan)
 290 {
 291         int k;
 292         int d1;
 293         int d2;
 294         int ret;
 295         int gain;
 296         int x1 =  adc->adc_info[adc_chan].x1;
 297         int x2 =  adc->adc_info[adc_chan].x2;
 298         int v1 = adc->adc_info[adc_chan].v1;
 299         int v2 = adc->adc_info[adc_chan].v2;
 300
 301         ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
 302                                 adc->adc_info[adc_chan].trim1_reg, &d1);
 303         if (ret < 0) {
 304                 dev_err(adc->dev, "TRIM read failed: %d\n", ret);
 305                 goto scrub;
 306         }
 307
 308         ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
 309                                 adc->adc_info[adc_chan].trim2_reg, &d2);
 310         if (ret < 0) {
 311                 dev_err(adc->dev, "TRIM read failed: %d\n", ret);
 312                 goto scrub;
 313         }
 314
 315         /* gain error calculation */
 316         k = (1000 + (1000 * (d2 - d1)) / (x2 - x1));
 317
 318         /* gain calculation */
 319         gain = ((v2 - v1) * 1000) / (x2 - x1);
 320
 321         adc->adc_info[adc_chan].gain_error = k;
 322         adc->adc_info[adc_chan].gain = gain;
 323         /* offset Calculation */
 324         adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1);
 325
 326 scrub:
 327         return ret;
 328 }
 329
 330 static int palmas_gpadc_start_conversion(struct palmas_gpadc *adc, int adc_chan)
 331 {
 332         unsigned int val;
 333         int ret;
 334
 335         init_completion(&adc->conv_completion);
 336         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 337                                 PALMAS_GPADC_SW_SELECT,
 338                                 PALMAS_GPADC_SW_SELECT_SW_START_CONV0,
 339                                 PALMAS_GPADC_SW_SELECT_SW_START_CONV0);
 340         if (ret < 0) {
 341                 dev_err(adc->dev, "SELECT_SW_START write failed: %d\n", ret);
 342                 return ret;
 343         }
 344
 345         ret = wait_for_completion_timeout(&adc->conv_completion,
 346                                 PALMAS_ADC_CONVERSION_TIMEOUT);
 347         if (ret == 0) {
 348                 dev_err(adc->dev, "conversion not completed\n");
 349                 return -ETIMEDOUT;
 350         }
 351
 352         ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE,
 353                                 PALMAS_GPADC_SW_CONV0_LSB, &val, 2);
 354         if (ret < 0) {
 355                 dev_err(adc->dev, "SW_CONV0_LSB read failed: %d\n", ret);
 356                 return ret;
 357         }
 358
 359         ret = val & 0xFFF;
 360
 361         return ret;
 362 }
 363
 364 static int palmas_gpadc_get_calibrated_code(struct palmas_gpadc *adc,
 365                                                 int adc_chan, int val)
 366 {
 367         if (!adc->adc_info[adc_chan].is_uncalibrated)
 368                 val  = (val*1000 - adc->adc_info[adc_chan].offset) /
 369                                         adc->adc_info[adc_chan].gain_error;
 370
 371         if (val < 0) {
 372                 dev_err(adc->dev, "Mismatch with calibration\n");
 373                 return 0;
 374         }
 375
 376         val = (val * adc->adc_info[adc_chan].gain) / 1000;
 377
 378         return val;
 379 }
 380
 381 static int palmas_gpadc_read_raw(struct iio_dev *indio_dev,
 382         struct iio_chan_spec const *chan, int *val, int *val2, long mask)
 383 {
 384         struct  palmas_gpadc *adc = iio_priv(indio_dev);
 385         int adc_chan = chan->channel;
 386         int ret = 0;
 387
 388         if (adc_chan > PALMAS_ADC_CH_MAX)
 389                 return -EINVAL;
 390
 391         mutex_lock(&indio_dev->mlock);
 392
 393         switch (mask) {
 394         case IIO_CHAN_INFO_RAW:
 395         case IIO_CHAN_INFO_PROCESSED:
 396                 ret = palmas_gpadc_read_prepare(adc, adc_chan);
 397                 if (ret < 0)
 398                         goto out;
 399
 400                 ret = palmas_gpadc_start_conversion(adc, adc_chan);
 401                 if (ret < 0) {
 402                         dev_err(adc->dev,
 403                         "ADC start conversion failed\n");
 404                         goto out;
 405                 }
 406
 407                 if (mask == IIO_CHAN_INFO_PROCESSED)
 408                         ret = palmas_gpadc_get_calibrated_code(
 409                                                         adc, adc_chan, ret);
 410
 411                 *val = ret;
 412
 413                 ret = IIO_VAL_INT;
 414                 goto out;
 415         }
 416
 417         mutex_unlock(&indio_dev->mlock);
 418         return ret;
 419
 420 out:
 421         palmas_gpadc_read_done(adc, adc_chan);
 422         mutex_unlock(&indio_dev->mlock);
 423
 424         return ret;
 425 }
 426
 427 static const struct iio_info palmas_gpadc_iio_info = {
 428         .read_raw = palmas_gpadc_read_raw,
 429 };
 430
 431 #define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info)     \
 432 {                                                       \
 433         .datasheet_name = PALMAS_DATASHEET_NAME(chan),  \
 434         .type = _type,                                  \
 435         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |  \
 436                         BIT(chan_info),                 \
 437         .indexed = 1,                                   \
 438         .channel = PALMAS_ADC_CH_##chan,                \
 439 }
 440
 441 static const struct iio_chan_spec palmas_gpadc_iio_channel[] = {
 442         PALMAS_ADC_CHAN_IIO(IN0, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 443         PALMAS_ADC_CHAN_IIO(IN1, IIO_TEMP, IIO_CHAN_INFO_RAW),
 444         PALMAS_ADC_CHAN_IIO(IN2, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 445         PALMAS_ADC_CHAN_IIO(IN3, IIO_TEMP, IIO_CHAN_INFO_RAW),
 446         PALMAS_ADC_CHAN_IIO(IN4, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 447         PALMAS_ADC_CHAN_IIO(IN5, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 448         PALMAS_ADC_CHAN_IIO(IN6, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 449         PALMAS_ADC_CHAN_IIO(IN7, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 450         PALMAS_ADC_CHAN_IIO(IN8, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 451         PALMAS_ADC_CHAN_IIO(IN9, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 452         PALMAS_ADC_CHAN_IIO(IN10, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 453         PALMAS_ADC_CHAN_IIO(IN11, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 454         PALMAS_ADC_CHAN_IIO(IN12, IIO_TEMP, IIO_CHAN_INFO_RAW),
 455         PALMAS_ADC_CHAN_IIO(IN13, IIO_TEMP, IIO_CHAN_INFO_RAW),
 456         PALMAS_ADC_CHAN_IIO(IN14, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 457         PALMAS_ADC_CHAN_IIO(IN15, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
 458 };
 459
 460 static int palmas_gpadc_get_adc_dt_data(struct platform_device *pdev,
 461         struct palmas_gpadc_platform_data **gpadc_pdata)
 462 {
 463         struct device_node *np = pdev->dev.of_node;
 464         struct palmas_gpadc_platform_data *gp_data;
 465         int ret;
 466         u32 pval;
 467
 468         gp_data = devm_kzalloc(&pdev->dev, sizeof(*gp_data), GFP_KERNEL);
 469         if (!gp_data)
 470                 return -ENOMEM;
 471
 472         ret = of_property_read_u32(np, "ti,channel0-current-microamp", &pval);
 473         if (!ret)
 474                 gp_data->ch0_current = pval;
 475
 476         ret = of_property_read_u32(np, "ti,channel3-current-microamp", &pval);
 477         if (!ret)
 478                 gp_data->ch3_current = pval;
 479
 480         gp_data->extended_delay = of_property_read_bool(np,
 481                                         "ti,enable-extended-delay");
 482
 483         *gpadc_pdata = gp_data;
 484
 485         return 0;
 486 }
 487
 488 static int palmas_gpadc_probe(struct platform_device *pdev)
 489 {
 490         struct palmas_gpadc *adc;
 491         struct palmas_platform_data *pdata;
 492         struct palmas_gpadc_platform_data *gpadc_pdata = NULL;
 493         struct iio_dev *indio_dev;
 494         int ret, i;
 495
 496         pdata = dev_get_platdata(pdev->dev.parent);
 497
 498         if (pdata && pdata->gpadc_pdata)
 499                 gpadc_pdata = pdata->gpadc_pdata;
 500
 501         if (!gpadc_pdata && pdev->dev.of_node) {
 502                 ret = palmas_gpadc_get_adc_dt_data(pdev, &gpadc_pdata);
 503                 if (ret < 0)
 504                         return ret;
 505         }
 506         if (!gpadc_pdata)
 507                 return -EINVAL;
 508
 509         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
 510         if (!indio_dev) {
 511                 dev_err(&pdev->dev, "iio_device_alloc failed\n");
 512                 return -ENOMEM;
 513         }
 514
 515         adc = iio_priv(indio_dev);
 516         adc->dev = &pdev->dev;
 517         adc->palmas = dev_get_drvdata(pdev->dev.parent);
 518         adc->adc_info = palmas_gpadc_info;
 519         init_completion(&adc->conv_completion);
 520         dev_set_drvdata(&pdev->dev, indio_dev);
 521
 522         adc->auto_conversion_period = gpadc_pdata->auto_conversion_period_ms;
 523         adc->irq = palmas_irq_get_virq(adc->palmas, PALMAS_GPADC_EOC_SW_IRQ);
 524         if (adc->irq < 0) {
 525                 dev_err(adc->dev,
 526                         "get virq failed: %d\n", adc->irq);
 527                 ret = adc->irq;
 528                 goto out;
 529         }
 530         ret = request_threaded_irq(adc->irq, NULL,
 531                 palmas_gpadc_irq,
 532                 IRQF_ONESHOT, dev_name(adc->dev),
 533                 adc);
 534         if (ret < 0) {
 535                 dev_err(adc->dev,
 536                         "request irq %d failed: %d\n", adc->irq, ret);
 537                 goto out;
 538         }
 539
 540         if (gpadc_pdata->adc_wakeup1_data) {
 541                 memcpy(&adc->wakeup1_data, gpadc_pdata->adc_wakeup1_data,
 542                         sizeof(adc->wakeup1_data));
 543                 adc->wakeup1_enable = true;
 544                 adc->irq_auto_0 =  platform_get_irq(pdev, 1);
 545                 ret = request_threaded_irq(adc->irq_auto_0, NULL,
 546                                 palmas_gpadc_irq_auto,
 547                                 IRQF_ONESHOT,
 548                                 "palmas-adc-auto-0", adc);
 549                 if (ret < 0) {
 550                         dev_err(adc->dev, "request auto0 irq %d failed: %d\n",
 551                                 adc->irq_auto_0, ret);
 552                         goto out_irq_free;
 553                 }
 554         }
 555
 556         if (gpadc_pdata->adc_wakeup2_data) {
 557                 memcpy(&adc->wakeup2_data, gpadc_pdata->adc_wakeup2_data,
 558                                 sizeof(adc->wakeup2_data));
 559                 adc->wakeup2_enable = true;
 560                 adc->irq_auto_1 =  platform_get_irq(pdev, 2);
 561                 ret = request_threaded_irq(adc->irq_auto_1, NULL,
 562                                 palmas_gpadc_irq_auto,
 563                                 IRQF_ONESHOT,
 564                                 "palmas-adc-auto-1", adc);
 565                 if (ret < 0) {
 566                         dev_err(adc->dev, "request auto1 irq %d failed: %d\n",
 567                                 adc->irq_auto_1, ret);
 568                         goto out_irq_auto0_free;
 569                 }
 570         }
 571
 572         /* set the current source 0 (value 0/5/15/20 uA => 0..3) */
 573         if (gpadc_pdata->ch0_current <= 1)
 574                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_0;
 575         else if (gpadc_pdata->ch0_current <= 5)
 576                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_5;
 577         else if (gpadc_pdata->ch0_current <= 15)
 578                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_15;
 579         else
 580                 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_20;
 581
 582         /* set the current source 3 (value 0/10/400/800 uA => 0..3) */
 583         if (gpadc_pdata->ch3_current <= 1)
 584                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_0;
 585         else if (gpadc_pdata->ch3_current <= 10)
 586                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_10;
 587         else if (gpadc_pdata->ch3_current <= 400)
 588                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_400;
 589         else
 590                 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_800;
 591
 592         adc->extended_delay = gpadc_pdata->extended_delay;
 593
 594         indio_dev->name = MOD_NAME;
 595         indio_dev->info = &palmas_gpadc_iio_info;
 596         indio_dev->modes = INDIO_DIRECT_MODE;
 597         indio_dev->channels = palmas_gpadc_iio_channel;
 598         indio_dev->num_channels = ARRAY_SIZE(palmas_gpadc_iio_channel);
 599
 600         ret = iio_device_register(indio_dev);
 601         if (ret < 0) {
 602                 dev_err(adc->dev, "iio_device_register() failed: %d\n", ret);
 603                 goto out_irq_auto1_free;
 604         }
 605
 606         device_set_wakeup_capable(&pdev->dev, 1);
 607         for (i = 0; i < PALMAS_ADC_CH_MAX; i++) {
 608                 if (!(adc->adc_info[i].is_uncalibrated))
 609                         palmas_gpadc_calibrate(adc, i);
 610         }
 611
 612         if (adc->wakeup1_enable || adc->wakeup2_enable)
 613                 device_wakeup_enable(&pdev->dev);
 614
 615         return 0;
 616
 617 out_irq_auto1_free:
 618         if (gpadc_pdata->adc_wakeup2_data)
 619                 free_irq(adc->irq_auto_1, adc);
 620 out_irq_auto0_free:
 621         if (gpadc_pdata->adc_wakeup1_data)
 622                 free_irq(adc->irq_auto_0, adc);
 623 out_irq_free:
 624         free_irq(adc->irq, adc);
 625 out:
 626         return ret;
 627 }
 628
 629 static int palmas_gpadc_remove(struct platform_device *pdev)
 630 {
 631         struct iio_dev *indio_dev = dev_to_iio_dev(&pdev->dev);
 632         struct palmas_gpadc *adc = iio_priv(indio_dev);
 633
 634         if (adc->wakeup1_enable || adc->wakeup2_enable)
 635                 device_wakeup_disable(&pdev->dev);
 636         iio_device_unregister(indio_dev);
 637         free_irq(adc->irq, adc);
 638         if (adc->wakeup1_enable)
 639                 free_irq(adc->irq_auto_0, adc);
 640         if (adc->wakeup2_enable)
 641                 free_irq(adc->irq_auto_1, adc);
 642
 643         return 0;
 644 }
 645
 646 #ifdef CONFIG_PM_SLEEP
 647 static int palmas_adc_wakeup_configure(struct palmas_gpadc *adc)
 648 {
 649         int adc_period, conv;
 650         int i;
 651         int ch0 = 0, ch1 = 0;
 652         int thres;
 653         int ret;
 654
 655         adc_period = adc->auto_conversion_period;
 656         for (i = 0; i < 16; ++i) {
 657                 if (((1000 * (1 << i)) / 32) < adc_period)
 658                         continue;
 659         }
 660         if (i > 0)
 661                 i--;
 662         adc_period = i;
 663         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 664                         PALMAS_GPADC_AUTO_CTRL,
 665                         PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK,
 666                         adc_period);
 667         if (ret < 0) {
 668                 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
 669                 return ret;
 670         }
 671
 672         conv = 0;
 673         if (adc->wakeup1_enable) {
 674                 int polarity;
 675
 676                 ch0 = adc->wakeup1_data.adc_channel_number;
 677                 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN;
 678                 if (adc->wakeup1_data.adc_high_threshold > 0) {
 679                         thres = adc->wakeup1_data.adc_high_threshold;
 680                         polarity = 0;
 681                 } else {
 682                         thres = adc->wakeup1_data.adc_low_threshold;
 683                         polarity = PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL;
 684                 }
 685
 686                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 687                                 PALMAS_GPADC_THRES_CONV0_LSB, thres & 0xFF);
 688                 if (ret < 0) {
 689                         dev_err(adc->dev,
 690                                 "THRES_CONV0_LSB write failed: %d\n", ret);
 691                         return ret;
 692                 }
 693
 694                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 695                                 PALMAS_GPADC_THRES_CONV0_MSB,
 696                                 ((thres >> 8) & 0xF) | polarity);
 697                 if (ret < 0) {
 698                         dev_err(adc->dev,
 699                                 "THRES_CONV0_MSB write failed: %d\n", ret);
 700                         return ret;
 701                 }
 702         }
 703
 704         if (adc->wakeup2_enable) {
 705                 int polarity;
 706
 707                 ch1 = adc->wakeup2_data.adc_channel_number;
 708                 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN;
 709                 if (adc->wakeup2_data.adc_high_threshold > 0) {
 710                         thres = adc->wakeup2_data.adc_high_threshold;
 711                         polarity = 0;
 712                 } else {
 713                         thres = adc->wakeup2_data.adc_low_threshold;
 714                         polarity = PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL;
 715                 }
 716
 717                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 718                                 PALMAS_GPADC_THRES_CONV1_LSB, thres & 0xFF);
 719                 if (ret < 0) {
 720                         dev_err(adc->dev,
 721                                 "THRES_CONV1_LSB write failed: %d\n", ret);
 722                         return ret;
 723                 }
 724
 725                 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 726                                 PALMAS_GPADC_THRES_CONV1_MSB,
 727                                 ((thres >> 8) & 0xF) | polarity);
 728                 if (ret < 0) {
 729                         dev_err(adc->dev,
 730                                 "THRES_CONV1_MSB write failed: %d\n", ret);
 731                         return ret;
 732                 }
 733         }
 734
 735         ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 736                         PALMAS_GPADC_AUTO_SELECT, (ch1 << 4) | ch0);
 737         if (ret < 0) {
 738                 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
 739                 return ret;
 740         }
 741
 742         ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
 743                         PALMAS_GPADC_AUTO_CTRL,
 744                         PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN |
 745                         PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN, conv);
 746         if (ret < 0)
 747                 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
 748
 749         return ret;
 750 }
 751
 752 static int palmas_adc_wakeup_reset(struct palmas_gpadc *adc)
 753 {
 754         int ret;
 755
 756         ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
 757                         PALMAS_GPADC_AUTO_SELECT, 0);
 758         if (ret < 0) {
 759                 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
 760                 return ret;
 761         }
 762
 763         ret = palmas_disable_auto_conversion(adc);
 764         if (ret < 0)
 765                 dev_err(adc->dev, "Disable auto conversion failed: %d\n", ret);
 766
 767         return ret;
 768 }
 769
 770 static int palmas_gpadc_suspend(struct device *dev)
 771 {
 772         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 773         struct palmas_gpadc *adc = iio_priv(indio_dev);
 774         int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
 775         int ret;
 776
 777         if (!device_may_wakeup(dev) || !wakeup)
 778                 return 0;
 779
 780         ret = palmas_adc_wakeup_configure(adc);
 781         if (ret < 0)
 782                 return ret;
 783
 784         if (adc->wakeup1_enable)
 785                 enable_irq_wake(adc->irq_auto_0);
 786
 787         if (adc->wakeup2_enable)
 788                 enable_irq_wake(adc->irq_auto_1);
 789
 790         return 0;
 791 }
 792
 793 static int palmas_gpadc_resume(struct device *dev)
 794 {
 795         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 796         struct palmas_gpadc *adc = iio_priv(indio_dev);
 797         int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
 798         int ret;
 799
 800         if (!device_may_wakeup(dev) || !wakeup)
 801                 return 0;
 802
 803         ret = palmas_adc_wakeup_reset(adc);
 804         if (ret < 0)
 805                 return ret;
 806
 807         if (adc->wakeup1_enable)
 808                 disable_irq_wake(adc->irq_auto_0);
 809
 810         if (adc->wakeup2_enable)
 811                 disable_irq_wake(adc->irq_auto_1);
 812
 813         return 0;
 814 };
 815 #endif
 816
 817 static const struct dev_pm_ops palmas_pm_ops = {
 818         SET_SYSTEM_SLEEP_PM_OPS(palmas_gpadc_suspend,
 819                                 palmas_gpadc_resume)
 820 };
 821
 822 static const struct of_device_id of_palmas_gpadc_match_tbl[] = {
 823         { .compatible = "ti,palmas-gpadc", },
 824         { /* end */ }
 825 };
 826 MODULE_DEVICE_TABLE(of, of_palmas_gpadc_match_tbl);
 827
 828 static struct platform_driver palmas_gpadc_driver = {
 829         .probe = palmas_gpadc_probe,
 830         .remove = palmas_gpadc_remove,
 831         .driver = {
 832                 .name = MOD_NAME,
 833                 .pm = &palmas_pm_ops,
 834                 .of_match_table = of_palmas_gpadc_match_tbl,
 835         },
 836 };
 837 module_platform_driver(palmas_gpadc_driver);
 838
 839 MODULE_DESCRIPTION("palmas GPADC driver");
 840 MODULE_AUTHOR("Pradeep Goudagunta<pgoudagunta@nvidia.com>");
 841 MODULE_ALIAS("platform:palmas-gpadc");
 842 MODULE_LICENSE("GPL v2");