1 // SPDX-License-Identifier: GPL-2.0-only
3 * palmas-adc.c -- TI PALMAS GPADC.
5 * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
7 * Author: Pradeep Goudagunta <pgoudagunta@nvidia.com>
10 #include <linux/module.h>
11 #include <linux/err.h>
12 #include <linux/irq.h>
13 #include <linux/interrupt.h>
14 #include <linux/platform_device.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
17 #include <linux/i2c.h>
19 #include <linux/mfd/palmas.h>
20 #include <linux/completion.h>
22 #include <linux/of_device.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/machine.h>
25 #include <linux/iio/driver.h>
27 #define MOD_NAME "palmas-gpadc"
28 #define PALMAS_ADC_CONVERSION_TIMEOUT (msecs_to_jiffies(5000))
29 #define PALMAS_TO_BE_CALCULATED 0
30 #define PALMAS_GPADC_TRIMINVALID -1
32 struct palmas_gpadc_info {
33 /* calibration codes and regs */
34 int x1; /* lower ideal code */
35 int x2; /* higher ideal code */
36 int v1; /* expected lower volt reading */
37 int v2; /* expected higher volt reading */
38 u8 trim1_reg; /* register number for lower trim */
39 u8 trim2_reg; /* register number for upper trim */
40 int gain; /* calculated from above (after reading trim regs) */
41 int offset; /* calculated from above (after reading trim regs) */
42 int gain_error; /* calculated from above (after reading trim regs) */
43 bool is_uncalibrated; /* if channel has calibration data */
46 #define PALMAS_ADC_INFO(_chan, _x1, _x2, _v1, _v2, _t1, _t2, _is_uncalibrated) \
47 [PALMAS_ADC_CH_##_chan] = { \
52 .gain = PALMAS_TO_BE_CALCULATED, \
53 .offset = PALMAS_TO_BE_CALCULATED, \
54 .gain_error = PALMAS_TO_BE_CALCULATED, \
55 .trim1_reg = PALMAS_GPADC_TRIM##_t1, \
56 .trim2_reg = PALMAS_GPADC_TRIM##_t2, \
57 .is_uncalibrated = _is_uncalibrated \
60 static struct palmas_gpadc_info palmas_gpadc_info[] = {
61 PALMAS_ADC_INFO(IN0, 2064, 3112, 630, 950, 1, 2, false),
62 PALMAS_ADC_INFO(IN1, 2064, 3112, 630, 950, 1, 2, false),
63 PALMAS_ADC_INFO(IN2, 2064, 3112, 1260, 1900, 3, 4, false),
64 PALMAS_ADC_INFO(IN3, 2064, 3112, 630, 950, 1, 2, false),
65 PALMAS_ADC_INFO(IN4, 2064, 3112, 630, 950, 1, 2, false),
66 PALMAS_ADC_INFO(IN5, 2064, 3112, 630, 950, 1, 2, false),
67 PALMAS_ADC_INFO(IN6, 2064, 3112, 2520, 3800, 5, 6, false),
68 PALMAS_ADC_INFO(IN7, 2064, 3112, 2520, 3800, 7, 8, false),
69 PALMAS_ADC_INFO(IN8, 2064, 3112, 3150, 4750, 9, 10, false),
70 PALMAS_ADC_INFO(IN9, 2064, 3112, 5670, 8550, 11, 12, false),
71 PALMAS_ADC_INFO(IN10, 2064, 3112, 3465, 5225, 13, 14, false),
72 PALMAS_ADC_INFO(IN11, 0, 0, 0, 0, INVALID, INVALID, true),
73 PALMAS_ADC_INFO(IN12, 0, 0, 0, 0, INVALID, INVALID, true),
74 PALMAS_ADC_INFO(IN13, 0, 0, 0, 0, INVALID, INVALID, true),
75 PALMAS_ADC_INFO(IN14, 2064, 3112, 3645, 5225, 15, 16, false),
76 PALMAS_ADC_INFO(IN15, 0, 0, 0, 0, INVALID, INVALID, true),
80 * struct palmas_gpadc - the palmas_gpadc structure
81 * @ch0_current: channel 0 current source setting
86 * @ch3_current: channel 0 current source setting
91 * @extended_delay: enable the gpadc extended delay mode
92 * @auto_conversion_period: define the auto_conversion_period
93 * @lock: Lock to protect the device state during a potential concurrent
94 * read access from userspace. Reading a raw value requires a sequence
95 * of register writes, then a wait for a completion callback,
96 * and finally a register read, during which userspace could issue
97 * another read request. This lock protects a read access from
98 * ocurring before another one has finished.
100 * This is the palmas_gpadc structure to store run-time information
101 * and pointers for this driver instance.
103 struct palmas_gpadc {
105 struct palmas *palmas;
112 struct palmas_gpadc_info *adc_info;
113 struct completion conv_completion;
114 struct palmas_adc_wakeup_property wakeup1_data;
115 struct palmas_adc_wakeup_property wakeup2_data;
118 int auto_conversion_period;
123 * GPADC lock issue in AUTO mode.
124 * Impact: In AUTO mode, GPADC conversion can be locked after disabling AUTO
127 * When the AUTO mode is the only conversion mode enabled, if the AUTO
128 * mode feature is disabled with bit GPADC_AUTO_CTRL. AUTO_CONV1_EN = 0
129 * or bit GPADC_AUTO_CTRL. AUTO_CONV0_EN = 0 during a conversion, the
130 * conversion mechanism can be seen as locked meaning that all following
131 * conversion will give 0 as a result. Bit GPADC_STATUS.GPADC_AVAILABLE
132 * will stay at 0 meaning that GPADC is busy. An RT conversion can unlock
136 * To avoid the lock mechanism, the workaround to follow before any stop
137 * conversion request is:
138 * Force the GPADC state machine to be ON by using the GPADC_CTRL1.
139 * GPADC_FORCE bit = 1
140 * Shutdown the GPADC AUTO conversion using
141 * GPADC_AUTO_CTRL.SHUTDOWN_CONV[01] = 0.
142 * After 100us, force the GPADC state machine to be OFF by using the
143 * GPADC_CTRL1. GPADC_FORCE bit = 0
146 static int palmas_disable_auto_conversion(struct palmas_gpadc *adc)
150 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
152 PALMAS_GPADC_CTRL1_GPADC_FORCE,
153 PALMAS_GPADC_CTRL1_GPADC_FORCE);
155 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
159 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
160 PALMAS_GPADC_AUTO_CTRL,
161 PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 |
162 PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0,
165 dev_err(adc->dev, "AUTO_CTRL update failed: %d\n", ret);
171 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
173 PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
175 dev_err(adc->dev, "GPADC_CTRL1 update failed: %d\n", ret);
180 static irqreturn_t palmas_gpadc_irq(int irq, void *data)
182 struct palmas_gpadc *adc = data;
184 complete(&adc->conv_completion);
189 static irqreturn_t palmas_gpadc_irq_auto(int irq, void *data)
191 struct palmas_gpadc *adc = data;
193 dev_dbg(adc->dev, "Threshold interrupt %d occurs\n", irq);
194 palmas_disable_auto_conversion(adc);
199 static int palmas_gpadc_start_mask_interrupt(struct palmas_gpadc *adc,
205 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
207 PALMAS_INT3_MASK_GPADC_EOC_SW, 0);
209 ret = palmas_update_bits(adc->palmas, PALMAS_INTERRUPT_BASE,
211 PALMAS_INT3_MASK_GPADC_EOC_SW,
212 PALMAS_INT3_MASK_GPADC_EOC_SW);
214 dev_err(adc->dev, "GPADC INT MASK update failed: %d\n", ret);
219 static int palmas_gpadc_enable(struct palmas_gpadc *adc, int adc_chan,
222 unsigned int mask, val;
226 val = (adc->extended_delay
227 << PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT);
228 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
229 PALMAS_GPADC_RT_CTRL,
230 PALMAS_GPADC_RT_CTRL_EXTEND_DELAY, val);
232 dev_err(adc->dev, "RT_CTRL update failed: %d\n", ret);
236 mask = (PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK |
237 PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK |
238 PALMAS_GPADC_CTRL1_GPADC_FORCE);
239 val = (adc->ch0_current
240 << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT);
241 val |= (adc->ch3_current
242 << PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT);
243 val |= PALMAS_GPADC_CTRL1_GPADC_FORCE;
244 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
245 PALMAS_GPADC_CTRL1, mask, val);
248 "Failed to update current setting: %d\n", ret);
252 mask = (PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK |
253 PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
254 val = (adc_chan | PALMAS_GPADC_SW_SELECT_SW_CONV_EN);
255 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
256 PALMAS_GPADC_SW_SELECT, mask, val);
258 dev_err(adc->dev, "SW_SELECT update failed: %d\n", ret);
262 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
263 PALMAS_GPADC_SW_SELECT, 0);
265 dev_err(adc->dev, "SW_SELECT write failed: %d\n", ret);
267 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
269 PALMAS_GPADC_CTRL1_GPADC_FORCE, 0);
271 dev_err(adc->dev, "CTRL1 update failed: %d\n", ret);
279 static int palmas_gpadc_read_prepare(struct palmas_gpadc *adc, int adc_chan)
283 ret = palmas_gpadc_enable(adc, adc_chan, true);
287 return palmas_gpadc_start_mask_interrupt(adc, 0);
290 static void palmas_gpadc_read_done(struct palmas_gpadc *adc, int adc_chan)
292 palmas_gpadc_start_mask_interrupt(adc, 1);
293 palmas_gpadc_enable(adc, adc_chan, false);
296 static int palmas_gpadc_calibrate(struct palmas_gpadc *adc, int adc_chan)
303 int x1 = adc->adc_info[adc_chan].x1;
304 int x2 = adc->adc_info[adc_chan].x2;
305 int v1 = adc->adc_info[adc_chan].v1;
306 int v2 = adc->adc_info[adc_chan].v2;
308 ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
309 adc->adc_info[adc_chan].trim1_reg, &d1);
311 dev_err(adc->dev, "TRIM read failed: %d\n", ret);
315 ret = palmas_read(adc->palmas, PALMAS_TRIM_GPADC_BASE,
316 adc->adc_info[adc_chan].trim2_reg, &d2);
318 dev_err(adc->dev, "TRIM read failed: %d\n", ret);
322 /* gain error calculation */
323 k = (1000 + (1000 * (d2 - d1)) / (x2 - x1));
325 /* gain calculation */
326 gain = ((v2 - v1) * 1000) / (x2 - x1);
328 adc->adc_info[adc_chan].gain_error = k;
329 adc->adc_info[adc_chan].gain = gain;
330 /* offset Calculation */
331 adc->adc_info[adc_chan].offset = (d1 * 1000) - ((k - 1000) * x1);
337 static int palmas_gpadc_start_conversion(struct palmas_gpadc *adc, int adc_chan)
342 init_completion(&adc->conv_completion);
343 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
344 PALMAS_GPADC_SW_SELECT,
345 PALMAS_GPADC_SW_SELECT_SW_START_CONV0,
346 PALMAS_GPADC_SW_SELECT_SW_START_CONV0);
348 dev_err(adc->dev, "SELECT_SW_START write failed: %d\n", ret);
352 ret = wait_for_completion_timeout(&adc->conv_completion,
353 PALMAS_ADC_CONVERSION_TIMEOUT);
355 dev_err(adc->dev, "conversion not completed\n");
359 ret = palmas_bulk_read(adc->palmas, PALMAS_GPADC_BASE,
360 PALMAS_GPADC_SW_CONV0_LSB, &val, 2);
362 dev_err(adc->dev, "SW_CONV0_LSB read failed: %d\n", ret);
371 static int palmas_gpadc_get_calibrated_code(struct palmas_gpadc *adc,
372 int adc_chan, int val)
374 if (!adc->adc_info[adc_chan].is_uncalibrated)
375 val = (val*1000 - adc->adc_info[adc_chan].offset) /
376 adc->adc_info[adc_chan].gain_error;
380 dev_err(adc->dev, "Mismatch with calibration var = %d\n", val);
384 val = (val * adc->adc_info[adc_chan].gain) / 1000;
389 static int palmas_gpadc_read_raw(struct iio_dev *indio_dev,
390 struct iio_chan_spec const *chan, int *val, int *val2, long mask)
392 struct palmas_gpadc *adc = iio_priv(indio_dev);
393 int adc_chan = chan->channel;
396 if (adc_chan > PALMAS_ADC_CH_MAX)
399 mutex_lock(&adc->lock);
402 case IIO_CHAN_INFO_RAW:
403 case IIO_CHAN_INFO_PROCESSED:
404 ret = palmas_gpadc_read_prepare(adc, adc_chan);
408 ret = palmas_gpadc_start_conversion(adc, adc_chan);
411 "ADC start conversion failed\n");
415 if (mask == IIO_CHAN_INFO_PROCESSED)
416 ret = palmas_gpadc_get_calibrated_code(
425 mutex_unlock(&adc->lock);
429 palmas_gpadc_read_done(adc, adc_chan);
430 mutex_unlock(&adc->lock);
435 static const struct iio_info palmas_gpadc_iio_info = {
436 .read_raw = palmas_gpadc_read_raw,
439 #define PALMAS_ADC_CHAN_IIO(chan, _type, chan_info) \
441 .datasheet_name = PALMAS_DATASHEET_NAME(chan), \
443 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
446 .channel = PALMAS_ADC_CH_##chan, \
449 static const struct iio_chan_spec palmas_gpadc_iio_channel[] = {
450 PALMAS_ADC_CHAN_IIO(IN0, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
451 PALMAS_ADC_CHAN_IIO(IN1, IIO_TEMP, IIO_CHAN_INFO_RAW),
452 PALMAS_ADC_CHAN_IIO(IN2, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
453 PALMAS_ADC_CHAN_IIO(IN3, IIO_TEMP, IIO_CHAN_INFO_RAW),
454 PALMAS_ADC_CHAN_IIO(IN4, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
455 PALMAS_ADC_CHAN_IIO(IN5, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
456 PALMAS_ADC_CHAN_IIO(IN6, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
457 PALMAS_ADC_CHAN_IIO(IN7, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
458 PALMAS_ADC_CHAN_IIO(IN8, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
459 PALMAS_ADC_CHAN_IIO(IN9, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
460 PALMAS_ADC_CHAN_IIO(IN10, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
461 PALMAS_ADC_CHAN_IIO(IN11, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
462 PALMAS_ADC_CHAN_IIO(IN12, IIO_TEMP, IIO_CHAN_INFO_RAW),
463 PALMAS_ADC_CHAN_IIO(IN13, IIO_TEMP, IIO_CHAN_INFO_RAW),
464 PALMAS_ADC_CHAN_IIO(IN14, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
465 PALMAS_ADC_CHAN_IIO(IN15, IIO_VOLTAGE, IIO_CHAN_INFO_PROCESSED),
468 static int palmas_gpadc_get_adc_dt_data(struct platform_device *pdev,
469 struct palmas_gpadc_platform_data **gpadc_pdata)
471 struct device_node *np = pdev->dev.of_node;
472 struct palmas_gpadc_platform_data *gp_data;
476 gp_data = devm_kzalloc(&pdev->dev, sizeof(*gp_data), GFP_KERNEL);
480 ret = of_property_read_u32(np, "ti,channel0-current-microamp", &pval);
482 gp_data->ch0_current = pval;
484 ret = of_property_read_u32(np, "ti,channel3-current-microamp", &pval);
486 gp_data->ch3_current = pval;
488 gp_data->extended_delay = of_property_read_bool(np,
489 "ti,enable-extended-delay");
491 *gpadc_pdata = gp_data;
496 static int palmas_gpadc_probe(struct platform_device *pdev)
498 struct palmas_gpadc *adc;
499 struct palmas_platform_data *pdata;
500 struct palmas_gpadc_platform_data *gpadc_pdata = NULL;
501 struct iio_dev *indio_dev;
504 pdata = dev_get_platdata(pdev->dev.parent);
506 if (pdata && pdata->gpadc_pdata)
507 gpadc_pdata = pdata->gpadc_pdata;
509 if (!gpadc_pdata && pdev->dev.of_node) {
510 ret = palmas_gpadc_get_adc_dt_data(pdev, &gpadc_pdata);
517 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
519 dev_err(&pdev->dev, "iio_device_alloc failed\n");
523 adc = iio_priv(indio_dev);
524 adc->dev = &pdev->dev;
525 adc->palmas = dev_get_drvdata(pdev->dev.parent);
526 adc->adc_info = palmas_gpadc_info;
528 mutex_init(&adc->lock);
530 init_completion(&adc->conv_completion);
531 platform_set_drvdata(pdev, indio_dev);
533 adc->auto_conversion_period = gpadc_pdata->auto_conversion_period_ms;
534 adc->irq = palmas_irq_get_virq(adc->palmas, PALMAS_GPADC_EOC_SW_IRQ);
537 "get virq failed: %d\n", adc->irq);
541 ret = request_threaded_irq(adc->irq, NULL,
543 IRQF_ONESHOT, dev_name(adc->dev),
547 "request irq %d failed: %d\n", adc->irq, ret);
551 if (gpadc_pdata->adc_wakeup1_data) {
552 memcpy(&adc->wakeup1_data, gpadc_pdata->adc_wakeup1_data,
553 sizeof(adc->wakeup1_data));
554 adc->wakeup1_enable = true;
555 adc->irq_auto_0 = platform_get_irq(pdev, 1);
556 ret = request_threaded_irq(adc->irq_auto_0, NULL,
557 palmas_gpadc_irq_auto,
559 "palmas-adc-auto-0", adc);
561 dev_err(adc->dev, "request auto0 irq %d failed: %d\n",
562 adc->irq_auto_0, ret);
567 if (gpadc_pdata->adc_wakeup2_data) {
568 memcpy(&adc->wakeup2_data, gpadc_pdata->adc_wakeup2_data,
569 sizeof(adc->wakeup2_data));
570 adc->wakeup2_enable = true;
571 adc->irq_auto_1 = platform_get_irq(pdev, 2);
572 ret = request_threaded_irq(adc->irq_auto_1, NULL,
573 palmas_gpadc_irq_auto,
575 "palmas-adc-auto-1", adc);
577 dev_err(adc->dev, "request auto1 irq %d failed: %d\n",
578 adc->irq_auto_1, ret);
579 goto out_irq_auto0_free;
583 /* set the current source 0 (value 0/5/15/20 uA => 0..3) */
584 if (gpadc_pdata->ch0_current <= 1)
585 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_0;
586 else if (gpadc_pdata->ch0_current <= 5)
587 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_5;
588 else if (gpadc_pdata->ch0_current <= 15)
589 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_15;
591 adc->ch0_current = PALMAS_ADC_CH0_CURRENT_SRC_20;
593 /* set the current source 3 (value 0/10/400/800 uA => 0..3) */
594 if (gpadc_pdata->ch3_current <= 1)
595 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_0;
596 else if (gpadc_pdata->ch3_current <= 10)
597 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_10;
598 else if (gpadc_pdata->ch3_current <= 400)
599 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_400;
601 adc->ch3_current = PALMAS_ADC_CH3_CURRENT_SRC_800;
603 adc->extended_delay = gpadc_pdata->extended_delay;
605 indio_dev->name = MOD_NAME;
606 indio_dev->info = &palmas_gpadc_iio_info;
607 indio_dev->modes = INDIO_DIRECT_MODE;
608 indio_dev->channels = palmas_gpadc_iio_channel;
609 indio_dev->num_channels = ARRAY_SIZE(palmas_gpadc_iio_channel);
611 ret = iio_device_register(indio_dev);
613 dev_err(adc->dev, "iio_device_register() failed: %d\n", ret);
614 goto out_irq_auto1_free;
617 device_set_wakeup_capable(&pdev->dev, 1);
618 for (i = 0; i < PALMAS_ADC_CH_MAX; i++) {
619 if (!(adc->adc_info[i].is_uncalibrated))
620 palmas_gpadc_calibrate(adc, i);
623 if (adc->wakeup1_enable || adc->wakeup2_enable)
624 device_wakeup_enable(&pdev->dev);
629 if (gpadc_pdata->adc_wakeup2_data)
630 free_irq(adc->irq_auto_1, adc);
632 if (gpadc_pdata->adc_wakeup1_data)
633 free_irq(adc->irq_auto_0, adc);
635 free_irq(adc->irq, adc);
640 static int palmas_gpadc_remove(struct platform_device *pdev)
642 struct iio_dev *indio_dev = dev_to_iio_dev(&pdev->dev);
643 struct palmas_gpadc *adc = iio_priv(indio_dev);
645 if (adc->wakeup1_enable || adc->wakeup2_enable)
646 device_wakeup_disable(&pdev->dev);
647 iio_device_unregister(indio_dev);
648 free_irq(adc->irq, adc);
649 if (adc->wakeup1_enable)
650 free_irq(adc->irq_auto_0, adc);
651 if (adc->wakeup2_enable)
652 free_irq(adc->irq_auto_1, adc);
657 static int palmas_adc_wakeup_configure(struct palmas_gpadc *adc)
659 int adc_period, conv;
661 int ch0 = 0, ch1 = 0;
665 adc_period = adc->auto_conversion_period;
666 for (i = 0; i < 16; ++i) {
667 if (((1000 * (1 << i)) / 32) >= adc_period)
673 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
674 PALMAS_GPADC_AUTO_CTRL,
675 PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK,
678 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
683 if (adc->wakeup1_enable) {
686 ch0 = adc->wakeup1_data.adc_channel_number;
687 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN;
688 if (adc->wakeup1_data.adc_high_threshold > 0) {
689 thres = adc->wakeup1_data.adc_high_threshold;
692 thres = adc->wakeup1_data.adc_low_threshold;
693 polarity = PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL;
696 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
697 PALMAS_GPADC_THRES_CONV0_LSB, thres & 0xFF);
700 "THRES_CONV0_LSB write failed: %d\n", ret);
704 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
705 PALMAS_GPADC_THRES_CONV0_MSB,
706 ((thres >> 8) & 0xF) | polarity);
709 "THRES_CONV0_MSB write failed: %d\n", ret);
714 if (adc->wakeup2_enable) {
717 ch1 = adc->wakeup2_data.adc_channel_number;
718 conv |= PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN;
719 if (adc->wakeup2_data.adc_high_threshold > 0) {
720 thres = adc->wakeup2_data.adc_high_threshold;
723 thres = adc->wakeup2_data.adc_low_threshold;
724 polarity = PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL;
727 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
728 PALMAS_GPADC_THRES_CONV1_LSB, thres & 0xFF);
731 "THRES_CONV1_LSB write failed: %d\n", ret);
735 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
736 PALMAS_GPADC_THRES_CONV1_MSB,
737 ((thres >> 8) & 0xF) | polarity);
740 "THRES_CONV1_MSB write failed: %d\n", ret);
745 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
746 PALMAS_GPADC_AUTO_SELECT, (ch1 << 4) | ch0);
748 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
752 ret = palmas_update_bits(adc->palmas, PALMAS_GPADC_BASE,
753 PALMAS_GPADC_AUTO_CTRL,
754 PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN |
755 PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN, conv);
757 dev_err(adc->dev, "AUTO_CTRL write failed: %d\n", ret);
762 static int palmas_adc_wakeup_reset(struct palmas_gpadc *adc)
766 ret = palmas_write(adc->palmas, PALMAS_GPADC_BASE,
767 PALMAS_GPADC_AUTO_SELECT, 0);
769 dev_err(adc->dev, "AUTO_SELECT write failed: %d\n", ret);
773 ret = palmas_disable_auto_conversion(adc);
775 dev_err(adc->dev, "Disable auto conversion failed: %d\n", ret);
780 static int palmas_gpadc_suspend(struct device *dev)
782 struct iio_dev *indio_dev = dev_get_drvdata(dev);
783 struct palmas_gpadc *adc = iio_priv(indio_dev);
784 int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
787 if (!device_may_wakeup(dev) || !wakeup)
790 ret = palmas_adc_wakeup_configure(adc);
794 if (adc->wakeup1_enable)
795 enable_irq_wake(adc->irq_auto_0);
797 if (adc->wakeup2_enable)
798 enable_irq_wake(adc->irq_auto_1);
803 static int palmas_gpadc_resume(struct device *dev)
805 struct iio_dev *indio_dev = dev_get_drvdata(dev);
806 struct palmas_gpadc *adc = iio_priv(indio_dev);
807 int wakeup = adc->wakeup1_enable || adc->wakeup2_enable;
810 if (!device_may_wakeup(dev) || !wakeup)
813 ret = palmas_adc_wakeup_reset(adc);
817 if (adc->wakeup1_enable)
818 disable_irq_wake(adc->irq_auto_0);
820 if (adc->wakeup2_enable)
821 disable_irq_wake(adc->irq_auto_1);
826 static DEFINE_SIMPLE_DEV_PM_OPS(palmas_pm_ops, palmas_gpadc_suspend,
827 palmas_gpadc_resume);
829 static const struct of_device_id of_palmas_gpadc_match_tbl[] = {
830 { .compatible = "ti,palmas-gpadc", },
833 MODULE_DEVICE_TABLE(of, of_palmas_gpadc_match_tbl);
835 static struct platform_driver palmas_gpadc_driver = {
836 .probe = palmas_gpadc_probe,
837 .remove = palmas_gpadc_remove,
840 .pm = pm_sleep_ptr(&palmas_pm_ops),
841 .of_match_table = of_palmas_gpadc_match_tbl,
844 module_platform_driver(palmas_gpadc_driver);
846 MODULE_DESCRIPTION("palmas GPADC driver");
847 MODULE_AUTHOR("Pradeep Goudagunta<pgoudagunta@nvidia.com>");
848 MODULE_ALIAS("platform:palmas-gpadc");
849 MODULE_LICENSE("GPL v2");