3 * Copyright (C) 2014 Philippe Reynes
5 * based on linux/drivers/iio/ad7923.c
6 * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
7 * Copyright 2012 CS Systemes d'Information
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 * Partial support for max1027 and similar chips.
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/spi/spi.h>
21 #include <linux/delay.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/trigger.h>
26 #include <linux/iio/trigger_consumer.h>
27 #include <linux/iio/triggered_buffer.h>
29 #define MAX1027_CONV_REG BIT(7)
30 #define MAX1027_SETUP_REG BIT(6)
31 #define MAX1027_AVG_REG BIT(5)
32 #define MAX1027_RST_REG BIT(4)
34 /* conversion register */
35 #define MAX1027_TEMP BIT(0)
36 #define MAX1027_SCAN_0_N (0x00 << 1)
37 #define MAX1027_SCAN_N_M (0x01 << 1)
38 #define MAX1027_SCAN_N (0x02 << 1)
39 #define MAX1027_NOSCAN (0x03 << 1)
40 #define MAX1027_CHAN(n) ((n) << 3)
43 #define MAX1027_UNIPOLAR 0x02
44 #define MAX1027_BIPOLAR 0x03
45 #define MAX1027_REF_MODE0 (0x00 << 2)
46 #define MAX1027_REF_MODE1 (0x01 << 2)
47 #define MAX1027_REF_MODE2 (0x02 << 2)
48 #define MAX1027_REF_MODE3 (0x03 << 2)
49 #define MAX1027_CKS_MODE0 (0x00 << 4)
50 #define MAX1027_CKS_MODE1 (0x01 << 4)
51 #define MAX1027_CKS_MODE2 (0x02 << 4)
52 #define MAX1027_CKS_MODE3 (0x03 << 4)
54 /* averaging register */
55 #define MAX1027_NSCAN_4 0x00
56 #define MAX1027_NSCAN_8 0x01
57 #define MAX1027_NSCAN_12 0x02
58 #define MAX1027_NSCAN_16 0x03
59 #define MAX1027_NAVG_4 (0x00 << 2)
60 #define MAX1027_NAVG_8 (0x01 << 2)
61 #define MAX1027_NAVG_16 (0x02 << 2)
62 #define MAX1027_NAVG_32 (0x03 << 2)
63 #define MAX1027_AVG_EN BIT(4)
71 static const struct spi_device_id max1027_id[] = {
77 MODULE_DEVICE_TABLE(spi, max1027_id);
80 static const struct of_device_id max1027_adc_dt_ids[] = {
81 { .compatible = "maxim,max1027" },
82 { .compatible = "maxim,max1029" },
83 { .compatible = "maxim,max1031" },
86 MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
89 #define MAX1027_V_CHAN(index) \
91 .type = IIO_VOLTAGE, \
94 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
95 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
96 .scan_index = index + 1, \
102 .endianness = IIO_BE, \
106 #define MAX1027_T_CHAN \
110 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
111 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
117 .endianness = IIO_BE, \
121 static const struct iio_chan_spec max1027_channels[] = {
133 static const struct iio_chan_spec max1029_channels[] = {
149 static const struct iio_chan_spec max1031_channels[] = {
169 static const unsigned long max1027_available_scan_masks[] = {
174 static const unsigned long max1029_available_scan_masks[] = {
179 static const unsigned long max1031_available_scan_masks[] = {
184 struct max1027_chip_info {
185 const struct iio_chan_spec *channels;
186 unsigned int num_channels;
187 const unsigned long *available_scan_masks;
190 static const struct max1027_chip_info max1027_chip_info_tbl[] = {
192 .channels = max1027_channels,
193 .num_channels = ARRAY_SIZE(max1027_channels),
194 .available_scan_masks = max1027_available_scan_masks,
197 .channels = max1029_channels,
198 .num_channels = ARRAY_SIZE(max1029_channels),
199 .available_scan_masks = max1029_available_scan_masks,
202 .channels = max1031_channels,
203 .num_channels = ARRAY_SIZE(max1031_channels),
204 .available_scan_masks = max1031_available_scan_masks,
208 struct max1027_state {
209 const struct max1027_chip_info *info;
210 struct spi_device *spi;
211 struct iio_trigger *trig;
215 u8 reg ____cacheline_aligned;
218 static int max1027_read_single_value(struct iio_dev *indio_dev,
219 struct iio_chan_spec const *chan,
223 struct max1027_state *st = iio_priv(indio_dev);
225 if (iio_buffer_enabled(indio_dev)) {
226 dev_warn(&indio_dev->dev, "trigger mode already enabled");
230 /* Start acquisition on conversion register write */
231 st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2;
232 ret = spi_write(st->spi, &st->reg, 1);
234 dev_err(&indio_dev->dev,
235 "Failed to configure setup register\n");
239 /* Configure conversion register with the requested chan */
240 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
242 if (chan->type == IIO_TEMP)
243 st->reg |= MAX1027_TEMP;
244 ret = spi_write(st->spi, &st->reg, 1);
246 dev_err(&indio_dev->dev,
247 "Failed to configure conversion register\n");
252 * For an unknown reason, when we use the mode "10" (write
253 * conversion register), the interrupt doesn't occur every time.
254 * So we just wait 1 ms.
259 ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
263 *val = be16_to_cpu(st->buffer[0]);
268 static int max1027_read_raw(struct iio_dev *indio_dev,
269 struct iio_chan_spec const *chan,
270 int *val, int *val2, long mask)
273 struct max1027_state *st = iio_priv(indio_dev);
275 mutex_lock(&st->lock);
278 case IIO_CHAN_INFO_RAW:
279 ret = max1027_read_single_value(indio_dev, chan, val);
281 case IIO_CHAN_INFO_SCALE:
282 switch (chan->type) {
286 ret = IIO_VAL_FRACTIONAL;
291 ret = IIO_VAL_FRACTIONAL_LOG2;
303 mutex_unlock(&st->lock);
308 static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
309 unsigned reg, unsigned writeval,
312 struct max1027_state *st = iio_priv(indio_dev);
313 u8 *val = (u8 *)st->buffer;
319 return spi_write(st->spi, val, 1);
322 static int max1027_validate_trigger(struct iio_dev *indio_dev,
323 struct iio_trigger *trig)
325 struct max1027_state *st = iio_priv(indio_dev);
327 if (st->trig != trig)
333 static int max1027_set_trigger_state(struct iio_trigger *trig, bool state)
335 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
336 struct max1027_state *st = iio_priv(indio_dev);
340 /* Start acquisition on cnvst */
341 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 |
343 ret = spi_write(st->spi, &st->reg, 1);
347 /* Scan from 0 to max */
348 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) |
349 MAX1027_SCAN_N_M | MAX1027_TEMP;
350 ret = spi_write(st->spi, &st->reg, 1);
354 /* Start acquisition on conversion register write */
355 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 |
357 ret = spi_write(st->spi, &st->reg, 1);
365 static irqreturn_t max1027_trigger_handler(int irq, void *private)
367 struct iio_poll_func *pf = private;
368 struct iio_dev *indio_dev = pf->indio_dev;
369 struct max1027_state *st = iio_priv(indio_dev);
371 pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private);
373 /* fill buffer with all channel */
374 spi_read(st->spi, st->buffer, indio_dev->masklength * 2);
376 iio_push_to_buffers(indio_dev, st->buffer);
378 iio_trigger_notify_done(indio_dev->trig);
383 static const struct iio_trigger_ops max1027_trigger_ops = {
384 .validate_device = &iio_trigger_validate_own_device,
385 .set_trigger_state = &max1027_set_trigger_state,
388 static const struct iio_info max1027_info = {
389 .read_raw = &max1027_read_raw,
390 .validate_trigger = &max1027_validate_trigger,
391 .debugfs_reg_access = &max1027_debugfs_reg_access,
394 static int max1027_probe(struct spi_device *spi)
397 struct iio_dev *indio_dev;
398 struct max1027_state *st;
400 pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi);
402 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
403 if (indio_dev == NULL) {
404 pr_err("Can't allocate iio device\n");
408 spi_set_drvdata(spi, indio_dev);
410 st = iio_priv(indio_dev);
412 st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
414 mutex_init(&st->lock);
416 indio_dev->name = spi_get_device_id(spi)->name;
417 indio_dev->dev.parent = &spi->dev;
418 indio_dev->dev.of_node = spi->dev.of_node;
419 indio_dev->info = &max1027_info;
420 indio_dev->modes = INDIO_DIRECT_MODE;
421 indio_dev->channels = st->info->channels;
422 indio_dev->num_channels = st->info->num_channels;
423 indio_dev->available_scan_masks = st->info->available_scan_masks;
425 st->buffer = devm_kmalloc(&indio_dev->dev,
426 indio_dev->num_channels * 2,
428 if (st->buffer == NULL) {
429 dev_err(&indio_dev->dev, "Can't allocate buffer\n");
433 ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
434 &max1027_trigger_handler, NULL);
436 dev_err(&indio_dev->dev, "Failed to setup buffer\n");
440 st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
442 if (st->trig == NULL) {
444 dev_err(&indio_dev->dev, "Failed to allocate iio trigger\n");
445 goto fail_trigger_alloc;
448 st->trig->ops = &max1027_trigger_ops;
449 st->trig->dev.parent = &spi->dev;
450 iio_trigger_set_drvdata(st->trig, indio_dev);
451 iio_trigger_register(st->trig);
453 ret = devm_request_threaded_irq(&spi->dev, spi->irq,
454 iio_trigger_generic_data_rdy_poll,
456 IRQF_TRIGGER_FALLING,
457 spi->dev.driver->name, st->trig);
459 dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
460 goto fail_dev_register;
463 /* Disable averaging */
464 st->reg = MAX1027_AVG_REG;
465 ret = spi_write(st->spi, &st->reg, 1);
467 dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
468 goto fail_dev_register;
471 ret = iio_device_register(indio_dev);
473 dev_err(&indio_dev->dev, "Failed to register iio device\n");
474 goto fail_dev_register;
481 iio_triggered_buffer_cleanup(indio_dev);
486 static int max1027_remove(struct spi_device *spi)
488 struct iio_dev *indio_dev = spi_get_drvdata(spi);
490 pr_debug("%s: remove(spi = 0x%p)\n", __func__, spi);
492 iio_device_unregister(indio_dev);
493 iio_triggered_buffer_cleanup(indio_dev);
498 static struct spi_driver max1027_driver = {
501 .of_match_table = of_match_ptr(max1027_adc_dt_ids),
503 .probe = max1027_probe,
504 .remove = max1027_remove,
505 .id_table = max1027_id,
507 module_spi_driver(max1027_driver);
509 MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
510 MODULE_DESCRIPTION("MAX1027/MAX1029/MAX1031 ADC");
511 MODULE_LICENSE("GPL v2");