1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale i.MX7D ADC driver
5 * Copyright (C) 2015 Freescale Semiconductor, Inc.
9 #include <linux/completion.h>
10 #include <linux/err.h>
11 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/regulator/consumer.h>
19 #include <linux/iio/iio.h>
20 #include <linux/iio/driver.h>
21 #include <linux/iio/sysfs.h>
24 #define IMX7D_REG_ADC_CH_A_CFG1 0x00
25 #define IMX7D_REG_ADC_CH_A_CFG2 0x10
26 #define IMX7D_REG_ADC_CH_B_CFG1 0x20
27 #define IMX7D_REG_ADC_CH_B_CFG2 0x30
28 #define IMX7D_REG_ADC_CH_C_CFG1 0x40
29 #define IMX7D_REG_ADC_CH_C_CFG2 0x50
30 #define IMX7D_REG_ADC_CH_D_CFG1 0x60
31 #define IMX7D_REG_ADC_CH_D_CFG2 0x70
32 #define IMX7D_REG_ADC_CH_SW_CFG 0x80
33 #define IMX7D_REG_ADC_TIMER_UNIT 0x90
34 #define IMX7D_REG_ADC_DMA_FIFO 0xa0
35 #define IMX7D_REG_ADC_FIFO_STATUS 0xb0
36 #define IMX7D_REG_ADC_INT_SIG_EN 0xc0
37 #define IMX7D_REG_ADC_INT_EN 0xd0
38 #define IMX7D_REG_ADC_INT_STATUS 0xe0
39 #define IMX7D_REG_ADC_CHA_B_CNV_RSLT 0xf0
40 #define IMX7D_REG_ADC_CHC_D_CNV_RSLT 0x100
41 #define IMX7D_REG_ADC_CH_SW_CNV_RSLT 0x110
42 #define IMX7D_REG_ADC_DMA_FIFO_DAT 0x120
43 #define IMX7D_REG_ADC_ADC_CFG 0x130
45 #define IMX7D_REG_ADC_CHANNEL_CFG2_BASE 0x10
46 #define IMX7D_EACH_CHANNEL_REG_OFFSET 0x20
48 #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN (0x1 << 31)
49 #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE BIT(30)
50 #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN BIT(29)
51 #define IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(x) ((x) << 24)
53 #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_4 (0x0 << 12)
54 #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_8 (0x1 << 12)
55 #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_16 (0x2 << 12)
56 #define IMX7D_REG_ADC_CH_CFG2_AVG_NUM_32 (0x3 << 12)
58 #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_4 (0x0 << 29)
59 #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_8 (0x1 << 29)
60 #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_16 (0x2 << 29)
61 #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_32 (0x3 << 29)
62 #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_64 (0x4 << 29)
63 #define IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_128 (0x5 << 29)
65 #define IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN BIT(31)
66 #define IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN BIT(1)
67 #define IMX7D_REG_ADC_ADC_CFG_ADC_EN BIT(0)
69 #define IMX7D_REG_ADC_INT_CHA_COV_INT_EN BIT(8)
70 #define IMX7D_REG_ADC_INT_CHB_COV_INT_EN BIT(9)
71 #define IMX7D_REG_ADC_INT_CHC_COV_INT_EN BIT(10)
72 #define IMX7D_REG_ADC_INT_CHD_COV_INT_EN BIT(11)
73 #define IMX7D_REG_ADC_INT_CHANNEL_INT_EN \
74 (IMX7D_REG_ADC_INT_CHA_COV_INT_EN | \
75 IMX7D_REG_ADC_INT_CHB_COV_INT_EN | \
76 IMX7D_REG_ADC_INT_CHC_COV_INT_EN | \
77 IMX7D_REG_ADC_INT_CHD_COV_INT_EN)
78 #define IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS 0xf00
79 #define IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT 0xf0000
81 #define IMX7D_ADC_TIMEOUT msecs_to_jiffies(100)
82 #define IMX7D_ADC_INPUT_CLK 24000000
84 enum imx7d_adc_clk_pre_div {
85 IMX7D_ADC_ANALOG_CLK_PRE_DIV_4,
86 IMX7D_ADC_ANALOG_CLK_PRE_DIV_8,
87 IMX7D_ADC_ANALOG_CLK_PRE_DIV_16,
88 IMX7D_ADC_ANALOG_CLK_PRE_DIV_32,
89 IMX7D_ADC_ANALOG_CLK_PRE_DIV_64,
90 IMX7D_ADC_ANALOG_CLK_PRE_DIV_128,
93 enum imx7d_adc_average_num {
94 IMX7D_ADC_AVERAGE_NUM_4,
95 IMX7D_ADC_AVERAGE_NUM_8,
96 IMX7D_ADC_AVERAGE_NUM_16,
97 IMX7D_ADC_AVERAGE_NUM_32,
100 struct imx7d_adc_feature {
101 enum imx7d_adc_clk_pre_div clk_pre_div;
102 enum imx7d_adc_average_num avg_num;
104 u32 core_time_unit; /* impact the sample rate */
117 struct regulator *vref;
118 struct imx7d_adc_feature adc_feature;
120 struct completion completion;
123 struct imx7d_adc_analogue_core_clk {
128 #define IMX7D_ADC_ANALOGUE_CLK_CONFIG(_pre_div, _reg_conf) { \
129 .pre_div = (_pre_div), \
130 .reg_config = (_reg_conf), \
133 static const struct imx7d_adc_analogue_core_clk imx7d_adc_analogue_clk[] = {
134 IMX7D_ADC_ANALOGUE_CLK_CONFIG(4, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_4),
135 IMX7D_ADC_ANALOGUE_CLK_CONFIG(8, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_8),
136 IMX7D_ADC_ANALOGUE_CLK_CONFIG(16, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_16),
137 IMX7D_ADC_ANALOGUE_CLK_CONFIG(32, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_32),
138 IMX7D_ADC_ANALOGUE_CLK_CONFIG(64, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_64),
139 IMX7D_ADC_ANALOGUE_CLK_CONFIG(128, IMX7D_REG_ADC_TIMER_UNIT_PRE_DIV_128),
142 #define IMX7D_ADC_CHAN(_idx) { \
143 .type = IIO_VOLTAGE, \
146 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
147 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
148 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
151 static const struct iio_chan_spec imx7d_adc_iio_channels[] = {
170 static const u32 imx7d_adc_average_num[] = {
171 IMX7D_REG_ADC_CH_CFG2_AVG_NUM_4,
172 IMX7D_REG_ADC_CH_CFG2_AVG_NUM_8,
173 IMX7D_REG_ADC_CH_CFG2_AVG_NUM_16,
174 IMX7D_REG_ADC_CH_CFG2_AVG_NUM_32,
177 static void imx7d_adc_feature_config(struct imx7d_adc *info)
179 info->adc_feature.clk_pre_div = IMX7D_ADC_ANALOG_CLK_PRE_DIV_4;
180 info->adc_feature.avg_num = IMX7D_ADC_AVERAGE_NUM_32;
181 info->adc_feature.core_time_unit = 1;
184 static void imx7d_adc_sample_rate_set(struct imx7d_adc *info)
186 struct imx7d_adc_feature *adc_feature = &info->adc_feature;
187 struct imx7d_adc_analogue_core_clk adc_analogure_clk;
193 * Before sample set, disable channel A,B,C,D. Here we
194 * clear the bit 31 of register REG_ADC_CH_A\B\C\D_CFG1.
196 for (i = 0; i < 4; i++) {
198 readl(info->regs + i * IMX7D_EACH_CHANNEL_REG_OFFSET);
199 tmp_cfg1 &= ~IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN;
201 info->regs + i * IMX7D_EACH_CHANNEL_REG_OFFSET);
204 adc_analogure_clk = imx7d_adc_analogue_clk[adc_feature->clk_pre_div];
205 sample_rate |= adc_analogure_clk.reg_config;
206 info->pre_div_num = adc_analogure_clk.pre_div;
208 sample_rate |= adc_feature->core_time_unit;
209 writel(sample_rate, info->regs + IMX7D_REG_ADC_TIMER_UNIT);
212 static void imx7d_adc_hw_init(struct imx7d_adc *info)
216 /* power up and enable adc analogue core */
217 cfg = readl(info->regs + IMX7D_REG_ADC_ADC_CFG);
218 cfg &= ~(IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN |
219 IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN);
220 cfg |= IMX7D_REG_ADC_ADC_CFG_ADC_EN;
221 writel(cfg, info->regs + IMX7D_REG_ADC_ADC_CFG);
223 /* enable channel A,B,C,D interrupt */
224 writel(IMX7D_REG_ADC_INT_CHANNEL_INT_EN,
225 info->regs + IMX7D_REG_ADC_INT_SIG_EN);
226 writel(IMX7D_REG_ADC_INT_CHANNEL_INT_EN,
227 info->regs + IMX7D_REG_ADC_INT_EN);
229 imx7d_adc_sample_rate_set(info);
232 static void imx7d_adc_channel_set(struct imx7d_adc *info)
238 channel = info->channel;
240 /* the channel choose single conversion, and enable average mode */
241 cfg1 |= (IMX7D_REG_ADC_CH_CFG1_CHANNEL_EN |
242 IMX7D_REG_ADC_CH_CFG1_CHANNEL_SINGLE |
243 IMX7D_REG_ADC_CH_CFG1_CHANNEL_AVG_EN);
246 * physical channel 0 chose logical channel A
247 * physical channel 1 chose logical channel B
248 * physical channel 2 chose logical channel C
249 * physical channel 3 chose logical channel D
251 cfg1 |= IMX7D_REG_ADC_CH_CFG1_CHANNEL_SEL(channel);
254 * read register REG_ADC_CH_A\B\C\D_CFG2, according to the
257 cfg2 = readl(info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
258 IMX7D_REG_ADC_CHANNEL_CFG2_BASE);
260 cfg2 |= imx7d_adc_average_num[info->adc_feature.avg_num];
263 * write the register REG_ADC_CH_A\B\C\D_CFG2, according to
266 writel(cfg2, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel +
267 IMX7D_REG_ADC_CHANNEL_CFG2_BASE);
268 writel(cfg1, info->regs + IMX7D_EACH_CHANNEL_REG_OFFSET * channel);
271 static u32 imx7d_adc_get_sample_rate(struct imx7d_adc *info)
273 u32 analogue_core_clk;
274 u32 core_time_unit = info->adc_feature.core_time_unit;
277 analogue_core_clk = IMX7D_ADC_INPUT_CLK / info->pre_div_num;
278 tmp = (core_time_unit + 1) * 6;
280 return analogue_core_clk / tmp;
283 static int imx7d_adc_read_raw(struct iio_dev *indio_dev,
284 struct iio_chan_spec const *chan,
289 struct imx7d_adc *info = iio_priv(indio_dev);
295 case IIO_CHAN_INFO_RAW:
296 mutex_lock(&indio_dev->mlock);
297 reinit_completion(&info->completion);
299 channel = chan->channel & 0x03;
300 info->channel = channel;
301 imx7d_adc_channel_set(info);
303 ret = wait_for_completion_interruptible_timeout
304 (&info->completion, IMX7D_ADC_TIMEOUT);
306 mutex_unlock(&indio_dev->mlock);
310 mutex_unlock(&indio_dev->mlock);
315 mutex_unlock(&indio_dev->mlock);
318 case IIO_CHAN_INFO_SCALE:
319 info->vref_uv = regulator_get_voltage(info->vref);
320 *val = info->vref_uv / 1000;
322 return IIO_VAL_FRACTIONAL_LOG2;
324 case IIO_CHAN_INFO_SAMP_FREQ:
325 *val = imx7d_adc_get_sample_rate(info);
333 static int imx7d_adc_read_data(struct imx7d_adc *info)
338 channel = info->channel & 0x03;
341 * channel A and B conversion result share one register,
342 * bit[27~16] is the channel B conversion result,
343 * bit[11~0] is the channel A conversion result.
344 * channel C and D is the same.
347 value = readl(info->regs + IMX7D_REG_ADC_CHA_B_CNV_RSLT);
349 value = readl(info->regs + IMX7D_REG_ADC_CHC_D_CNV_RSLT);
350 if (channel & 0x1) /* channel B or D */
351 value = (value >> 16) & 0xFFF;
352 else /* channel A or C */
358 static irqreturn_t imx7d_adc_isr(int irq, void *dev_id)
360 struct imx7d_adc *info = dev_id;
363 status = readl(info->regs + IMX7D_REG_ADC_INT_STATUS);
364 if (status & IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS) {
365 info->value = imx7d_adc_read_data(info);
366 complete(&info->completion);
369 * The register IMX7D_REG_ADC_INT_STATUS can't clear
370 * itself after read operation, need software to write
371 * 0 to the related bit. Here we clear the channel A/B/C/D
372 * conversion finished flag.
374 status &= ~IMX7D_REG_ADC_INT_STATUS_CHANNEL_INT_STATUS;
375 writel(status, info->regs + IMX7D_REG_ADC_INT_STATUS);
379 * If the channel A/B/C/D conversion timeout, report it and clear these
382 if (status & IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT) {
384 "ADC got conversion time out interrupt: 0x%08x\n",
386 status &= ~IMX7D_REG_ADC_INT_STATUS_CHANNEL_CONV_TIME_OUT;
387 writel(status, info->regs + IMX7D_REG_ADC_INT_STATUS);
393 static int imx7d_adc_reg_access(struct iio_dev *indio_dev,
394 unsigned reg, unsigned writeval,
397 struct imx7d_adc *info = iio_priv(indio_dev);
399 if (!readval || reg % 4 || reg > IMX7D_REG_ADC_ADC_CFG)
402 *readval = readl(info->regs + reg);
407 static const struct iio_info imx7d_adc_iio_info = {
408 .read_raw = &imx7d_adc_read_raw,
409 .debugfs_reg_access = &imx7d_adc_reg_access,
412 static const struct of_device_id imx7d_adc_match[] = {
413 { .compatible = "fsl,imx7d-adc", },
416 MODULE_DEVICE_TABLE(of, imx7d_adc_match);
418 static void imx7d_adc_power_down(struct imx7d_adc *info)
422 adc_cfg = readl(info->regs + IMX7D_REG_ADC_ADC_CFG);
423 adc_cfg |= IMX7D_REG_ADC_ADC_CFG_ADC_CLK_DOWN |
424 IMX7D_REG_ADC_ADC_CFG_ADC_POWER_DOWN;
425 adc_cfg &= ~IMX7D_REG_ADC_ADC_CFG_ADC_EN;
426 writel(adc_cfg, info->regs + IMX7D_REG_ADC_ADC_CFG);
429 static int imx7d_adc_enable(struct device *dev)
431 struct iio_dev *indio_dev = dev_get_drvdata(dev);
432 struct imx7d_adc *info = iio_priv(indio_dev);
435 ret = regulator_enable(info->vref);
438 "Can't enable adc reference top voltage, err = %d\n",
443 ret = clk_prepare_enable(info->clk);
446 "Could not prepare or enable clock.\n");
447 regulator_disable(info->vref);
451 imx7d_adc_hw_init(info);
456 static int imx7d_adc_disable(struct device *dev)
458 struct iio_dev *indio_dev = dev_get_drvdata(dev);
459 struct imx7d_adc *info = iio_priv(indio_dev);
461 imx7d_adc_power_down(info);
463 clk_disable_unprepare(info->clk);
464 regulator_disable(info->vref);
469 static void __imx7d_adc_disable(void *data)
471 imx7d_adc_disable(data);
474 static int imx7d_adc_probe(struct platform_device *pdev)
476 struct imx7d_adc *info;
477 struct iio_dev *indio_dev;
478 struct device *dev = &pdev->dev;
482 indio_dev = devm_iio_device_alloc(dev, sizeof(*info));
484 dev_err(&pdev->dev, "Failed allocating iio device\n");
488 info = iio_priv(indio_dev);
491 info->regs = devm_platform_ioremap_resource(pdev, 0);
492 if (IS_ERR(info->regs))
493 return PTR_ERR(info->regs);
495 irq = platform_get_irq(pdev, 0);
497 return dev_err_probe(dev, irq, "Failed getting irq\n");
499 info->clk = devm_clk_get(dev, "adc");
500 if (IS_ERR(info->clk))
501 return dev_err_probe(dev, PTR_ERR(info->clk), "Failed getting clock\n");
503 info->vref = devm_regulator_get(dev, "vref");
504 if (IS_ERR(info->vref))
505 return dev_err_probe(dev, PTR_ERR(info->vref),
506 "Failed getting reference voltage\n");
508 platform_set_drvdata(pdev, indio_dev);
510 init_completion(&info->completion);
512 indio_dev->name = dev_name(dev);
513 indio_dev->info = &imx7d_adc_iio_info;
514 indio_dev->modes = INDIO_DIRECT_MODE;
515 indio_dev->channels = imx7d_adc_iio_channels;
516 indio_dev->num_channels = ARRAY_SIZE(imx7d_adc_iio_channels);
518 ret = devm_request_irq(dev, irq, imx7d_adc_isr, 0, dev_name(dev), info);
520 dev_err(dev, "Failed requesting irq, irq = %d\n", irq);
524 imx7d_adc_feature_config(info);
526 ret = imx7d_adc_enable(dev);
530 ret = devm_add_action_or_reset(dev, __imx7d_adc_disable, dev);
534 ret = devm_iio_device_register(dev, indio_dev);
536 dev_err(&pdev->dev, "Couldn't register the device.\n");
543 static DEFINE_SIMPLE_DEV_PM_OPS(imx7d_adc_pm_ops, imx7d_adc_disable,
546 static struct platform_driver imx7d_adc_driver = {
547 .probe = imx7d_adc_probe,
550 .of_match_table = imx7d_adc_match,
551 .pm = pm_sleep_ptr(&imx7d_adc_pm_ops),
555 module_platform_driver(imx7d_adc_driver);
557 MODULE_AUTHOR("Haibo Chen <haibo.chen@freescale.com>");
558 MODULE_DESCRIPTION("Freescale IMX7D ADC driver");
559 MODULE_LICENSE("GPL v2");