1 // SPDX-License-Identifier: GPL-2.0-only
3 * Atmel ADC driver for SAMA5D2 devices and compatible.
5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmaengine.h>
14 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/wait.h>
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/trigger.h>
25 #include <linux/iio/trigger_consumer.h>
26 #include <linux/iio/triggered_buffer.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/regulator/consumer.h>
30 /* Control Register */
31 #define AT91_SAMA5D2_CR 0x00
33 #define AT91_SAMA5D2_CR_SWRST BIT(0)
34 /* Start Conversion */
35 #define AT91_SAMA5D2_CR_START BIT(1)
36 /* Touchscreen Calibration */
37 #define AT91_SAMA5D2_CR_TSCALIB BIT(2)
38 /* Comparison Restart */
39 #define AT91_SAMA5D2_CR_CMPRST BIT(4)
42 #define AT91_SAMA5D2_MR 0x04
43 /* Trigger Selection */
44 #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1)
46 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0
48 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1
50 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2
52 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3
53 /* PWM event line 0 */
54 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4
55 /* PWM event line 1 */
56 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5
58 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6
60 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7
62 #define AT91_SAMA5D2_MR_SLEEP BIT(5)
64 #define AT91_SAMA5D2_MR_FWUP BIT(6)
65 /* Prescaler Rate Selection */
66 #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
67 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8
68 #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff
69 #define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8)
71 #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16)
72 #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16)
74 #define AT91_SAMA5D2_MR_ANACH BIT(23)
76 #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24)
77 #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff
79 #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28)
80 #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3
81 /* Use Sequence Enable */
82 #define AT91_SAMA5D2_MR_USEQ BIT(31)
84 /* Channel Sequence Register 1 */
85 #define AT91_SAMA5D2_SEQR1 0x08
86 /* Channel Sequence Register 2 */
87 #define AT91_SAMA5D2_SEQR2 0x0c
88 /* Channel Enable Register */
89 #define AT91_SAMA5D2_CHER 0x10
90 /* Channel Disable Register */
91 #define AT91_SAMA5D2_CHDR 0x14
92 /* Channel Status Register */
93 #define AT91_SAMA5D2_CHSR 0x18
94 /* Last Converted Data Register */
95 #define AT91_SAMA5D2_LCDR 0x20
96 /* Interrupt Enable Register */
97 #define AT91_SAMA5D2_IER 0x24
98 /* Interrupt Enable Register - TS X measurement ready */
99 #define AT91_SAMA5D2_IER_XRDY BIT(20)
100 /* Interrupt Enable Register - TS Y measurement ready */
101 #define AT91_SAMA5D2_IER_YRDY BIT(21)
102 /* Interrupt Enable Register - TS pressure measurement ready */
103 #define AT91_SAMA5D2_IER_PRDY BIT(22)
104 /* Interrupt Enable Register - Data ready */
105 #define AT91_SAMA5D2_IER_DRDY BIT(24)
106 /* Interrupt Enable Register - general overrun error */
107 #define AT91_SAMA5D2_IER_GOVRE BIT(25)
108 /* Interrupt Enable Register - Pen detect */
109 #define AT91_SAMA5D2_IER_PEN BIT(29)
110 /* Interrupt Enable Register - No pen detect */
111 #define AT91_SAMA5D2_IER_NOPEN BIT(30)
112 /* Interrupt Disable Register */
113 #define AT91_SAMA5D2_IDR 0x28
114 /* Interrupt Mask Register */
115 #define AT91_SAMA5D2_IMR 0x2c
116 /* Interrupt Status Register */
117 #define AT91_SAMA5D2_ISR 0x30
118 /* Interrupt Status Register - Pen touching sense status */
119 #define AT91_SAMA5D2_ISR_PENS BIT(31)
120 /* Last Channel Trigger Mode Register */
121 #define AT91_SAMA5D2_LCTMR 0x34
122 /* Last Channel Compare Window Register */
123 #define AT91_SAMA5D2_LCCWR 0x38
124 /* Overrun Status Register */
125 #define AT91_SAMA5D2_OVER 0x3c
126 /* Extended Mode Register */
127 #define AT91_SAMA5D2_EMR 0x40
128 /* Extended Mode Register - Oversampling rate */
129 #define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16)
130 #define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16)
131 #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0
132 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1
133 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2
135 /* Extended Mode Register - Averaging on single trigger event */
136 #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20)
137 /* Compare Window Register */
138 #define AT91_SAMA5D2_CWR 0x44
139 /* Channel Gain Register */
140 #define AT91_SAMA5D2_CGR 0x48
142 /* Channel Offset Register */
143 #define AT91_SAMA5D2_COR 0x4c
144 #define AT91_SAMA5D2_COR_DIFF_OFFSET 16
146 /* Channel Data Register 0 */
147 #define AT91_SAMA5D2_CDR0 0x50
148 /* Analog Control Register */
149 #define AT91_SAMA5D2_ACR 0x94
150 /* Analog Control Register - Pen detect sensitivity mask */
151 #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0)
153 /* Touchscreen Mode Register */
154 #define AT91_SAMA5D2_TSMR 0xb0
155 /* Touchscreen Mode Register - No touch mode */
156 #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0
157 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */
158 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1
159 /* Touchscreen Mode Register - 4 wire screen, pressure measurement */
160 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2
161 /* Touchscreen Mode Register - 5 wire screen */
162 #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3
163 /* Touchscreen Mode Register - Average samples mask */
164 #define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4)
165 /* Touchscreen Mode Register - Average samples */
166 #define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4)
167 /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */
168 #define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8)
169 /* Touchscreen Mode Register - Touch/trigger frequency ratio */
170 #define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8)
171 /* Touchscreen Mode Register - Pen Debounce Time mask */
172 #define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28)
173 /* Touchscreen Mode Register - Pen Debounce Time */
174 #define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28)
175 /* Touchscreen Mode Register - No DMA for touch measurements */
176 #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22)
177 /* Touchscreen Mode Register - Disable pen detection */
178 #define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24)
179 /* Touchscreen Mode Register - Enable pen detection */
180 #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24)
182 /* Touchscreen X Position Register */
183 #define AT91_SAMA5D2_XPOSR 0xb4
184 /* Touchscreen Y Position Register */
185 #define AT91_SAMA5D2_YPOSR 0xb8
186 /* Touchscreen Pressure Register */
187 #define AT91_SAMA5D2_PRESSR 0xbc
188 /* Trigger Register */
189 #define AT91_SAMA5D2_TRGR 0xc0
190 /* Mask for TRGMOD field of TRGR register */
191 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
192 /* No trigger, only software trigger can start conversions */
193 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0
194 /* Trigger Mode external trigger rising edge */
195 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1
196 /* Trigger Mode external trigger falling edge */
197 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2
198 /* Trigger Mode external trigger any edge */
199 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3
200 /* Trigger Mode internal periodic */
201 #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5
202 /* Trigger Mode - trigger period mask */
203 #define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16)
204 /* Trigger Mode - trigger period */
205 #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16)
207 /* Correction Select Register */
208 #define AT91_SAMA5D2_COSR 0xd0
209 /* Correction Value Register */
210 #define AT91_SAMA5D2_CVR 0xd4
211 /* Channel Error Correction Register */
212 #define AT91_SAMA5D2_CECR 0xd8
213 /* Write Protection Mode Register */
214 #define AT91_SAMA5D2_WPMR 0xe4
215 /* Write Protection Status Register */
216 #define AT91_SAMA5D2_WPSR 0xe8
217 /* Version Register */
218 #define AT91_SAMA5D2_VERSION 0xfc
220 #define AT91_SAMA5D2_HW_TRIG_CNT 3
221 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12
222 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6
224 #define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
225 AT91_SAMA5D2_DIFF_CHAN_CNT + 1)
227 #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \
228 AT91_SAMA5D2_DIFF_CHAN_CNT * 2)
229 #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1)
230 #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1)
231 #define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX
233 #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
234 #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200
236 #define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0)
238 #define AT91_SAMA5D2_MAX_POS_BITS 12
241 * Maximum number of bytes to hold conversion from all channels
242 * without the timestamp.
244 #define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \
245 AT91_SAMA5D2_DIFF_CHAN_CNT) * 2)
247 /* This total must also include the timestamp */
248 #define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8)
250 #define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2)
252 #define AT91_HWFIFO_MAX_SIZE_STR "128"
253 #define AT91_HWFIFO_MAX_SIZE 128
255 /* Possible values for oversampling ratio */
256 #define AT91_OSR_1SAMPLES 1
257 #define AT91_OSR_4SAMPLES 4
258 #define AT91_OSR_16SAMPLES 16
260 #define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \
262 .type = IIO_VOLTAGE, \
271 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
272 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
273 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
274 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
275 .datasheet_name = "CH"#num, \
279 #define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \
281 .type = IIO_VOLTAGE, \
286 .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \
292 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
293 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
294 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
295 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
296 .datasheet_name = "CH"#num"-CH"#num2, \
300 #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \
302 .type = IIO_POSITIONRELATIVE, \
312 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
313 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
314 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
315 .datasheet_name = name, \
317 #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \
319 .type = IIO_PRESSURE, \
327 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
328 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
329 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
330 .datasheet_name = name, \
333 #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg)
334 #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg)
336 struct at91_adc_soc_info {
337 unsigned startup_time;
338 unsigned min_sample_rate;
339 unsigned max_sample_rate;
342 struct at91_adc_trigger {
344 unsigned int trgmod_value;
345 unsigned int edge_type;
350 * struct at91_adc_dma - at91-sama5d2 dma information struct
351 * @dma_chan: the dma channel acquired
352 * @rx_buf: dma coherent allocated area
353 * @rx_dma_buf: dma handler for the buffer
354 * @phys_addr: physical address of the ADC base register
355 * @buf_idx: index inside the dma buffer where reading was last done
356 * @rx_buf_sz: size of buffer used by DMA operation
357 * @watermark: number of conversions to copy before DMA triggers irq
358 * @dma_ts: hold the start timestamp of dma operation
360 struct at91_adc_dma {
361 struct dma_chan *dma_chan;
363 dma_addr_t rx_dma_buf;
364 phys_addr_t phys_addr;
372 * struct at91_adc_touch - at91-sama5d2 touchscreen information struct
373 * @sample_period_val: the value for periodic trigger interval
374 * @touching: is the pen touching the screen or not
375 * @x_pos: temporary placeholder for pressure computation
376 * @channels_bitmask: bitmask with the touchscreen channels enabled
377 * @workq: workqueue for buffer data pushing
379 struct at91_adc_touch {
380 u16 sample_period_val;
383 unsigned long channels_bitmask;
384 struct work_struct workq;
387 struct at91_adc_state {
391 struct regulator *reg;
392 struct regulator *vref;
394 unsigned int current_sample_rate;
395 struct iio_trigger *trig;
396 const struct at91_adc_trigger *selected_trig;
397 const struct iio_chan_spec *chan;
398 bool conversion_done;
399 u32 conversion_value;
400 unsigned int oversampling_ratio;
401 struct at91_adc_soc_info soc_info;
402 wait_queue_head_t wq_data_available;
403 struct at91_adc_dma dma_st;
404 struct at91_adc_touch touch_st;
405 struct iio_dev *indio_dev;
406 u16 buffer[AT91_BUFFER_MAX_HWORDS];
408 * lock to prevent concurrent 'single conversion' requests through
414 static const struct at91_adc_trigger at91_adc_trigger_list[] = {
416 .name = "external_rising",
417 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE,
418 .edge_type = IRQ_TYPE_EDGE_RISING,
422 .name = "external_falling",
423 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL,
424 .edge_type = IRQ_TYPE_EDGE_FALLING,
428 .name = "external_any",
429 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY,
430 .edge_type = IRQ_TYPE_EDGE_BOTH,
435 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER,
436 .edge_type = IRQ_TYPE_NONE,
441 static const struct iio_chan_spec at91_adc_channels[] = {
442 AT91_SAMA5D2_CHAN_SINGLE(0, 0x50),
443 AT91_SAMA5D2_CHAN_SINGLE(1, 0x54),
444 AT91_SAMA5D2_CHAN_SINGLE(2, 0x58),
445 AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c),
446 AT91_SAMA5D2_CHAN_SINGLE(4, 0x60),
447 AT91_SAMA5D2_CHAN_SINGLE(5, 0x64),
448 AT91_SAMA5D2_CHAN_SINGLE(6, 0x68),
449 AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c),
450 AT91_SAMA5D2_CHAN_SINGLE(8, 0x70),
451 AT91_SAMA5D2_CHAN_SINGLE(9, 0x74),
452 AT91_SAMA5D2_CHAN_SINGLE(10, 0x78),
453 AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c),
454 AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50),
455 AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58),
456 AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60),
457 AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68),
458 AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70),
459 AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78),
460 IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_TIMESTAMP_CHAN_IDX),
461 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_X_CHAN_IDX, "x", IIO_MOD_X),
462 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, "y", IIO_MOD_Y),
463 AT91_SAMA5D2_CHAN_PRESSURE(AT91_SAMA5D2_TOUCH_P_CHAN_IDX, "pressure"),
466 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
470 for (i = 0; i < indio_dev->num_channels; i++) {
471 if (indio_dev->channels[i].scan_index == chan)
477 static inline struct iio_chan_spec const *
478 at91_adc_chan_get(struct iio_dev *indio_dev, int chan)
480 int index = at91_adc_chan_xlate(indio_dev, chan);
484 return indio_dev->channels + index;
487 static inline int at91_adc_of_xlate(struct iio_dev *indio_dev,
488 const struct of_phandle_args *iiospec)
490 return at91_adc_chan_xlate(indio_dev, iiospec->args[0]);
493 static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev)
498 for_each_set_bit(bit, indio_dev->active_scan_mask,
499 indio_dev->num_channels) {
500 struct iio_chan_spec const *chan =
501 at91_adc_chan_get(indio_dev, bit);
502 mask |= BIT(chan->channel);
505 return mask & GENMASK(11, 0);
508 static void at91_adc_config_emr(struct at91_adc_state *st)
510 /* configure the extended mode register */
511 unsigned int emr = at91_adc_readl(st, AT91_SAMA5D2_EMR);
513 /* select oversampling per single trigger event */
514 emr |= AT91_SAMA5D2_EMR_ASTE(1);
516 /* delete leftover content if it's the case */
517 emr &= ~AT91_SAMA5D2_EMR_OSR_MASK;
519 /* select oversampling ratio from configuration */
520 switch (st->oversampling_ratio) {
521 case AT91_OSR_1SAMPLES:
522 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) &
523 AT91_SAMA5D2_EMR_OSR_MASK;
525 case AT91_OSR_4SAMPLES:
526 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) &
527 AT91_SAMA5D2_EMR_OSR_MASK;
529 case AT91_OSR_16SAMPLES:
530 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) &
531 AT91_SAMA5D2_EMR_OSR_MASK;
535 at91_adc_writel(st, AT91_SAMA5D2_EMR, emr);
538 static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val)
540 if (st->oversampling_ratio == AT91_OSR_1SAMPLES) {
542 * in this case we only have 12 bits of real data, but channel
543 * is registered as 14 bits, so shift left two bits
546 } else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) {
548 * in this case we have 13 bits of real data, but channel
549 * is registered as 14 bits, so left shift one bit
557 static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf,
561 u16 *buf_u16 = (u16 *) buf;
564 * We are converting each two bytes (each sample).
565 * First convert the byte based array to u16, and convert each sample
567 * Each value is two bytes in an array of chars, so to not shift
568 * more than we need, save the value separately.
569 * len is in bytes, so divide by two to get number of samples.
571 while (i < len / 2) {
573 at91_adc_adjust_val_osr(st, &val);
579 static int at91_adc_configure_touch(struct at91_adc_state *st, bool state)
581 u32 clk_khz = st->current_sample_rate / 1000;
587 /* disabling touch IRQs and setting mode to no touch enabled */
588 at91_adc_writel(st, AT91_SAMA5D2_IDR,
589 AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN);
590 at91_adc_writel(st, AT91_SAMA5D2_TSMR, 0);
594 * debounce time is in microseconds, we need it in milliseconds to
595 * multiply with kilohertz, so, divide by 1000, but after the multiply.
596 * round up to make sure pendbc is at least 1
598 pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US *
601 /* get the required exponent */
602 while (pendbc >> i++)
607 tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS;
609 tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK;
610 tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) &
611 AT91_SAMA5D2_TSMR_PENDBC_MASK;
612 tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA;
613 tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA;
614 tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK;
616 at91_adc_writel(st, AT91_SAMA5D2_TSMR, tsmr);
618 acr = at91_adc_readl(st, AT91_SAMA5D2_ACR);
619 acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK;
620 acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK;
621 at91_adc_writel(st, AT91_SAMA5D2_ACR, acr);
623 /* Sample Period Time = (TRGPER + 1) / ADCClock */
624 st->touch_st.sample_period_val =
625 round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US *
626 clk_khz / 1000) - 1, 1);
627 /* enable pen detect IRQ */
628 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
633 static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg)
636 u32 scale, result, pos;
639 * to obtain the actual position we must divide by scale
640 * and multiply with max, where
641 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1
643 /* first half of register is the x or y, second half is the scale */
644 val = at91_adc_readl(st, reg);
646 dev_dbg(&st->indio_dev->dev, "pos is 0\n");
648 pos = val & AT91_SAMA5D2_XYZ_MASK;
649 result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos;
650 scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
652 dev_err(&st->indio_dev->dev, "scale is 0\n");
660 static u16 at91_adc_touch_x_pos(struct at91_adc_state *st)
662 st->touch_st.x_pos = at91_adc_touch_pos(st, AT91_SAMA5D2_XPOSR);
663 return st->touch_st.x_pos;
666 static u16 at91_adc_touch_y_pos(struct at91_adc_state *st)
668 return at91_adc_touch_pos(st, AT91_SAMA5D2_YPOSR);
671 static u16 at91_adc_touch_pressure(struct at91_adc_state *st)
679 /* calculate the pressure */
680 val = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
681 z1 = val & AT91_SAMA5D2_XYZ_MASK;
682 z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
685 pres = rxp * (st->touch_st.x_pos * factor / 1024) *
686 (z2 * factor / z1 - factor) /
689 pres = 0xFFFF; /* no pen contact */
692 * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0.
693 * We compute it this way, but let's return it in the expected way,
694 * growing from 0 to 0xFFFF.
696 return 0xFFFF - pres;
699 static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val)
702 if (!st->touch_st.touching)
704 if (chan == AT91_SAMA5D2_TOUCH_X_CHAN_IDX)
705 *val = at91_adc_touch_x_pos(st);
706 else if (chan == AT91_SAMA5D2_TOUCH_Y_CHAN_IDX)
707 *val = at91_adc_touch_y_pos(st);
714 static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val)
717 if (!st->touch_st.touching)
719 if (chan == AT91_SAMA5D2_TOUCH_P_CHAN_IDX)
720 *val = at91_adc_touch_pressure(st);
727 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
729 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
730 struct at91_adc_state *st = iio_priv(indio);
731 u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR);
734 status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
737 status |= st->selected_trig->trgmod_value;
739 /* set/unset hw trigger */
740 at91_adc_writel(st, AT91_SAMA5D2_TRGR, status);
745 static int at91_adc_reenable_trigger(struct iio_trigger *trig)
747 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
748 struct at91_adc_state *st = iio_priv(indio);
750 /* if we are using DMA, we must not reenable irq after each trigger */
751 if (st->dma_st.dma_chan)
756 /* Needed to ACK the DRDY interruption */
757 at91_adc_readl(st, AT91_SAMA5D2_LCDR);
762 static const struct iio_trigger_ops at91_adc_trigger_ops = {
763 .set_trigger_state = &at91_adc_configure_trigger,
764 .try_reenable = &at91_adc_reenable_trigger,
765 .validate_device = iio_trigger_validate_own_device,
768 static int at91_adc_dma_size_done(struct at91_adc_state *st)
770 struct dma_tx_state state;
771 enum dma_status status;
774 status = dmaengine_tx_status(st->dma_st.dma_chan,
775 st->dma_st.dma_chan->cookie,
777 if (status != DMA_IN_PROGRESS)
780 /* Transferred length is size in bytes from end of buffer */
781 i = st->dma_st.rx_buf_sz - state.residue;
783 /* Return available bytes */
784 if (i >= st->dma_st.buf_idx)
785 size = i - st->dma_st.buf_idx;
787 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx;
791 static void at91_dma_buffer_done(void *data)
793 struct iio_dev *indio_dev = data;
795 iio_trigger_poll_chained(indio_dev->trig);
798 static int at91_adc_dma_start(struct iio_dev *indio_dev)
800 struct at91_adc_state *st = iio_priv(indio_dev);
801 struct dma_async_tx_descriptor *desc;
806 if (!st->dma_st.dma_chan)
809 /* we start a new DMA, so set buffer index to start */
810 st->dma_st.buf_idx = 0;
813 * compute buffer size w.r.t. watermark and enabled channels.
814 * scan_bytes is aligned so we need an exact size for DMA
816 st->dma_st.rx_buf_sz = 0;
818 for_each_set_bit(bit, indio_dev->active_scan_mask,
819 indio_dev->num_channels) {
820 struct iio_chan_spec const *chan =
821 at91_adc_chan_get(indio_dev, bit);
826 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8;
828 st->dma_st.rx_buf_sz *= st->dma_st.watermark;
830 /* Prepare a DMA cyclic transaction */
831 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan,
832 st->dma_st.rx_dma_buf,
833 st->dma_st.rx_buf_sz,
834 st->dma_st.rx_buf_sz / 2,
835 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
838 dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n");
842 desc->callback = at91_dma_buffer_done;
843 desc->callback_param = indio_dev;
845 cookie = dmaengine_submit(desc);
846 ret = dma_submit_error(cookie);
848 dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n");
849 dmaengine_terminate_async(st->dma_st.dma_chan);
853 /* enable general overrun error signaling */
854 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_GOVRE);
855 /* Issue pending DMA requests */
856 dma_async_issue_pending(st->dma_st.dma_chan);
858 /* consider current time as DMA start time for timestamps */
859 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
861 dev_dbg(&indio_dev->dev, "DMA cyclic started\n");
866 static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio,
867 struct at91_adc_state *st)
869 /* if using DMA, we do not use our own IRQ (we use DMA-controller) */
870 if (st->dma_st.dma_chan)
872 /* if the trigger is not ours, then it has its own IRQ */
873 if (iio_trigger_validate_own_device(indio->trig, indio))
878 static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev)
880 struct at91_adc_state *st = iio_priv(indio_dev);
882 return !!bitmap_subset(indio_dev->active_scan_mask,
883 &st->touch_st.channels_bitmask,
884 AT91_SAMA5D2_MAX_CHAN_IDX + 1);
887 static int at91_adc_buffer_prepare(struct iio_dev *indio_dev)
891 struct at91_adc_state *st = iio_priv(indio_dev);
893 /* check if we are enabling triggered buffer or the touchscreen */
894 if (at91_adc_current_chan_is_touch(indio_dev))
895 return at91_adc_configure_touch(st, true);
897 /* if we are not in triggered mode, we cannot enable the buffer. */
898 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
901 /* we continue with the triggered buffer */
902 ret = at91_adc_dma_start(indio_dev);
904 dev_err(&indio_dev->dev, "buffer prepare failed\n");
908 for_each_set_bit(bit, indio_dev->active_scan_mask,
909 indio_dev->num_channels) {
910 struct iio_chan_spec const *chan =
911 at91_adc_chan_get(indio_dev, bit);
916 /* these channel types cannot be handled by this trigger */
917 if (chan->type == IIO_POSITIONRELATIVE ||
918 chan->type == IIO_PRESSURE)
921 cor = at91_adc_readl(st, AT91_SAMA5D2_COR);
923 if (chan->differential)
924 cor |= (BIT(chan->channel) | BIT(chan->channel2)) <<
925 AT91_SAMA5D2_COR_DIFF_OFFSET;
927 cor &= ~(BIT(chan->channel) <<
928 AT91_SAMA5D2_COR_DIFF_OFFSET);
930 at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
932 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
935 if (at91_adc_buffer_check_use_irq(indio_dev, st))
936 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_DRDY);
941 static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev)
943 struct at91_adc_state *st = iio_priv(indio_dev);
946 /* check if we are disabling triggered buffer or the touchscreen */
947 if (at91_adc_current_chan_is_touch(indio_dev))
948 return at91_adc_configure_touch(st, false);
950 /* if we are not in triggered mode, nothing to do here */
951 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
955 * For each enable channel we must disable it in hardware.
956 * In the case of DMA, we must read the last converted value
957 * to clear EOC status and not get a possible interrupt later.
958 * This value is being read by DMA from LCDR anyway, so it's not lost.
960 for_each_set_bit(bit, indio_dev->active_scan_mask,
961 indio_dev->num_channels) {
962 struct iio_chan_spec const *chan =
963 at91_adc_chan_get(indio_dev, bit);
967 /* these channel types are virtual, no need to do anything */
968 if (chan->type == IIO_POSITIONRELATIVE ||
969 chan->type == IIO_PRESSURE)
972 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
974 if (st->dma_st.dma_chan)
975 at91_adc_readl(st, chan->address);
978 if (at91_adc_buffer_check_use_irq(indio_dev, st))
979 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_DRDY);
981 /* read overflow register to clear possible overflow status */
982 at91_adc_readl(st, AT91_SAMA5D2_OVER);
984 /* if we are using DMA we must clear registers and end DMA */
985 if (st->dma_st.dma_chan)
986 dmaengine_terminate_sync(st->dma_st.dma_chan);
991 static const struct iio_buffer_setup_ops at91_buffer_setup_ops = {
992 .postdisable = &at91_adc_buffer_postdisable,
995 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio,
998 struct iio_trigger *trig;
1001 trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name,
1002 indio->id, trigger_name);
1006 trig->dev.parent = indio->dev.parent;
1007 iio_trigger_set_drvdata(trig, indio);
1008 trig->ops = &at91_adc_trigger_ops;
1010 ret = devm_iio_trigger_register(&indio->dev, trig);
1012 return ERR_PTR(ret);
1016 static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev,
1017 struct iio_poll_func *pf)
1019 struct at91_adc_state *st = iio_priv(indio_dev);
1023 u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev);
1024 unsigned int timeout = 50;
1027 * Check if the conversion is ready. If not, wait a little bit, and
1028 * in case of timeout exit with an error.
1030 while ((at91_adc_readl(st, AT91_SAMA5D2_ISR) & mask) != mask &&
1032 usleep_range(50, 100);
1036 /* Cannot read data, not ready. Continue without reporting data */
1040 for_each_set_bit(bit, indio_dev->active_scan_mask,
1041 indio_dev->num_channels) {
1042 struct iio_chan_spec const *chan =
1043 at91_adc_chan_get(indio_dev, bit);
1048 * Our external trigger only supports the voltage channels.
1049 * In case someone requested a different type of channel
1050 * just put zeroes to buffer.
1051 * This should not happen because we check the scan mode
1052 * and scan mask when we enable the buffer, and we don't allow
1053 * the buffer to start with a mixed mask (voltage and something
1055 * Thus, emit a warning.
1057 if (chan->type == IIO_VOLTAGE) {
1058 val = at91_adc_readl(st, chan->address);
1059 at91_adc_adjust_val_osr(st, &val);
1060 st->buffer[i] = val;
1063 WARN(true, "This trigger cannot handle this type of channel");
1067 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer,
1071 static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev)
1073 struct at91_adc_state *st = iio_priv(indio_dev);
1074 int transferred_len = at91_adc_dma_size_done(st);
1075 s64 ns = iio_get_time_ns(indio_dev);
1077 int sample_index = 0, sample_count, sample_size;
1079 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
1080 /* if we reached this point, we cannot sample faster */
1081 if (status & AT91_SAMA5D2_IER_GOVRE)
1082 pr_info_ratelimited("%s: conversion overrun detected\n",
1085 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark);
1087 sample_count = div_s64(transferred_len, sample_size);
1090 * interval between samples is total time since last transfer handling
1091 * divided by the number of samples (total size divided by sample size)
1093 interval = div_s64((ns - st->dma_st.dma_ts), sample_count);
1095 while (transferred_len >= sample_size) {
1097 * for all the values in the current sample,
1098 * adjust the values inside the buffer for oversampling
1100 at91_adc_adjust_val_osr_array(st,
1101 &st->dma_st.rx_buf[st->dma_st.buf_idx],
1104 iio_push_to_buffers_with_timestamp(indio_dev,
1105 (st->dma_st.rx_buf + st->dma_st.buf_idx),
1106 (st->dma_st.dma_ts + interval * sample_index));
1107 /* adjust remaining length */
1108 transferred_len -= sample_size;
1109 /* adjust buffer index */
1110 st->dma_st.buf_idx += sample_size;
1111 /* in case of reaching end of buffer, reset index */
1112 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz)
1113 st->dma_st.buf_idx = 0;
1116 /* adjust saved time for next transfer handling */
1117 st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
1120 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
1122 struct iio_poll_func *pf = p;
1123 struct iio_dev *indio_dev = pf->indio_dev;
1124 struct at91_adc_state *st = iio_priv(indio_dev);
1127 * If it's not our trigger, start a conversion now, as we are
1128 * actually polling the trigger now.
1130 if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev))
1131 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
1133 if (st->dma_st.dma_chan)
1134 at91_adc_trigger_handler_dma(indio_dev);
1136 at91_adc_trigger_handler_nodma(indio_dev, pf);
1138 iio_trigger_notify_done(indio_dev->trig);
1143 static unsigned at91_adc_startup_time(unsigned startup_time_min,
1144 unsigned adc_clk_khz)
1146 static const unsigned int startup_lookup[] = {
1152 unsigned ticks_min, i;
1155 * Since the adc frequency is checked before, there is no reason
1156 * to not meet the startup time constraint.
1159 ticks_min = startup_time_min * adc_clk_khz / 1000;
1160 for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
1161 if (startup_lookup[i] > ticks_min)
1167 static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq)
1169 struct at91_adc_state *st = iio_priv(indio_dev);
1170 unsigned f_per, prescal, startup, mr;
1172 f_per = clk_get_rate(st->per_clk);
1173 prescal = (f_per / (2 * freq)) - 1;
1175 startup = at91_adc_startup_time(st->soc_info.startup_time,
1178 mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
1179 mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
1180 mr |= AT91_SAMA5D2_MR_STARTUP(startup);
1181 mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
1182 at91_adc_writel(st, AT91_SAMA5D2_MR, mr);
1184 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n",
1185 freq, startup, prescal);
1186 st->current_sample_rate = freq;
1189 static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
1191 return st->current_sample_rate;
1194 static void at91_adc_touch_data_handler(struct iio_dev *indio_dev)
1196 struct at91_adc_state *st = iio_priv(indio_dev);
1201 for_each_set_bit(bit, indio_dev->active_scan_mask,
1202 AT91_SAMA5D2_MAX_CHAN_IDX + 1) {
1203 struct iio_chan_spec const *chan =
1204 at91_adc_chan_get(indio_dev, bit);
1206 if (chan->type == IIO_POSITIONRELATIVE)
1207 at91_adc_read_position(st, chan->channel, &val);
1208 else if (chan->type == IIO_PRESSURE)
1209 at91_adc_read_pressure(st, chan->channel, &val);
1212 st->buffer[i] = val;
1216 * Schedule work to push to buffers.
1217 * This is intended to push to the callback buffer that another driver
1218 * registered. We are still in a handler from our IRQ. If we push
1219 * directly, it means the other driver has it's callback called
1220 * from our IRQ context. Which is something we better avoid.
1221 * Let's schedule it after our IRQ is completed.
1223 schedule_work(&st->touch_st.workq);
1226 static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st)
1228 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_PEN);
1229 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_NOPEN |
1230 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1231 AT91_SAMA5D2_IER_PRDY);
1232 at91_adc_writel(st, AT91_SAMA5D2_TRGR,
1233 AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC |
1234 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val));
1235 st->touch_st.touching = true;
1238 static void at91_adc_no_pen_detect_interrupt(struct iio_dev *indio_dev)
1240 struct at91_adc_state *st = iio_priv(indio_dev);
1242 at91_adc_writel(st, AT91_SAMA5D2_TRGR,
1243 AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER);
1244 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_NOPEN |
1245 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1246 AT91_SAMA5D2_IER_PRDY);
1247 st->touch_st.touching = false;
1249 at91_adc_touch_data_handler(indio_dev);
1251 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN);
1254 static void at91_adc_workq_handler(struct work_struct *workq)
1256 struct at91_adc_touch *touch_st = container_of(workq,
1257 struct at91_adc_touch, workq);
1258 struct at91_adc_state *st = container_of(touch_st,
1259 struct at91_adc_state, touch_st);
1260 struct iio_dev *indio_dev = st->indio_dev;
1262 iio_push_to_buffers(indio_dev, st->buffer);
1265 static irqreturn_t at91_adc_interrupt(int irq, void *private)
1267 struct iio_dev *indio = private;
1268 struct at91_adc_state *st = iio_priv(indio);
1269 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
1270 u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR);
1271 u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1272 AT91_SAMA5D2_IER_PRDY;
1274 if (!(status & imr))
1276 if (status & AT91_SAMA5D2_IER_PEN) {
1277 /* pen detected IRQ */
1278 at91_adc_pen_detect_interrupt(st);
1279 } else if ((status & AT91_SAMA5D2_IER_NOPEN)) {
1280 /* nopen detected IRQ */
1281 at91_adc_no_pen_detect_interrupt(indio);
1282 } else if ((status & AT91_SAMA5D2_ISR_PENS) &&
1283 ((status & rdy_mask) == rdy_mask)) {
1284 /* periodic trigger IRQ - during pen sense */
1285 at91_adc_touch_data_handler(indio);
1286 } else if (status & AT91_SAMA5D2_ISR_PENS) {
1288 * touching, but the measurements are not ready yet.
1291 status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR);
1292 status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR);
1293 status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR);
1294 } else if (iio_buffer_enabled(indio) &&
1295 (status & AT91_SAMA5D2_IER_DRDY)) {
1296 /* triggered buffer without DMA */
1297 disable_irq_nosync(irq);
1298 iio_trigger_poll(indio->trig);
1299 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) {
1300 /* triggered buffer with DMA - should not happen */
1301 disable_irq_nosync(irq);
1302 WARN(true, "Unexpected irq occurred\n");
1303 } else if (!iio_buffer_enabled(indio)) {
1304 /* software requested conversion */
1305 st->conversion_value = at91_adc_readl(st, st->chan->address);
1306 st->conversion_done = true;
1307 wake_up_interruptible(&st->wq_data_available);
1312 static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
1313 struct iio_chan_spec const *chan, int *val)
1315 struct at91_adc_state *st = iio_priv(indio_dev);
1321 * Keep in mind that we cannot use software trigger or touchscreen
1322 * if external trigger is enabled
1324 if (chan->type == IIO_POSITIONRELATIVE) {
1325 ret = iio_device_claim_direct_mode(indio_dev);
1328 mutex_lock(&st->lock);
1330 ret = at91_adc_read_position(st, chan->channel,
1333 mutex_unlock(&st->lock);
1334 iio_device_release_direct_mode(indio_dev);
1336 return at91_adc_adjust_val_osr(st, val);
1338 if (chan->type == IIO_PRESSURE) {
1339 ret = iio_device_claim_direct_mode(indio_dev);
1342 mutex_lock(&st->lock);
1344 ret = at91_adc_read_pressure(st, chan->channel,
1347 mutex_unlock(&st->lock);
1348 iio_device_release_direct_mode(indio_dev);
1350 return at91_adc_adjust_val_osr(st, val);
1353 /* in this case we have a voltage channel */
1355 ret = iio_device_claim_direct_mode(indio_dev);
1358 mutex_lock(&st->lock);
1362 if (chan->differential)
1363 cor = (BIT(chan->channel) | BIT(chan->channel2)) <<
1364 AT91_SAMA5D2_COR_DIFF_OFFSET;
1366 at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
1367 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
1368 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel));
1369 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
1371 ret = wait_event_interruptible_timeout(st->wq_data_available,
1372 st->conversion_done,
1373 msecs_to_jiffies(1000));
1378 *val = st->conversion_value;
1379 ret = at91_adc_adjust_val_osr(st, val);
1380 if (chan->scan_type.sign == 's')
1381 *val = sign_extend32(*val, 11);
1382 st->conversion_done = false;
1385 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel));
1386 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
1388 /* Needed to ACK the DRDY interruption */
1389 at91_adc_readl(st, AT91_SAMA5D2_LCDR);
1391 mutex_unlock(&st->lock);
1393 iio_device_release_direct_mode(indio_dev);
1397 static int at91_adc_read_raw(struct iio_dev *indio_dev,
1398 struct iio_chan_spec const *chan,
1399 int *val, int *val2, long mask)
1401 struct at91_adc_state *st = iio_priv(indio_dev);
1404 case IIO_CHAN_INFO_RAW:
1405 return at91_adc_read_info_raw(indio_dev, chan, val);
1406 case IIO_CHAN_INFO_SCALE:
1407 *val = st->vref_uv / 1000;
1408 if (chan->differential)
1410 *val2 = chan->scan_type.realbits;
1411 return IIO_VAL_FRACTIONAL_LOG2;
1413 case IIO_CHAN_INFO_SAMP_FREQ:
1414 *val = at91_adc_get_sample_freq(st);
1417 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1418 *val = st->oversampling_ratio;
1426 static int at91_adc_write_raw(struct iio_dev *indio_dev,
1427 struct iio_chan_spec const *chan,
1428 int val, int val2, long mask)
1430 struct at91_adc_state *st = iio_priv(indio_dev);
1433 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1434 if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) &&
1435 (val != AT91_OSR_16SAMPLES))
1437 /* if no change, optimize out */
1438 if (val == st->oversampling_ratio)
1440 st->oversampling_ratio = val;
1442 at91_adc_config_emr(st);
1444 case IIO_CHAN_INFO_SAMP_FREQ:
1445 if (val < st->soc_info.min_sample_rate ||
1446 val > st->soc_info.max_sample_rate)
1449 at91_adc_setup_samp_freq(indio_dev, val);
1456 static void at91_adc_dma_init(struct platform_device *pdev)
1458 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1459 struct at91_adc_state *st = iio_priv(indio_dev);
1460 struct dma_slave_config config = {0};
1462 * We make the buffer double the size of the fifo,
1463 * such that DMA uses one half of the buffer (full fifo size)
1464 * and the software uses the other half to read/write.
1466 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
1467 AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
1470 if (st->dma_st.dma_chan)
1473 st->dma_st.dma_chan = dma_request_chan(&pdev->dev, "rx");
1474 if (IS_ERR(st->dma_st.dma_chan)) {
1475 dev_info(&pdev->dev, "can't get DMA channel\n");
1476 st->dma_st.dma_chan = NULL;
1480 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev,
1482 &st->dma_st.rx_dma_buf,
1484 if (!st->dma_st.rx_buf) {
1485 dev_info(&pdev->dev, "can't allocate coherent DMA area\n");
1486 goto dma_chan_disable;
1489 /* Configure DMA channel to read data register */
1490 config.direction = DMA_DEV_TO_MEM;
1491 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr
1492 + AT91_SAMA5D2_LCDR);
1493 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1494 config.src_maxburst = 1;
1495 config.dst_maxburst = 1;
1497 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) {
1498 dev_info(&pdev->dev, "can't configure DMA slave\n");
1502 dev_info(&pdev->dev, "using %s for rx DMA transfers\n",
1503 dma_chan_name(st->dma_st.dma_chan));
1508 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
1509 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
1511 dma_release_channel(st->dma_st.dma_chan);
1512 st->dma_st.dma_chan = NULL;
1514 dev_info(&pdev->dev, "continuing without DMA support\n");
1517 static void at91_adc_dma_disable(struct platform_device *pdev)
1519 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1520 struct at91_adc_state *st = iio_priv(indio_dev);
1521 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
1522 AT91_BUFFER_MAX_CONVERSION_BYTES * 2,
1525 /* if we are not using DMA, just return */
1526 if (!st->dma_st.dma_chan)
1529 /* wait for all transactions to be terminated first*/
1530 dmaengine_terminate_sync(st->dma_st.dma_chan);
1532 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
1533 st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
1534 dma_release_channel(st->dma_st.dma_chan);
1535 st->dma_st.dma_chan = NULL;
1537 dev_info(&pdev->dev, "continuing without DMA support\n");
1540 static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1542 struct at91_adc_state *st = iio_priv(indio_dev);
1545 if (val > AT91_HWFIFO_MAX_SIZE)
1548 if (!st->selected_trig->hw_trig) {
1549 dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n");
1553 dev_dbg(&indio_dev->dev, "new watermark is %u\n", val);
1554 st->dma_st.watermark = val;
1557 * The logic here is: if we have watermark 1, it means we do
1558 * each conversion with it's own IRQ, thus we don't need DMA.
1559 * If the watermark is higher, we do DMA to do all the transfers in bulk
1563 at91_adc_dma_disable(to_platform_device(&indio_dev->dev));
1565 at91_adc_dma_init(to_platform_device(&indio_dev->dev));
1568 * We can start the DMA only after setting the watermark and
1569 * having the DMA initialization completed
1571 ret = at91_adc_buffer_prepare(indio_dev);
1573 at91_adc_dma_disable(to_platform_device(&indio_dev->dev));
1578 static int at91_adc_update_scan_mode(struct iio_dev *indio_dev,
1579 const unsigned long *scan_mask)
1581 struct at91_adc_state *st = iio_priv(indio_dev);
1583 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask,
1584 AT91_SAMA5D2_MAX_CHAN_IDX + 1))
1587 * if the new bitmap is a combination of touchscreen and regular
1588 * channels, then we are not fine
1590 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask,
1591 AT91_SAMA5D2_MAX_CHAN_IDX + 1))
1596 static void at91_adc_hw_init(struct iio_dev *indio_dev)
1598 struct at91_adc_state *st = iio_priv(indio_dev);
1600 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
1601 at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff);
1603 * Transfer field must be set to 2 according to the datasheet and
1604 * allows different analog settings for each channel.
1606 at91_adc_writel(st, AT91_SAMA5D2_MR,
1607 AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
1609 at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate);
1611 /* configure extended mode register */
1612 at91_adc_config_emr(st);
1615 static ssize_t at91_adc_get_fifo_state(struct device *dev,
1616 struct device_attribute *attr, char *buf)
1618 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1619 struct at91_adc_state *st = iio_priv(indio_dev);
1621 return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan);
1624 static ssize_t at91_adc_get_watermark(struct device *dev,
1625 struct device_attribute *attr, char *buf)
1627 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1628 struct at91_adc_state *st = iio_priv(indio_dev);
1630 return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark);
1633 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1634 at91_adc_get_fifo_state, NULL, 0);
1635 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1636 at91_adc_get_watermark, NULL, 0);
1638 static IIO_CONST_ATTR(hwfifo_watermark_min, "2");
1639 static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR);
1641 static IIO_CONST_ATTR(oversampling_ratio_available,
1642 __stringify(AT91_OSR_1SAMPLES) " "
1643 __stringify(AT91_OSR_4SAMPLES) " "
1644 __stringify(AT91_OSR_16SAMPLES));
1646 static struct attribute *at91_adc_attributes[] = {
1647 &iio_const_attr_oversampling_ratio_available.dev_attr.attr,
1651 static const struct attribute_group at91_adc_attribute_group = {
1652 .attrs = at91_adc_attributes,
1655 static const struct attribute *at91_adc_fifo_attributes[] = {
1656 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
1657 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
1658 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
1659 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
1663 static const struct iio_info at91_adc_info = {
1664 .attrs = &at91_adc_attribute_group,
1665 .read_raw = &at91_adc_read_raw,
1666 .write_raw = &at91_adc_write_raw,
1667 .update_scan_mode = &at91_adc_update_scan_mode,
1668 .of_xlate = &at91_adc_of_xlate,
1669 .hwfifo_set_watermark = &at91_adc_set_watermark,
1672 static int at91_adc_buffer_and_trigger_init(struct device *dev,
1673 struct iio_dev *indio)
1675 struct at91_adc_state *st = iio_priv(indio);
1676 const struct attribute **fifo_attrs;
1679 if (st->selected_trig->hw_trig)
1680 fifo_attrs = at91_adc_fifo_attributes;
1684 ret = devm_iio_triggered_buffer_setup_ext(&indio->dev, indio,
1685 &iio_pollfunc_store_time,
1686 &at91_adc_trigger_handler, &at91_buffer_setup_ops, fifo_attrs);
1688 dev_err(dev, "couldn't initialize the buffer.\n");
1692 if (!st->selected_trig->hw_trig)
1695 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
1696 if (IS_ERR(st->trig)) {
1697 dev_err(dev, "could not allocate trigger\n");
1698 return PTR_ERR(st->trig);
1702 * Initially the iio buffer has a length of 2 and
1705 st->dma_st.watermark = 1;
1710 static int at91_adc_probe(struct platform_device *pdev)
1712 struct iio_dev *indio_dev;
1713 struct at91_adc_state *st;
1714 struct resource *res;
1716 u32 edge_type = IRQ_TYPE_NONE;
1718 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
1722 indio_dev->name = dev_name(&pdev->dev);
1723 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
1724 indio_dev->info = &at91_adc_info;
1725 indio_dev->channels = at91_adc_channels;
1726 indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels);
1728 st = iio_priv(indio_dev);
1729 st->indio_dev = indio_dev;
1731 bitmap_set(&st->touch_st.channels_bitmask,
1732 AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 1);
1733 bitmap_set(&st->touch_st.channels_bitmask,
1734 AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 1);
1735 bitmap_set(&st->touch_st.channels_bitmask,
1736 AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 1);
1738 st->oversampling_ratio = AT91_OSR_1SAMPLES;
1740 ret = of_property_read_u32(pdev->dev.of_node,
1741 "atmel,min-sample-rate-hz",
1742 &st->soc_info.min_sample_rate);
1745 "invalid or missing value for atmel,min-sample-rate-hz\n");
1749 ret = of_property_read_u32(pdev->dev.of_node,
1750 "atmel,max-sample-rate-hz",
1751 &st->soc_info.max_sample_rate);
1754 "invalid or missing value for atmel,max-sample-rate-hz\n");
1758 ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms",
1759 &st->soc_info.startup_time);
1762 "invalid or missing value for atmel,startup-time-ms\n");
1766 ret = of_property_read_u32(pdev->dev.of_node,
1767 "atmel,trigger-edge-type", &edge_type);
1770 "atmel,trigger-edge-type not specified, only software trigger available\n");
1773 st->selected_trig = NULL;
1775 /* find the right trigger, or no trigger at all */
1776 for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT + 1; i++)
1777 if (at91_adc_trigger_list[i].edge_type == edge_type) {
1778 st->selected_trig = &at91_adc_trigger_list[i];
1782 if (!st->selected_trig) {
1783 dev_err(&pdev->dev, "invalid external trigger edge value\n");
1787 init_waitqueue_head(&st->wq_data_available);
1788 mutex_init(&st->lock);
1789 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler);
1791 st->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1792 if (IS_ERR(st->base))
1793 return PTR_ERR(st->base);
1795 /* if we plan to use DMA, we need the physical address of the regs */
1796 st->dma_st.phys_addr = res->start;
1798 st->irq = platform_get_irq(pdev, 0);
1806 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
1807 if (IS_ERR(st->per_clk))
1808 return PTR_ERR(st->per_clk);
1810 st->reg = devm_regulator_get(&pdev->dev, "vddana");
1811 if (IS_ERR(st->reg))
1812 return PTR_ERR(st->reg);
1814 st->vref = devm_regulator_get(&pdev->dev, "vref");
1815 if (IS_ERR(st->vref))
1816 return PTR_ERR(st->vref);
1818 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
1819 pdev->dev.driver->name, indio_dev);
1823 ret = regulator_enable(st->reg);
1827 ret = regulator_enable(st->vref);
1831 st->vref_uv = regulator_get_voltage(st->vref);
1832 if (st->vref_uv <= 0) {
1837 at91_adc_hw_init(indio_dev);
1839 ret = clk_prepare_enable(st->per_clk);
1843 platform_set_drvdata(pdev, indio_dev);
1845 ret = at91_adc_buffer_and_trigger_init(&pdev->dev, indio_dev);
1847 goto per_clk_disable_unprepare;
1849 if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32)))
1850 dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n");
1852 ret = iio_device_register(indio_dev);
1856 if (st->selected_trig->hw_trig)
1857 dev_info(&pdev->dev, "setting up trigger as %s\n",
1858 st->selected_trig->name);
1860 dev_info(&pdev->dev, "version: %x\n",
1861 readl_relaxed(st->base + AT91_SAMA5D2_VERSION));
1866 at91_adc_dma_disable(pdev);
1867 per_clk_disable_unprepare:
1868 clk_disable_unprepare(st->per_clk);
1870 regulator_disable(st->vref);
1872 regulator_disable(st->reg);
1876 static int at91_adc_remove(struct platform_device *pdev)
1878 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1879 struct at91_adc_state *st = iio_priv(indio_dev);
1881 iio_device_unregister(indio_dev);
1883 at91_adc_dma_disable(pdev);
1885 clk_disable_unprepare(st->per_clk);
1887 regulator_disable(st->vref);
1888 regulator_disable(st->reg);
1893 static __maybe_unused int at91_adc_suspend(struct device *dev)
1895 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1896 struct at91_adc_state *st = iio_priv(indio_dev);
1899 * Do a sofware reset of the ADC before we go to suspend.
1900 * this will ensure that all pins are free from being muxed by the ADC
1901 * and can be used by for other devices.
1902 * Otherwise, ADC will hog them and we can't go to suspend mode.
1904 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
1906 clk_disable_unprepare(st->per_clk);
1907 regulator_disable(st->vref);
1908 regulator_disable(st->reg);
1910 return pinctrl_pm_select_sleep_state(dev);
1913 static __maybe_unused int at91_adc_resume(struct device *dev)
1915 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1916 struct at91_adc_state *st = iio_priv(indio_dev);
1919 ret = pinctrl_pm_select_default_state(dev);
1923 ret = regulator_enable(st->reg);
1927 ret = regulator_enable(st->vref);
1929 goto reg_disable_resume;
1931 ret = clk_prepare_enable(st->per_clk);
1933 goto vref_disable_resume;
1935 at91_adc_hw_init(indio_dev);
1937 /* reconfiguring trigger hardware state */
1938 if (!iio_buffer_enabled(indio_dev))
1941 /* check if we are enabling triggered buffer or the touchscreen */
1942 if (at91_adc_current_chan_is_touch(indio_dev))
1943 return at91_adc_configure_touch(st, true);
1945 return at91_adc_configure_trigger(st->trig, true);
1947 /* not needed but more explicit */
1950 vref_disable_resume:
1951 regulator_disable(st->vref);
1953 regulator_disable(st->reg);
1955 dev_err(&indio_dev->dev, "failed to resume\n");
1959 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
1961 static const struct of_device_id at91_adc_dt_match[] = {
1963 .compatible = "atmel,sama5d2-adc",
1968 MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
1970 static struct platform_driver at91_adc_driver = {
1971 .probe = at91_adc_probe,
1972 .remove = at91_adc_remove,
1974 .name = "at91-sama5d2_adc",
1975 .of_match_table = at91_adc_dt_match,
1976 .pm = &at91_adc_pm_ops,
1979 module_platform_driver(at91_adc_driver)
1981 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
1982 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
1983 MODULE_LICENSE("GPL v2");