1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aspeed AST2400/2500/2600 ADC
5 * Copyright (C) 2017 Google, Inc.
6 * Copyright (C) 2021 Aspeed Technology Inc.
10 * clock period = period of PCLK * 2 * (ADC0C[31:17] + 1) * (ADC0C[9:0] + 1)
12 * clock period = period of PCLK * 2 * (ADC0C[15:0] + 1)
15 #include <linux/clk.h>
16 #include <linux/clk-provider.h>
17 #include <linux/err.h>
18 #include <linux/errno.h>
20 #include <linux/module.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/reset.h>
25 #include <linux/spinlock.h>
26 #include <linux/types.h>
27 #include <linux/bitfield.h>
28 #include <linux/regmap.h>
29 #include <linux/mfd/syscon.h>
31 #include <linux/iio/iio.h>
32 #include <linux/iio/driver.h>
33 #include <linux/iopoll.h>
35 #define ASPEED_RESOLUTION_BITS 10
36 #define ASPEED_CLOCKS_PER_SAMPLE 12
38 #define ASPEED_REG_ENGINE_CONTROL 0x00
39 #define ASPEED_REG_INTERRUPT_CONTROL 0x04
40 #define ASPEED_REG_VGA_DETECT_CONTROL 0x08
41 #define ASPEED_REG_CLOCK_CONTROL 0x0C
42 #define ASPEED_REG_COMPENSATION_TRIM 0xC4
44 * The register offset between 0xC8~0xCC can be read and won't affect the
45 * hardware logic in each version of ADC.
47 #define ASPEED_REG_MAX 0xD0
49 #define ASPEED_ADC_ENGINE_ENABLE BIT(0)
50 #define ASPEED_ADC_OP_MODE GENMASK(3, 1)
51 #define ASPEED_ADC_OP_MODE_PWR_DOWN 0
52 #define ASPEED_ADC_OP_MODE_STANDBY 1
53 #define ASPEED_ADC_OP_MODE_NORMAL 7
54 #define ASPEED_ADC_CTRL_COMPENSATION BIT(4)
55 #define ASPEED_ADC_AUTO_COMPENSATION BIT(5)
57 * Bit 6 determines not only the reference voltage range but also the dividing
58 * circuit for battery sensing.
60 #define ASPEED_ADC_REF_VOLTAGE GENMASK(7, 6)
61 #define ASPEED_ADC_REF_VOLTAGE_2500mV 0
62 #define ASPEED_ADC_REF_VOLTAGE_1200mV 1
63 #define ASPEED_ADC_REF_VOLTAGE_EXT_HIGH 2
64 #define ASPEED_ADC_REF_VOLTAGE_EXT_LOW 3
65 #define ASPEED_ADC_BAT_SENSING_DIV BIT(6)
66 #define ASPEED_ADC_BAT_SENSING_DIV_2_3 0
67 #define ASPEED_ADC_BAT_SENSING_DIV_1_3 1
68 #define ASPEED_ADC_CTRL_INIT_RDY BIT(8)
69 #define ASPEED_ADC_CH7_MODE BIT(12)
70 #define ASPEED_ADC_CH7_NORMAL 0
71 #define ASPEED_ADC_CH7_BAT 1
72 #define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13)
73 #define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16)
74 #define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch))
76 #define ASPEED_ADC_INIT_POLLING_TIME 500
77 #define ASPEED_ADC_INIT_TIMEOUT 500000
79 * When the sampling rate is too high, the ADC may not have enough charging
80 * time, resulting in a low voltage value. Thus, the default uses a slow
81 * sampling rate for most use cases.
83 #define ASPEED_ADC_DEF_SAMPLING_RATE 65000
85 struct aspeed_adc_trim_locate {
86 const unsigned int offset;
87 const unsigned int field;
90 struct aspeed_adc_model_data {
91 const char *model_name;
92 unsigned int min_sampling_rate; // Hz
93 unsigned int max_sampling_rate; // Hz
94 unsigned int vref_fixed_mv;
95 bool wait_init_sequence;
99 unsigned int num_channels;
100 const struct aspeed_adc_trim_locate *trim_locate;
108 struct aspeed_adc_data {
110 const struct aspeed_adc_model_data *model_data;
111 struct regulator *regulator;
114 struct clk_hw *fixed_div_clk;
115 struct clk_hw *clk_prescaler;
116 struct clk_hw *clk_scaler;
117 struct reset_control *rst;
119 u32 sample_period_ns;
121 bool battery_sensing;
122 struct adc_gain battery_mode_gain;
125 #define ASPEED_CHAN(_idx, _data_reg_addr) { \
126 .type = IIO_VOLTAGE, \
129 .address = (_data_reg_addr), \
130 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
131 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
132 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
133 BIT(IIO_CHAN_INFO_OFFSET), \
136 static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
137 ASPEED_CHAN(0, 0x10),
138 ASPEED_CHAN(1, 0x12),
139 ASPEED_CHAN(2, 0x14),
140 ASPEED_CHAN(3, 0x16),
141 ASPEED_CHAN(4, 0x18),
142 ASPEED_CHAN(5, 0x1A),
143 ASPEED_CHAN(6, 0x1C),
144 ASPEED_CHAN(7, 0x1E),
145 ASPEED_CHAN(8, 0x20),
146 ASPEED_CHAN(9, 0x22),
147 ASPEED_CHAN(10, 0x24),
148 ASPEED_CHAN(11, 0x26),
149 ASPEED_CHAN(12, 0x28),
150 ASPEED_CHAN(13, 0x2A),
151 ASPEED_CHAN(14, 0x2C),
152 ASPEED_CHAN(15, 0x2E),
155 #define ASPEED_BAT_CHAN(_idx, _data_reg_addr) { \
156 .type = IIO_VOLTAGE, \
159 .address = (_data_reg_addr), \
160 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
161 BIT(IIO_CHAN_INFO_OFFSET), \
162 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
163 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
165 static const struct iio_chan_spec aspeed_adc_iio_bat_channels[] = {
166 ASPEED_CHAN(0, 0x10),
167 ASPEED_CHAN(1, 0x12),
168 ASPEED_CHAN(2, 0x14),
169 ASPEED_CHAN(3, 0x16),
170 ASPEED_CHAN(4, 0x18),
171 ASPEED_CHAN(5, 0x1A),
172 ASPEED_CHAN(6, 0x1C),
173 ASPEED_BAT_CHAN(7, 0x1E),
176 static int aspeed_adc_set_trim_data(struct iio_dev *indio_dev)
178 struct device_node *syscon;
180 u32 scu_otp, trimming_val;
181 struct aspeed_adc_data *data = iio_priv(indio_dev);
183 syscon = of_find_node_by_name(NULL, "syscon");
184 if (syscon == NULL) {
185 dev_warn(data->dev, "Couldn't find syscon node\n");
188 scu = syscon_node_to_regmap(syscon);
191 dev_warn(data->dev, "Failed to get syscon regmap\n");
194 if (data->model_data->trim_locate) {
195 if (regmap_read(scu, data->model_data->trim_locate->offset,
198 "Failed to get adc trimming data\n");
203 (data->model_data->trim_locate->field)) >>
204 __ffs(data->model_data->trim_locate->field);
207 "trimming val = %d, offset = %08x, fields = %08x\n",
208 trimming_val, data->model_data->trim_locate->offset,
209 data->model_data->trim_locate->field);
210 writel(trimming_val, data->base + ASPEED_REG_COMPENSATION_TRIM);
215 static int aspeed_adc_compensation(struct iio_dev *indio_dev)
217 struct aspeed_adc_data *data = iio_priv(indio_dev);
218 u32 index, adc_raw = 0;
219 u32 adc_engine_control_reg_val;
221 adc_engine_control_reg_val =
222 readl(data->base + ASPEED_REG_ENGINE_CONTROL);
223 adc_engine_control_reg_val &= ~ASPEED_ADC_OP_MODE;
224 adc_engine_control_reg_val |=
225 (FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) |
226 ASPEED_ADC_ENGINE_ENABLE);
228 * Enable compensating sensing:
229 * After that, the input voltage of ADC will force to half of the reference
230 * voltage. So the expected reading raw data will become half of the max
231 * value. We can get compensating value = 0x200 - ADC read raw value.
232 * It is recommended to average at least 10 samples to get a final CV.
234 writel(adc_engine_control_reg_val | ASPEED_ADC_CTRL_COMPENSATION |
235 ASPEED_ADC_CTRL_CHANNEL_ENABLE(0),
236 data->base + ASPEED_REG_ENGINE_CONTROL);
238 * After enable compensating sensing mode need to wait some time for ADC stable
239 * Experiment result is 1ms.
243 for (index = 0; index < 16; index++) {
245 * Waiting for the sampling period ensures that the value acquired
246 * is fresh each time.
248 ndelay(data->sample_period_ns);
249 adc_raw += readw(data->base + aspeed_adc_iio_channels[0].address);
252 data->cv = BIT(ASPEED_RESOLUTION_BITS - 1) - adc_raw;
253 writel(adc_engine_control_reg_val,
254 data->base + ASPEED_REG_ENGINE_CONTROL);
255 dev_dbg(data->dev, "Compensating value = %d\n", data->cv);
260 static int aspeed_adc_set_sampling_rate(struct iio_dev *indio_dev, u32 rate)
262 struct aspeed_adc_data *data = iio_priv(indio_dev);
264 if (rate < data->model_data->min_sampling_rate ||
265 rate > data->model_data->max_sampling_rate)
267 /* Each sampling needs 12 clocks to convert.*/
268 clk_set_rate(data->clk_scaler->clk, rate * ASPEED_CLOCKS_PER_SAMPLE);
269 rate = clk_get_rate(data->clk_scaler->clk);
270 data->sample_period_ns = DIV_ROUND_UP_ULL(
271 (u64)NSEC_PER_SEC * ASPEED_CLOCKS_PER_SAMPLE, rate);
272 dev_dbg(data->dev, "Adc clock = %d sample period = %d ns", rate,
273 data->sample_period_ns);
278 static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
279 struct iio_chan_spec const *chan,
280 int *val, int *val2, long mask)
282 struct aspeed_adc_data *data = iio_priv(indio_dev);
283 u32 adc_engine_control_reg_val;
286 case IIO_CHAN_INFO_RAW:
287 if (data->battery_sensing && chan->channel == 7) {
288 adc_engine_control_reg_val =
289 readl(data->base + ASPEED_REG_ENGINE_CONTROL);
290 writel(adc_engine_control_reg_val |
291 FIELD_PREP(ASPEED_ADC_CH7_MODE,
292 ASPEED_ADC_CH7_BAT) |
293 ASPEED_ADC_BAT_SENSING_ENABLE,
294 data->base + ASPEED_REG_ENGINE_CONTROL);
296 * After enable battery sensing mode need to wait some time for adc stable
297 * Experiment result is 1ms.
300 *val = readw(data->base + chan->address);
301 *val = (*val * data->battery_mode_gain.mult) /
302 data->battery_mode_gain.div;
303 /* Restore control register value */
304 writel(adc_engine_control_reg_val,
305 data->base + ASPEED_REG_ENGINE_CONTROL);
307 *val = readw(data->base + chan->address);
310 case IIO_CHAN_INFO_OFFSET:
311 if (data->battery_sensing && chan->channel == 7)
312 *val = (data->cv * data->battery_mode_gain.mult) /
313 data->battery_mode_gain.div;
318 case IIO_CHAN_INFO_SCALE:
319 *val = data->vref_mv;
320 *val2 = ASPEED_RESOLUTION_BITS;
321 return IIO_VAL_FRACTIONAL_LOG2;
323 case IIO_CHAN_INFO_SAMP_FREQ:
324 *val = clk_get_rate(data->clk_scaler->clk) /
325 ASPEED_CLOCKS_PER_SAMPLE;
333 static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
334 struct iio_chan_spec const *chan,
335 int val, int val2, long mask)
338 case IIO_CHAN_INFO_SAMP_FREQ:
339 return aspeed_adc_set_sampling_rate(indio_dev, val);
341 case IIO_CHAN_INFO_SCALE:
342 case IIO_CHAN_INFO_RAW:
344 * Technically, these could be written but the only reasons
345 * for doing so seem better handled in userspace. EPERM is
346 * returned to signal this is a policy choice rather than a
347 * hardware limitation.
356 static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
357 unsigned int reg, unsigned int writeval,
358 unsigned int *readval)
360 struct aspeed_adc_data *data = iio_priv(indio_dev);
362 if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
365 *readval = readl(data->base + reg);
370 static const struct iio_info aspeed_adc_iio_info = {
371 .read_raw = aspeed_adc_read_raw,
372 .write_raw = aspeed_adc_write_raw,
373 .debugfs_reg_access = aspeed_adc_reg_access,
376 static void aspeed_adc_unregister_fixed_divider(void *data)
378 struct clk_hw *clk = data;
380 clk_hw_unregister_fixed_factor(clk);
383 static void aspeed_adc_reset_assert(void *data)
385 struct reset_control *rst = data;
387 reset_control_assert(rst);
390 static void aspeed_adc_clk_disable_unprepare(void *data)
392 struct clk *clk = data;
394 clk_disable_unprepare(clk);
397 static void aspeed_adc_power_down(void *data)
399 struct aspeed_adc_data *priv_data = data;
401 writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN),
402 priv_data->base + ASPEED_REG_ENGINE_CONTROL);
405 static void aspeed_adc_reg_disable(void *data)
407 struct regulator *reg = data;
409 regulator_disable(reg);
412 static int aspeed_adc_vref_config(struct iio_dev *indio_dev)
414 struct aspeed_adc_data *data = iio_priv(indio_dev);
416 u32 adc_engine_control_reg_val;
418 if (data->model_data->vref_fixed_mv) {
419 data->vref_mv = data->model_data->vref_fixed_mv;
422 adc_engine_control_reg_val =
423 readl(data->base + ASPEED_REG_ENGINE_CONTROL);
424 data->regulator = devm_regulator_get_optional(data->dev, "vref");
425 if (!IS_ERR(data->regulator)) {
426 ret = regulator_enable(data->regulator);
429 ret = devm_add_action_or_reset(
430 data->dev, aspeed_adc_reg_disable, data->regulator);
433 data->vref_mv = regulator_get_voltage(data->regulator);
434 /* Conversion from uV to mV */
435 data->vref_mv /= 1000;
436 if ((data->vref_mv >= 1550) && (data->vref_mv <= 2700))
437 writel(adc_engine_control_reg_val |
439 ASPEED_ADC_REF_VOLTAGE,
440 ASPEED_ADC_REF_VOLTAGE_EXT_HIGH),
441 data->base + ASPEED_REG_ENGINE_CONTROL);
442 else if ((data->vref_mv >= 900) && (data->vref_mv <= 1650))
443 writel(adc_engine_control_reg_val |
445 ASPEED_ADC_REF_VOLTAGE,
446 ASPEED_ADC_REF_VOLTAGE_EXT_LOW),
447 data->base + ASPEED_REG_ENGINE_CONTROL);
449 dev_err(data->dev, "Regulator voltage %d not support",
454 if (PTR_ERR(data->regulator) != -ENODEV)
455 return PTR_ERR(data->regulator);
456 data->vref_mv = 2500000;
457 of_property_read_u32(data->dev->of_node,
458 "aspeed,int-vref-microvolt",
460 /* Conversion from uV to mV */
461 data->vref_mv /= 1000;
462 if (data->vref_mv == 2500)
463 writel(adc_engine_control_reg_val |
464 FIELD_PREP(ASPEED_ADC_REF_VOLTAGE,
465 ASPEED_ADC_REF_VOLTAGE_2500mV),
466 data->base + ASPEED_REG_ENGINE_CONTROL);
467 else if (data->vref_mv == 1200)
468 writel(adc_engine_control_reg_val |
469 FIELD_PREP(ASPEED_ADC_REF_VOLTAGE,
470 ASPEED_ADC_REF_VOLTAGE_1200mV),
471 data->base + ASPEED_REG_ENGINE_CONTROL);
473 dev_err(data->dev, "Voltage %d not support", data->vref_mv);
481 static int aspeed_adc_probe(struct platform_device *pdev)
483 struct iio_dev *indio_dev;
484 struct aspeed_adc_data *data;
486 u32 adc_engine_control_reg_val;
487 unsigned long scaler_flags = 0;
488 char clk_name[32], clk_parent_name[32];
490 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
494 data = iio_priv(indio_dev);
495 data->dev = &pdev->dev;
496 data->model_data = of_device_get_match_data(&pdev->dev);
497 platform_set_drvdata(pdev, indio_dev);
499 data->base = devm_platform_ioremap_resource(pdev, 0);
500 if (IS_ERR(data->base))
501 return PTR_ERR(data->base);
503 /* Register ADC clock prescaler with source specified by device tree. */
504 spin_lock_init(&data->clk_lock);
505 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), "%s",
506 of_clk_get_parent_name(pdev->dev.of_node, 0));
507 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-fixed-div",
508 data->model_data->model_name);
509 data->fixed_div_clk = clk_hw_register_fixed_factor(
510 &pdev->dev, clk_name, clk_parent_name, 0, 1, 2);
511 if (IS_ERR(data->fixed_div_clk))
512 return PTR_ERR(data->fixed_div_clk);
514 ret = devm_add_action_or_reset(data->dev,
515 aspeed_adc_unregister_fixed_divider,
516 data->fixed_div_clk);
519 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), clk_name);
521 if (data->model_data->need_prescaler) {
522 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-prescaler",
523 data->model_data->model_name);
524 data->clk_prescaler = devm_clk_hw_register_divider(
525 &pdev->dev, clk_name, clk_parent_name, 0,
526 data->base + ASPEED_REG_CLOCK_CONTROL, 17, 15, 0,
528 if (IS_ERR(data->clk_prescaler))
529 return PTR_ERR(data->clk_prescaler);
530 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name),
532 scaler_flags = CLK_SET_RATE_PARENT;
535 * Register ADC clock scaler downstream from the prescaler. Allow rate
536 * setting to adjust the prescaler as well.
538 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-scaler",
539 data->model_data->model_name);
540 data->clk_scaler = devm_clk_hw_register_divider(
541 &pdev->dev, clk_name, clk_parent_name, scaler_flags,
542 data->base + ASPEED_REG_CLOCK_CONTROL, 0,
543 data->model_data->scaler_bit_width,
544 data->model_data->need_prescaler ? CLK_DIVIDER_ONE_BASED : 0,
546 if (IS_ERR(data->clk_scaler))
547 return PTR_ERR(data->clk_scaler);
549 data->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
550 if (IS_ERR(data->rst)) {
552 "invalid or missing reset controller device tree entry");
553 return PTR_ERR(data->rst);
555 reset_control_deassert(data->rst);
557 ret = devm_add_action_or_reset(data->dev, aspeed_adc_reset_assert,
562 ret = aspeed_adc_vref_config(indio_dev);
566 if (of_find_property(data->dev->of_node, "aspeed,trim-data-valid",
568 ret = aspeed_adc_set_trim_data(indio_dev);
573 if (of_find_property(data->dev->of_node, "aspeed,battery-sensing",
575 if (data->model_data->bat_sense_sup) {
576 data->battery_sensing = 1;
577 if (readl(data->base + ASPEED_REG_ENGINE_CONTROL) &
578 ASPEED_ADC_BAT_SENSING_DIV) {
579 data->battery_mode_gain.mult = 3;
580 data->battery_mode_gain.div = 1;
582 data->battery_mode_gain.mult = 3;
583 data->battery_mode_gain.div = 2;
587 "Failed to enable battery-sensing mode\n");
590 ret = clk_prepare_enable(data->clk_scaler->clk);
593 ret = devm_add_action_or_reset(data->dev,
594 aspeed_adc_clk_disable_unprepare,
595 data->clk_scaler->clk);
598 ret = aspeed_adc_set_sampling_rate(indio_dev,
599 ASPEED_ADC_DEF_SAMPLING_RATE);
603 adc_engine_control_reg_val =
604 readl(data->base + ASPEED_REG_ENGINE_CONTROL);
605 adc_engine_control_reg_val |=
606 FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) |
607 ASPEED_ADC_ENGINE_ENABLE;
608 /* Enable engine in normal mode. */
609 writel(adc_engine_control_reg_val,
610 data->base + ASPEED_REG_ENGINE_CONTROL);
612 ret = devm_add_action_or_reset(data->dev, aspeed_adc_power_down,
617 if (data->model_data->wait_init_sequence) {
618 /* Wait for initial sequence complete. */
619 ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL,
620 adc_engine_control_reg_val,
621 adc_engine_control_reg_val &
622 ASPEED_ADC_CTRL_INIT_RDY,
623 ASPEED_ADC_INIT_POLLING_TIME,
624 ASPEED_ADC_INIT_TIMEOUT);
629 aspeed_adc_compensation(indio_dev);
630 /* Start all channels in normal mode. */
631 adc_engine_control_reg_val =
632 readl(data->base + ASPEED_REG_ENGINE_CONTROL);
633 adc_engine_control_reg_val |= ASPEED_ADC_CTRL_CHANNEL;
634 writel(adc_engine_control_reg_val,
635 data->base + ASPEED_REG_ENGINE_CONTROL);
637 indio_dev->name = data->model_data->model_name;
638 indio_dev->info = &aspeed_adc_iio_info;
639 indio_dev->modes = INDIO_DIRECT_MODE;
640 indio_dev->channels = data->battery_sensing ?
641 aspeed_adc_iio_bat_channels :
642 aspeed_adc_iio_channels;
643 indio_dev->num_channels = data->model_data->num_channels;
645 ret = devm_iio_device_register(data->dev, indio_dev);
649 static const struct aspeed_adc_trim_locate ast2500_adc_trim = {
651 .field = GENMASK(31, 28),
654 static const struct aspeed_adc_trim_locate ast2600_adc0_trim = {
656 .field = GENMASK(3, 0),
659 static const struct aspeed_adc_trim_locate ast2600_adc1_trim = {
661 .field = GENMASK(7, 4),
664 static const struct aspeed_adc_model_data ast2400_model_data = {
665 .model_name = "ast2400-adc",
666 .vref_fixed_mv = 2500,
667 .min_sampling_rate = 10000,
668 .max_sampling_rate = 500000,
669 .need_prescaler = true,
670 .scaler_bit_width = 10,
674 static const struct aspeed_adc_model_data ast2500_model_data = {
675 .model_name = "ast2500-adc",
676 .vref_fixed_mv = 1800,
677 .min_sampling_rate = 1,
678 .max_sampling_rate = 1000000,
679 .wait_init_sequence = true,
680 .need_prescaler = true,
681 .scaler_bit_width = 10,
683 .trim_locate = &ast2500_adc_trim,
686 static const struct aspeed_adc_model_data ast2600_adc0_model_data = {
687 .model_name = "ast2600-adc0",
688 .min_sampling_rate = 10000,
689 .max_sampling_rate = 500000,
690 .wait_init_sequence = true,
691 .bat_sense_sup = true,
692 .scaler_bit_width = 16,
694 .trim_locate = &ast2600_adc0_trim,
697 static const struct aspeed_adc_model_data ast2600_adc1_model_data = {
698 .model_name = "ast2600-adc1",
699 .min_sampling_rate = 10000,
700 .max_sampling_rate = 500000,
701 .wait_init_sequence = true,
702 .bat_sense_sup = true,
703 .scaler_bit_width = 16,
705 .trim_locate = &ast2600_adc1_trim,
708 static const struct of_device_id aspeed_adc_matches[] = {
709 { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
710 { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
711 { .compatible = "aspeed,ast2600-adc0", .data = &ast2600_adc0_model_data },
712 { .compatible = "aspeed,ast2600-adc1", .data = &ast2600_adc1_model_data },
715 MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
717 static struct platform_driver aspeed_adc_driver = {
718 .probe = aspeed_adc_probe,
720 .name = KBUILD_MODNAME,
721 .of_match_table = aspeed_adc_matches,
725 module_platform_driver(aspeed_adc_driver);
727 MODULE_AUTHOR("Rick Altherr <raltherr@google.com>");
728 MODULE_DESCRIPTION("Aspeed AST2400/2500/2600 ADC Driver");
729 MODULE_LICENSE("GPL");