2 * Aspeed AST2400/2500 ADC
4 * Copyright (C) 2017 Google, Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
17 #include <linux/module.h>
18 #include <linux/of_platform.h>
19 #include <linux/platform_device.h>
20 #include <linux/spinlock.h>
21 #include <linux/types.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/driver.h>
25 #include <linux/iopoll.h>
27 #define ASPEED_RESOLUTION_BITS 10
28 #define ASPEED_CLOCKS_PER_SAMPLE 12
30 #define ASPEED_REG_ENGINE_CONTROL 0x00
31 #define ASPEED_REG_INTERRUPT_CONTROL 0x04
32 #define ASPEED_REG_VGA_DETECT_CONTROL 0x08
33 #define ASPEED_REG_CLOCK_CONTROL 0x0C
34 #define ASPEED_REG_MAX 0xC0
36 #define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1)
37 #define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1)
38 #define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1)
40 #define ASPEED_ENGINE_ENABLE BIT(0)
42 #define ASPEED_ADC_CTRL_INIT_RDY BIT(8)
44 #define ASPEED_ADC_INIT_POLLING_TIME 500
45 #define ASPEED_ADC_INIT_TIMEOUT 500000
47 struct aspeed_adc_model_data {
48 const char *model_name;
49 unsigned int min_sampling_rate; // Hz
50 unsigned int max_sampling_rate; // Hz
51 unsigned int vref_voltage; // mV
52 bool wait_init_sequence;
55 struct aspeed_adc_data {
59 struct clk_hw *clk_prescaler;
60 struct clk_hw *clk_scaler;
63 #define ASPEED_CHAN(_idx, _data_reg_addr) { \
64 .type = IIO_VOLTAGE, \
67 .address = (_data_reg_addr), \
68 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
69 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
70 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
73 static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
84 ASPEED_CHAN(10, 0x24),
85 ASPEED_CHAN(11, 0x26),
86 ASPEED_CHAN(12, 0x28),
87 ASPEED_CHAN(13, 0x2A),
88 ASPEED_CHAN(14, 0x2C),
89 ASPEED_CHAN(15, 0x2E),
92 static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
93 struct iio_chan_spec const *chan,
94 int *val, int *val2, long mask)
96 struct aspeed_adc_data *data = iio_priv(indio_dev);
97 const struct aspeed_adc_model_data *model_data =
98 of_device_get_match_data(data->dev);
101 case IIO_CHAN_INFO_RAW:
102 *val = readw(data->base + chan->address);
105 case IIO_CHAN_INFO_SCALE:
106 *val = model_data->vref_voltage;
107 *val2 = ASPEED_RESOLUTION_BITS;
108 return IIO_VAL_FRACTIONAL_LOG2;
110 case IIO_CHAN_INFO_SAMP_FREQ:
111 *val = clk_get_rate(data->clk_scaler->clk) /
112 ASPEED_CLOCKS_PER_SAMPLE;
120 static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
121 struct iio_chan_spec const *chan,
122 int val, int val2, long mask)
124 struct aspeed_adc_data *data = iio_priv(indio_dev);
125 const struct aspeed_adc_model_data *model_data =
126 of_device_get_match_data(data->dev);
129 case IIO_CHAN_INFO_SAMP_FREQ:
130 if (val < model_data->min_sampling_rate ||
131 val > model_data->max_sampling_rate)
134 clk_set_rate(data->clk_scaler->clk,
135 val * ASPEED_CLOCKS_PER_SAMPLE);
138 case IIO_CHAN_INFO_SCALE:
139 case IIO_CHAN_INFO_RAW:
141 * Technically, these could be written but the only reasons
142 * for doing so seem better handled in userspace. EPERM is
143 * returned to signal this is a policy choice rather than a
144 * hardware limitation.
153 static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
154 unsigned int reg, unsigned int writeval,
155 unsigned int *readval)
157 struct aspeed_adc_data *data = iio_priv(indio_dev);
159 if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
162 *readval = readl(data->base + reg);
167 static const struct iio_info aspeed_adc_iio_info = {
168 .read_raw = aspeed_adc_read_raw,
169 .write_raw = aspeed_adc_write_raw,
170 .debugfs_reg_access = aspeed_adc_reg_access,
173 static int aspeed_adc_probe(struct platform_device *pdev)
175 struct iio_dev *indio_dev;
176 struct aspeed_adc_data *data;
177 const struct aspeed_adc_model_data *model_data;
178 struct resource *res;
179 const char *clk_parent_name;
181 u32 adc_engine_control_reg_val;
183 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
187 data = iio_priv(indio_dev);
188 data->dev = &pdev->dev;
190 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
191 data->base = devm_ioremap_resource(&pdev->dev, res);
192 if (IS_ERR(data->base))
193 return PTR_ERR(data->base);
195 /* Register ADC clock prescaler with source specified by device tree. */
196 spin_lock_init(&data->clk_lock);
197 clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
199 data->clk_prescaler = clk_hw_register_divider(
200 &pdev->dev, "prescaler", clk_parent_name, 0,
201 data->base + ASPEED_REG_CLOCK_CONTROL,
202 17, 15, 0, &data->clk_lock);
203 if (IS_ERR(data->clk_prescaler))
204 return PTR_ERR(data->clk_prescaler);
207 * Register ADC clock scaler downstream from the prescaler. Allow rate
208 * setting to adjust the prescaler as well.
210 data->clk_scaler = clk_hw_register_divider(
211 &pdev->dev, "scaler", "prescaler",
213 data->base + ASPEED_REG_CLOCK_CONTROL,
214 0, 10, 0, &data->clk_lock);
215 if (IS_ERR(data->clk_scaler)) {
216 ret = PTR_ERR(data->clk_scaler);
220 model_data = of_device_get_match_data(&pdev->dev);
222 if (model_data->wait_init_sequence) {
223 /* Enable engine in normal mode. */
224 writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE,
225 data->base + ASPEED_REG_ENGINE_CONTROL);
227 /* Wait for initial sequence complete. */
228 ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL,
229 adc_engine_control_reg_val,
230 adc_engine_control_reg_val &
231 ASPEED_ADC_CTRL_INIT_RDY,
232 ASPEED_ADC_INIT_POLLING_TIME,
233 ASPEED_ADC_INIT_TIMEOUT);
238 /* Start all channels in normal mode. */
239 ret = clk_prepare_enable(data->clk_scaler->clk);
241 goto clk_enable_error;
243 adc_engine_control_reg_val = GENMASK(31, 16) |
244 ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE;
245 writel(adc_engine_control_reg_val,
246 data->base + ASPEED_REG_ENGINE_CONTROL);
248 model_data = of_device_get_match_data(&pdev->dev);
249 indio_dev->name = model_data->model_name;
250 indio_dev->dev.parent = &pdev->dev;
251 indio_dev->info = &aspeed_adc_iio_info;
252 indio_dev->modes = INDIO_DIRECT_MODE;
253 indio_dev->channels = aspeed_adc_iio_channels;
254 indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels);
256 ret = iio_device_register(indio_dev);
258 goto iio_register_error;
263 writel(ASPEED_OPERATION_MODE_POWER_DOWN,
264 data->base + ASPEED_REG_ENGINE_CONTROL);
265 clk_disable_unprepare(data->clk_scaler->clk);
267 clk_hw_unregister_divider(data->clk_scaler);
270 clk_hw_unregister_divider(data->clk_prescaler);
274 static int aspeed_adc_remove(struct platform_device *pdev)
276 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
277 struct aspeed_adc_data *data = iio_priv(indio_dev);
279 iio_device_unregister(indio_dev);
280 writel(ASPEED_OPERATION_MODE_POWER_DOWN,
281 data->base + ASPEED_REG_ENGINE_CONTROL);
282 clk_disable_unprepare(data->clk_scaler->clk);
283 clk_hw_unregister_divider(data->clk_scaler);
284 clk_hw_unregister_divider(data->clk_prescaler);
289 static const struct aspeed_adc_model_data ast2400_model_data = {
290 .model_name = "ast2400-adc",
291 .vref_voltage = 2500, // mV
292 .min_sampling_rate = 10000,
293 .max_sampling_rate = 500000,
296 static const struct aspeed_adc_model_data ast2500_model_data = {
297 .model_name = "ast2500-adc",
298 .vref_voltage = 1800, // mV
299 .min_sampling_rate = 1,
300 .max_sampling_rate = 1000000,
301 .wait_init_sequence = true,
304 static const struct of_device_id aspeed_adc_matches[] = {
305 { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
306 { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
309 MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
311 static struct platform_driver aspeed_adc_driver = {
312 .probe = aspeed_adc_probe,
313 .remove = aspeed_adc_remove,
315 .name = KBUILD_MODNAME,
316 .of_match_table = aspeed_adc_matches,
320 module_platform_driver(aspeed_adc_driver);
322 MODULE_AUTHOR("Rick Altherr <raltherr@google.com>");
323 MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver");
324 MODULE_LICENSE("GPL");