1 // SPDX-License-Identifier: GPL-2.0-only
3 * Analog Devices Generic AXI ADC IP core
4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
6 * Copyright 2012-2020 Analog Devices Inc.
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
16 #include <linux/slab.h>
18 #include <linux/iio/iio.h>
19 #include <linux/iio/sysfs.h>
20 #include <linux/iio/buffer.h>
21 #include <linux/iio/buffer-dmaengine.h>
23 #include <linux/fpga/adi-axi-common.h>
24 #include <linux/iio/adc/adi-axi-adc.h>
27 * Register definitions:
28 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
33 #define ADI_AXI_REG_RSTN 0x0040
34 #define ADI_AXI_REG_RSTN_CE_N BIT(2)
35 #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1)
36 #define ADI_AXI_REG_RSTN_RSTN BIT(0)
38 /* ADC Channel controls */
40 #define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40)
41 #define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11)
42 #define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10)
43 #define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9)
44 #define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8)
45 #define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6)
46 #define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5)
47 #define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4)
48 #define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1)
49 #define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0)
51 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \
52 (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \
53 ADI_AXI_REG_CHAN_CTRL_FMT_EN | \
54 ADI_AXI_REG_CHAN_CTRL_ENABLE)
56 struct adi_axi_adc_core_info {
60 struct adi_axi_adc_state {
63 struct adi_axi_adc_client *client;
67 struct adi_axi_adc_client {
68 struct list_head entry;
69 struct adi_axi_adc_conv conv;
70 struct adi_axi_adc_state *state;
72 const struct adi_axi_adc_core_info *info;
75 static LIST_HEAD(registered_clients);
76 static DEFINE_MUTEX(registered_clients_lock);
78 static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv)
80 return container_of(conv, struct adi_axi_adc_client, conv);
83 void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv)
85 struct adi_axi_adc_client *cl = conv_to_client(conv);
87 return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN);
89 EXPORT_SYMBOL_GPL(adi_axi_adc_conv_priv);
91 static void adi_axi_adc_write(struct adi_axi_adc_state *st,
95 iowrite32(val, st->regs + reg);
98 static unsigned int adi_axi_adc_read(struct adi_axi_adc_state *st,
101 return ioread32(st->regs + reg);
104 static int adi_axi_adc_config_dma_buffer(struct device *dev,
105 struct iio_dev *indio_dev)
107 const char *dma_name;
109 if (!device_property_present(dev, "dmas"))
112 if (device_property_read_string(dev, "dma-names", &dma_name))
115 return devm_iio_dmaengine_buffer_setup(indio_dev->dev.parent,
116 indio_dev, dma_name);
119 static int adi_axi_adc_read_raw(struct iio_dev *indio_dev,
120 struct iio_chan_spec const *chan,
121 int *val, int *val2, long mask)
123 struct adi_axi_adc_state *st = iio_priv(indio_dev);
124 struct adi_axi_adc_conv *conv = &st->client->conv;
129 return conv->read_raw(conv, chan, val, val2, mask);
132 static int adi_axi_adc_write_raw(struct iio_dev *indio_dev,
133 struct iio_chan_spec const *chan,
134 int val, int val2, long mask)
136 struct adi_axi_adc_state *st = iio_priv(indio_dev);
137 struct adi_axi_adc_conv *conv = &st->client->conv;
139 if (!conv->write_raw)
142 return conv->write_raw(conv, chan, val, val2, mask);
145 static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev,
146 const unsigned long *scan_mask)
148 struct adi_axi_adc_state *st = iio_priv(indio_dev);
149 struct adi_axi_adc_conv *conv = &st->client->conv;
150 unsigned int i, ctrl;
152 for (i = 0; i < conv->chip_info->num_channels; i++) {
153 ctrl = adi_axi_adc_read(st, ADI_AXI_REG_CHAN_CTRL(i));
155 if (test_bit(i, scan_mask))
156 ctrl |= ADI_AXI_REG_CHAN_CTRL_ENABLE;
158 ctrl &= ~ADI_AXI_REG_CHAN_CTRL_ENABLE;
160 adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), ctrl);
166 static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev,
169 struct adi_axi_adc_client *cl;
172 alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN);
174 alloc_size += ALIGN(sizeof_priv, IIO_ALIGN);
176 cl = kzalloc(alloc_size, GFP_KERNEL);
178 return ERR_PTR(-ENOMEM);
180 mutex_lock(®istered_clients_lock);
182 cl->dev = get_device(dev);
184 list_add_tail(&cl->entry, ®istered_clients);
186 mutex_unlock(®istered_clients_lock);
191 static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv)
193 struct adi_axi_adc_client *cl = conv_to_client(conv);
195 mutex_lock(®istered_clients_lock);
197 list_del(&cl->entry);
200 mutex_unlock(®istered_clients_lock);
205 static void devm_adi_axi_adc_conv_release(void *conv)
207 adi_axi_adc_conv_unregister(conv);
210 struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev,
213 struct adi_axi_adc_conv *conv;
216 conv = adi_axi_adc_conv_register(dev, sizeof_priv);
220 ret = devm_add_action_or_reset(dev, devm_adi_axi_adc_conv_release,
227 EXPORT_SYMBOL_GPL(devm_adi_axi_adc_conv_register);
229 static ssize_t in_voltage_scale_available_show(struct device *dev,
230 struct device_attribute *attr,
233 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
234 struct adi_axi_adc_state *st = iio_priv(indio_dev);
235 struct adi_axi_adc_conv *conv = &st->client->conv;
239 for (i = 0; i < conv->chip_info->num_scales; i++) {
240 const unsigned int *s = conv->chip_info->scale_table[i];
242 len += scnprintf(buf + len, PAGE_SIZE - len,
243 "%u.%06u ", s[0], s[1]);
250 static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0);
253 ADI_AXI_ATTR_SCALE_AVAIL,
256 #define ADI_AXI_ATTR(_en_, _file_) \
257 [ADI_AXI_ATTR_##_en_] = &iio_dev_attr_##_file_.dev_attr.attr
259 static struct attribute *adi_axi_adc_attributes[] = {
260 ADI_AXI_ATTR(SCALE_AVAIL, in_voltage_scale_available),
264 static umode_t axi_adc_attr_is_visible(struct kobject *kobj,
265 struct attribute *attr, int n)
267 struct device *dev = kobj_to_dev(kobj);
268 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
269 struct adi_axi_adc_state *st = iio_priv(indio_dev);
270 struct adi_axi_adc_conv *conv = &st->client->conv;
273 case ADI_AXI_ATTR_SCALE_AVAIL:
274 if (!conv->chip_info->num_scales)
282 static const struct attribute_group adi_axi_adc_attribute_group = {
283 .attrs = adi_axi_adc_attributes,
284 .is_visible = axi_adc_attr_is_visible,
287 static const struct iio_info adi_axi_adc_info = {
288 .read_raw = &adi_axi_adc_read_raw,
289 .write_raw = &adi_axi_adc_write_raw,
290 .attrs = &adi_axi_adc_attribute_group,
291 .update_scan_mode = &adi_axi_adc_update_scan_mode,
294 static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = {
295 .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
298 static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev)
300 const struct adi_axi_adc_core_info *info;
301 struct adi_axi_adc_client *cl;
302 struct device_node *cln;
304 info = of_device_get_match_data(dev);
306 return ERR_PTR(-ENODEV);
308 cln = of_parse_phandle(dev->of_node, "adi,adc-dev", 0);
310 dev_err(dev, "No 'adi,adc-dev' node defined\n");
311 return ERR_PTR(-ENODEV);
314 mutex_lock(®istered_clients_lock);
316 list_for_each_entry(cl, ®istered_clients, entry) {
320 if (cl->dev->of_node != cln)
323 if (!try_module_get(cl->dev->driver->owner)) {
324 mutex_unlock(®istered_clients_lock);
326 return ERR_PTR(-ENODEV);
331 mutex_unlock(®istered_clients_lock);
336 mutex_unlock(®istered_clients_lock);
339 return ERR_PTR(-EPROBE_DEFER);
342 static int adi_axi_adc_setup_channels(struct device *dev,
343 struct adi_axi_adc_state *st)
345 struct adi_axi_adc_conv *conv = &st->client->conv;
348 if (conv->preenable_setup) {
349 ret = conv->preenable_setup(conv);
354 for (i = 0; i < conv->chip_info->num_channels; i++) {
355 adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i),
356 ADI_AXI_REG_CHAN_CTRL_DEFAULTS);
362 static void axi_adc_reset(struct adi_axi_adc_state *st)
364 adi_axi_adc_write(st, ADI_AXI_REG_RSTN, 0);
366 adi_axi_adc_write(st, ADI_AXI_REG_RSTN, ADI_AXI_REG_RSTN_MMCM_RSTN);
368 adi_axi_adc_write(st, ADI_AXI_REG_RSTN,
369 ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
372 static void adi_axi_adc_cleanup(void *data)
374 struct adi_axi_adc_client *cl = data;
377 module_put(cl->dev->driver->owner);
380 static int adi_axi_adc_probe(struct platform_device *pdev)
382 struct adi_axi_adc_conv *conv;
383 struct iio_dev *indio_dev;
384 struct adi_axi_adc_client *cl;
385 struct adi_axi_adc_state *st;
389 cl = adi_axi_adc_attach_client(&pdev->dev);
393 ret = devm_add_action_or_reset(&pdev->dev, adi_axi_adc_cleanup, cl);
397 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
398 if (indio_dev == NULL)
401 st = iio_priv(indio_dev);
404 mutex_init(&st->lock);
406 st->regs = devm_platform_ioremap_resource(pdev, 0);
407 if (IS_ERR(st->regs))
408 return PTR_ERR(st->regs);
410 conv = &st->client->conv;
414 ver = adi_axi_adc_read(st, ADI_AXI_REG_VERSION);
416 if (cl->info->version > ver) {
418 "IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
419 ADI_AXI_PCORE_VER_MAJOR(cl->info->version),
420 ADI_AXI_PCORE_VER_MINOR(cl->info->version),
421 ADI_AXI_PCORE_VER_PATCH(cl->info->version),
422 ADI_AXI_PCORE_VER_MAJOR(ver),
423 ADI_AXI_PCORE_VER_MINOR(ver),
424 ADI_AXI_PCORE_VER_PATCH(ver));
428 indio_dev->info = &adi_axi_adc_info;
429 indio_dev->name = "adi-axi-adc";
430 indio_dev->modes = INDIO_DIRECT_MODE;
431 indio_dev->num_channels = conv->chip_info->num_channels;
432 indio_dev->channels = conv->chip_info->channels;
434 ret = adi_axi_adc_config_dma_buffer(&pdev->dev, indio_dev);
438 ret = adi_axi_adc_setup_channels(&pdev->dev, st);
442 ret = devm_iio_device_register(&pdev->dev, indio_dev);
446 dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
447 ADI_AXI_PCORE_VER_MAJOR(ver),
448 ADI_AXI_PCORE_VER_MINOR(ver),
449 ADI_AXI_PCORE_VER_PATCH(ver));
454 /* Match table for of_platform binding */
455 static const struct of_device_id adi_axi_adc_of_match[] = {
456 { .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info },
457 { /* end of list */ }
459 MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);
461 static struct platform_driver adi_axi_adc_driver = {
463 .name = KBUILD_MODNAME,
464 .of_match_table = adi_axi_adc_of_match,
466 .probe = adi_axi_adc_probe,
468 module_platform_driver(adi_axi_adc_driver);
470 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
471 MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver");
472 MODULE_LICENSE("GPL v2");