1 // SPDX-License-Identifier: GPL-2.0-only
3 * AD7904/AD7914/AD7923/AD7924/AD7908/AD7918/AD7928 SPI ADC driver
5 * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
6 * Copyright 2012 CS Systemes d'Information
9 #include <linux/device.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/sysfs.h>
13 #include <linux/spi/spi.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/err.h>
16 #include <linux/delay.h>
17 #include <linux/module.h>
18 #include <linux/interrupt.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/trigger_consumer.h>
24 #include <linux/iio/triggered_buffer.h>
26 #define AD7923_WRITE_CR BIT(11) /* write control register */
27 #define AD7923_RANGE BIT(1) /* range to REFin */
28 #define AD7923_CODING BIT(0) /* coding is straight binary */
29 #define AD7923_PM_MODE_AS (1) /* auto shutdown */
30 #define AD7923_PM_MODE_FS (2) /* full shutdown */
31 #define AD7923_PM_MODE_OPS (3) /* normal operation */
32 #define AD7923_SEQUENCE_OFF (0) /* no sequence fonction */
33 #define AD7923_SEQUENCE_PROTECT (2) /* no interrupt write cycle */
34 #define AD7923_SEQUENCE_ON (3) /* continuous sequence */
37 #define AD7923_PM_MODE_WRITE(mode) ((mode) << 4) /* write mode */
38 #define AD7923_CHANNEL_WRITE(channel) ((channel) << 6) /* write channel */
39 #define AD7923_SEQUENCE_WRITE(sequence) ((((sequence) & 1) << 3) \
40 + (((sequence) & 2) << 9))
41 /* write sequence fonction */
42 /* left shift for CR : bit 11 transmit in first */
43 #define AD7923_SHIFT_REGISTER 4
45 /* val = value, dec = left shift, bits = number of bits of the mask */
46 #define EXTRACT(val, dec, bits) (((val) >> (dec)) & ((1 << (bits)) - 1))
49 struct spi_device *spi;
50 struct spi_transfer ring_xfer[5];
51 struct spi_transfer scan_single_xfer[2];
52 struct spi_message ring_msg;
53 struct spi_message scan_single_msg;
55 struct regulator *reg;
57 unsigned int settings;
60 * DMA (thus cache coherency maintenance) may require the
61 * transfer buffers to live in their own cache lines.
62 * Ensure rx_buf can be directly used in iio_push_to_buffers_with_timetamp
63 * Length = 8 channels + 4 extra for 8 byte timestamp
65 __be16 rx_buf[12] __aligned(IIO_DMA_MINALIGN);
69 struct ad7923_chip_info {
70 const struct iio_chan_spec *channels;
71 unsigned int num_channels;
83 #define AD7923_V_CHAN(index, bits) \
85 .type = IIO_VOLTAGE, \
88 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
89 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
91 .scan_index = index, \
96 .endianness = IIO_BE, \
100 #define DECLARE_AD7923_CHANNELS(name, bits) \
101 const struct iio_chan_spec name ## _channels[] = { \
102 AD7923_V_CHAN(0, bits), \
103 AD7923_V_CHAN(1, bits), \
104 AD7923_V_CHAN(2, bits), \
105 AD7923_V_CHAN(3, bits), \
106 IIO_CHAN_SOFT_TIMESTAMP(4), \
109 #define DECLARE_AD7908_CHANNELS(name, bits) \
110 const struct iio_chan_spec name ## _channels[] = { \
111 AD7923_V_CHAN(0, bits), \
112 AD7923_V_CHAN(1, bits), \
113 AD7923_V_CHAN(2, bits), \
114 AD7923_V_CHAN(3, bits), \
115 AD7923_V_CHAN(4, bits), \
116 AD7923_V_CHAN(5, bits), \
117 AD7923_V_CHAN(6, bits), \
118 AD7923_V_CHAN(7, bits), \
119 IIO_CHAN_SOFT_TIMESTAMP(8), \
122 static DECLARE_AD7923_CHANNELS(ad7904, 8);
123 static DECLARE_AD7923_CHANNELS(ad7914, 10);
124 static DECLARE_AD7923_CHANNELS(ad7924, 12);
125 static DECLARE_AD7908_CHANNELS(ad7908, 8);
126 static DECLARE_AD7908_CHANNELS(ad7918, 10);
127 static DECLARE_AD7908_CHANNELS(ad7928, 12);
129 static const struct ad7923_chip_info ad7923_chip_info[] = {
131 .channels = ad7904_channels,
132 .num_channels = ARRAY_SIZE(ad7904_channels),
135 .channels = ad7914_channels,
136 .num_channels = ARRAY_SIZE(ad7914_channels),
139 .channels = ad7924_channels,
140 .num_channels = ARRAY_SIZE(ad7924_channels),
143 .channels = ad7908_channels,
144 .num_channels = ARRAY_SIZE(ad7908_channels),
147 .channels = ad7918_channels,
148 .num_channels = ARRAY_SIZE(ad7918_channels),
151 .channels = ad7928_channels,
152 .num_channels = ARRAY_SIZE(ad7928_channels),
157 * ad7923_update_scan_mode() setup the spi transfer buffer for the new scan mask
159 static int ad7923_update_scan_mode(struct iio_dev *indio_dev,
160 const unsigned long *active_scan_mask)
162 struct ad7923_state *st = iio_priv(indio_dev);
167 * For this driver the last channel is always the software timestamp so
170 for_each_set_bit(i, active_scan_mask, indio_dev->num_channels - 1) {
171 cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(i) |
172 AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
174 cmd <<= AD7923_SHIFT_REGISTER;
175 st->tx_buf[len++] = cpu_to_be16(cmd);
177 /* build spi ring message */
178 st->ring_xfer[0].tx_buf = &st->tx_buf[0];
179 st->ring_xfer[0].len = len;
180 st->ring_xfer[0].cs_change = 1;
182 spi_message_init(&st->ring_msg);
183 spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
185 for (i = 0; i < len; i++) {
186 st->ring_xfer[i + 1].rx_buf = &st->rx_buf[i];
187 st->ring_xfer[i + 1].len = 2;
188 st->ring_xfer[i + 1].cs_change = 1;
189 spi_message_add_tail(&st->ring_xfer[i + 1], &st->ring_msg);
191 /* make sure last transfer cs_change is not set */
192 st->ring_xfer[i + 1].cs_change = 0;
197 static irqreturn_t ad7923_trigger_handler(int irq, void *p)
199 struct iio_poll_func *pf = p;
200 struct iio_dev *indio_dev = pf->indio_dev;
201 struct ad7923_state *st = iio_priv(indio_dev);
204 b_sent = spi_sync(st->spi, &st->ring_msg);
208 iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
209 iio_get_time_ns(indio_dev));
212 iio_trigger_notify_done(indio_dev->trig);
217 static int ad7923_scan_direct(struct ad7923_state *st, unsigned int ch)
221 cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(ch) |
222 AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
224 cmd <<= AD7923_SHIFT_REGISTER;
225 st->tx_buf[0] = cpu_to_be16(cmd);
227 ret = spi_sync(st->spi, &st->scan_single_msg);
231 return be16_to_cpu(st->rx_buf[0]);
234 static int ad7923_get_range(struct ad7923_state *st)
238 vref = regulator_get_voltage(st->reg);
244 if (!(st->settings & AD7923_RANGE))
250 static int ad7923_read_raw(struct iio_dev *indio_dev,
251 struct iio_chan_spec const *chan,
257 struct ad7923_state *st = iio_priv(indio_dev);
260 case IIO_CHAN_INFO_RAW:
261 ret = iio_device_claim_direct_mode(indio_dev);
264 ret = ad7923_scan_direct(st, chan->address);
265 iio_device_release_direct_mode(indio_dev);
270 if (chan->address == EXTRACT(ret, 12, 4))
271 *val = EXTRACT(ret, 0, 12);
276 case IIO_CHAN_INFO_SCALE:
277 ret = ad7923_get_range(st);
281 *val2 = chan->scan_type.realbits;
282 return IIO_VAL_FRACTIONAL_LOG2;
287 static const struct iio_info ad7923_info = {
288 .read_raw = &ad7923_read_raw,
289 .update_scan_mode = ad7923_update_scan_mode,
292 static void ad7923_regulator_disable(void *data)
294 struct ad7923_state *st = data;
296 regulator_disable(st->reg);
299 static int ad7923_probe(struct spi_device *spi)
301 struct ad7923_state *st;
302 struct iio_dev *indio_dev;
303 const struct ad7923_chip_info *info;
306 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
310 st = iio_priv(indio_dev);
313 st->settings = AD7923_CODING | AD7923_RANGE |
314 AD7923_PM_MODE_WRITE(AD7923_PM_MODE_OPS);
316 info = &ad7923_chip_info[spi_get_device_id(spi)->driver_data];
318 indio_dev->name = spi_get_device_id(spi)->name;
319 indio_dev->modes = INDIO_DIRECT_MODE;
320 indio_dev->channels = info->channels;
321 indio_dev->num_channels = info->num_channels;
322 indio_dev->info = &ad7923_info;
324 /* Setup default message */
326 st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
327 st->scan_single_xfer[0].len = 2;
328 st->scan_single_xfer[0].cs_change = 1;
329 st->scan_single_xfer[1].rx_buf = &st->rx_buf[0];
330 st->scan_single_xfer[1].len = 2;
332 spi_message_init(&st->scan_single_msg);
333 spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
334 spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
336 st->reg = devm_regulator_get(&spi->dev, "refin");
338 return PTR_ERR(st->reg);
340 ret = regulator_enable(st->reg);
344 ret = devm_add_action_or_reset(&spi->dev, ad7923_regulator_disable, st);
348 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
349 &ad7923_trigger_handler, NULL);
353 return devm_iio_device_register(&spi->dev, indio_dev);
356 static const struct spi_device_id ad7923_id[] = {
366 MODULE_DEVICE_TABLE(spi, ad7923_id);
368 static const struct of_device_id ad7923_of_match[] = {
369 { .compatible = "adi,ad7904", },
370 { .compatible = "adi,ad7914", },
371 { .compatible = "adi,ad7923", },
372 { .compatible = "adi,ad7924", },
373 { .compatible = "adi,ad7908", },
374 { .compatible = "adi,ad7918", },
375 { .compatible = "adi,ad7928", },
378 MODULE_DEVICE_TABLE(of, ad7923_of_match);
380 static struct spi_driver ad7923_driver = {
383 .of_match_table = ad7923_of_match,
385 .probe = ad7923_probe,
386 .id_table = ad7923_id,
388 module_spi_driver(ad7923_driver);
390 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
391 MODULE_AUTHOR("Patrick Vasseur <patrick.vasseur@c-s.fr>");
392 MODULE_DESCRIPTION("Analog Devices AD7923 and similar ADC");
393 MODULE_LICENSE("GPL v2");