1 // SPDX-License-Identifier: GPL-2.0
3 * Analog Devices AD7466/7/8 AD7476/5/7/8 (A) SPI ADC driver
4 * TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver
6 * Copyright 2010 Analog Devices Inc.
9 #include <linux/device.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/sysfs.h>
13 #include <linux/spi/spi.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/err.h>
17 #include <linux/module.h>
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/trigger_consumer.h>
25 #include <linux/iio/triggered_buffer.h>
29 struct ad7476_chip_info {
30 unsigned int int_vref_uv;
31 struct iio_chan_spec channel[2];
32 /* channels used when convst gpio is defined */
33 struct iio_chan_spec convst_channel[2];
34 void (*reset)(struct ad7476_state *);
38 struct spi_device *spi;
39 const struct ad7476_chip_info *chip_info;
40 struct regulator *reg;
41 struct gpio_desc *convst_gpio;
42 struct spi_transfer xfer;
43 struct spi_message msg;
45 * DMA (thus cache coherency maintenance) requires the
46 * transfer buffers to live in their own cache lines.
47 * Make the buffer large enough for one 16 bit sample and one 64 bit
48 * aligned 64 bit timestamp.
50 unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)]
51 ____cacheline_aligned;
54 enum ad7476_supported_device_ids {
72 static void ad7091_convst(struct ad7476_state *st)
77 gpiod_set_value(st->convst_gpio, 0);
78 udelay(1); /* CONVST pulse width: 10 ns min */
79 gpiod_set_value(st->convst_gpio, 1);
80 udelay(1); /* Conversion time: 650 ns max */
83 static irqreturn_t ad7476_trigger_handler(int irq, void *p)
85 struct iio_poll_func *pf = p;
86 struct iio_dev *indio_dev = pf->indio_dev;
87 struct ad7476_state *st = iio_priv(indio_dev);
92 b_sent = spi_sync(st->spi, &st->msg);
96 iio_push_to_buffers_with_timestamp(indio_dev, st->data,
97 iio_get_time_ns(indio_dev));
99 iio_trigger_notify_done(indio_dev->trig);
104 static void ad7091_reset(struct ad7476_state *st)
106 /* Any transfers with 8 scl cycles will reset the device */
107 spi_read(st->spi, st->data, 1);
110 static int ad7476_scan_direct(struct ad7476_state *st)
116 ret = spi_sync(st->spi, &st->msg);
120 return be16_to_cpup((__be16 *)st->data);
123 static int ad7476_read_raw(struct iio_dev *indio_dev,
124 struct iio_chan_spec const *chan,
130 struct ad7476_state *st = iio_priv(indio_dev);
134 case IIO_CHAN_INFO_RAW:
135 ret = iio_device_claim_direct_mode(indio_dev);
138 ret = ad7476_scan_direct(st);
139 iio_device_release_direct_mode(indio_dev);
143 *val = (ret >> st->chip_info->channel[0].scan_type.shift) &
144 GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0);
146 case IIO_CHAN_INFO_SCALE:
147 if (!st->chip_info->int_vref_uv) {
148 scale_uv = regulator_get_voltage(st->reg);
152 scale_uv = st->chip_info->int_vref_uv;
154 *val = scale_uv / 1000;
155 *val2 = chan->scan_type.realbits;
156 return IIO_VAL_FRACTIONAL_LOG2;
161 #define _AD7476_CHAN(bits, _shift, _info_mask_sep) \
163 .type = IIO_VOLTAGE, \
165 .info_mask_separate = _info_mask_sep, \
166 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
169 .realbits = (bits), \
172 .endianness = IIO_BE, \
176 #define ADC081S_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
177 BIT(IIO_CHAN_INFO_RAW))
178 #define AD7476_CHAN(bits) _AD7476_CHAN((bits), 13 - (bits), \
179 BIT(IIO_CHAN_INFO_RAW))
180 #define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \
181 BIT(IIO_CHAN_INFO_RAW))
182 #define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0)
183 #define AD7091R_CONVST_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), \
184 BIT(IIO_CHAN_INFO_RAW))
185 #define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \
186 BIT(IIO_CHAN_INFO_RAW))
188 static const struct ad7476_chip_info ad7476_chip_info_tbl[] = {
190 .channel[0] = AD7091R_CHAN(12),
191 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
192 .convst_channel[0] = AD7091R_CONVST_CHAN(12),
193 .convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
194 .reset = ad7091_reset,
197 .channel[0] = AD7940_CHAN(12),
198 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
201 .channel[0] = AD7940_CHAN(10),
202 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
205 .channel[0] = AD7940_CHAN(8),
206 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
209 .channel[0] = AD7476_CHAN(12),
210 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
213 .channel[0] = AD7476_CHAN(10),
214 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
217 .channel[0] = AD7476_CHAN(8),
218 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
221 .channel[0] = AD7476_CHAN(12),
222 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
223 .int_vref_uv = 2500000,
226 .channel[0] = AD7940_CHAN(14),
227 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
230 .channel[0] = ADC081S_CHAN(8),
231 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
234 .channel[0] = ADC081S_CHAN(10),
235 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
238 .channel[0] = ADC081S_CHAN(12),
239 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
242 .channel[0] = ADS786X_CHAN(12),
243 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
246 .channel[0] = ADS786X_CHAN(10),
247 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
250 .channel[0] = ADS786X_CHAN(8),
251 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
255 static const struct iio_info ad7476_info = {
256 .read_raw = &ad7476_read_raw,
259 static void ad7476_reg_disable(void *data)
261 struct ad7476_state *st = data;
263 regulator_disable(st->reg);
266 static int ad7476_probe(struct spi_device *spi)
268 struct ad7476_state *st;
269 struct iio_dev *indio_dev;
272 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
276 st = iio_priv(indio_dev);
278 &ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data];
280 st->reg = devm_regulator_get(&spi->dev, "vcc");
282 return PTR_ERR(st->reg);
284 ret = regulator_enable(st->reg);
288 ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable,
293 st->convst_gpio = devm_gpiod_get_optional(&spi->dev,
294 "adi,conversion-start",
296 if (IS_ERR(st->convst_gpio))
297 return PTR_ERR(st->convst_gpio);
299 spi_set_drvdata(spi, indio_dev);
303 indio_dev->name = spi_get_device_id(spi)->name;
304 indio_dev->modes = INDIO_DIRECT_MODE;
305 indio_dev->channels = st->chip_info->channel;
306 indio_dev->num_channels = 2;
307 indio_dev->info = &ad7476_info;
310 indio_dev->channels = st->chip_info->convst_channel;
311 /* Setup default message */
313 st->xfer.rx_buf = &st->data;
314 st->xfer.len = st->chip_info->channel[0].scan_type.storagebits / 8;
316 spi_message_init(&st->msg);
317 spi_message_add_tail(&st->xfer, &st->msg);
319 ret = iio_triggered_buffer_setup(indio_dev, NULL,
320 &ad7476_trigger_handler, NULL);
322 goto error_disable_reg;
324 if (st->chip_info->reset)
325 st->chip_info->reset(st);
327 ret = iio_device_register(indio_dev);
329 goto error_ring_unregister;
332 error_ring_unregister:
333 iio_triggered_buffer_cleanup(indio_dev);
335 regulator_disable(st->reg);
340 static const struct spi_device_id ad7476_id[] = {
341 {"ad7091", ID_AD7091R},
342 {"ad7091r", ID_AD7091R},
343 {"ad7273", ID_AD7277},
344 {"ad7274", ID_AD7276},
345 {"ad7276", ID_AD7276},
346 {"ad7277", ID_AD7277},
347 {"ad7278", ID_AD7278},
348 {"ad7466", ID_AD7466},
349 {"ad7467", ID_AD7467},
350 {"ad7468", ID_AD7468},
351 {"ad7475", ID_AD7466},
352 {"ad7476", ID_AD7466},
353 {"ad7476a", ID_AD7466},
354 {"ad7477", ID_AD7467},
355 {"ad7477a", ID_AD7467},
356 {"ad7478", ID_AD7468},
357 {"ad7478a", ID_AD7468},
358 {"ad7495", ID_AD7495},
359 {"ad7910", ID_AD7467},
360 {"ad7920", ID_AD7466},
361 {"ad7940", ID_AD7940},
362 {"adc081s", ID_ADC081S},
363 {"adc101s", ID_ADC101S},
364 {"adc121s", ID_ADC121S},
365 {"ads7866", ID_ADS7866},
366 {"ads7867", ID_ADS7867},
367 {"ads7868", ID_ADS7868},
370 MODULE_DEVICE_TABLE(spi, ad7476_id);
372 static struct spi_driver ad7476_driver = {
376 .probe = ad7476_probe,
377 .id_table = ad7476_id,
379 module_spi_driver(ad7476_driver);
381 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
382 MODULE_DESCRIPTION("Analog Devices AD7476 and similar 1-channel ADCs");
383 MODULE_LICENSE("GPL v2");