1 // SPDX-License-Identifier: GPL-2.0+
3 * AD7124 SPI ADC driver
5 * Copyright 2018 Analog Devices Inc.
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/kfifo.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/spi/spi.h>
21 #include <linux/iio/iio.h>
22 #include <linux/iio/adc/ad_sigma_delta.h>
23 #include <linux/iio/sysfs.h>
25 /* AD7124 registers */
26 #define AD7124_COMMS 0x00
27 #define AD7124_STATUS 0x00
28 #define AD7124_ADC_CONTROL 0x01
29 #define AD7124_DATA 0x02
30 #define AD7124_IO_CONTROL_1 0x03
31 #define AD7124_IO_CONTROL_2 0x04
32 #define AD7124_ID 0x05
33 #define AD7124_ERROR 0x06
34 #define AD7124_ERROR_EN 0x07
35 #define AD7124_MCLK_COUNT 0x08
36 #define AD7124_CHANNEL(x) (0x09 + (x))
37 #define AD7124_CONFIG(x) (0x19 + (x))
38 #define AD7124_FILTER(x) (0x21 + (x))
39 #define AD7124_OFFSET(x) (0x29 + (x))
40 #define AD7124_GAIN(x) (0x31 + (x))
43 #define AD7124_STATUS_POR_FLAG_MSK BIT(4)
45 /* AD7124_ADC_CONTROL */
46 #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8)
47 #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
48 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
49 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
50 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
51 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
54 #define AD7124_DEVICE_ID_MSK GENMASK(7, 4)
55 #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x)
56 #define AD7124_SILICON_REV_MSK GENMASK(3, 0)
57 #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x)
59 #define CHIPID_AD7124_4 0x0
60 #define CHIPID_AD7124_8 0x1
62 /* AD7124_CHANNEL_X */
63 #define AD7124_CHANNEL_EN_MSK BIT(15)
64 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
65 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
66 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
67 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
68 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
69 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
70 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
73 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
74 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
75 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
76 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
77 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
78 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
79 #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(6, 5)
80 #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
83 #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
84 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
85 #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21)
86 #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
88 #define AD7124_SINC3_FILTER 2
89 #define AD7124_SINC4_FILTER 0
91 #define AD7124_CONF_ADDR_OFFSET 20
92 #define AD7124_MAX_CONFIGS 8
93 #define AD7124_MAX_CHANNELS 16
100 enum ad7124_ref_sel {
107 enum ad7124_power_mode {
113 static const unsigned int ad7124_gain[8] = {
114 1, 2, 4, 8, 16, 32, 64, 128
117 static const unsigned int ad7124_reg_size[] = {
118 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
119 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
120 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
121 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
125 static const int ad7124_master_clk_freq_hz[3] = {
126 [AD7124_LOW_POWER] = 76800,
127 [AD7124_MID_POWER] = 153600,
128 [AD7124_FULL_POWER] = 614400,
131 static const char * const ad7124_ref_names[] = {
132 [AD7124_REFIN1] = "refin1",
133 [AD7124_REFIN2] = "refin2",
134 [AD7124_INT_REF] = "int",
135 [AD7124_AVDD_REF] = "avdd",
138 struct ad7124_chip_info {
140 unsigned int chip_id;
141 unsigned int num_inputs;
144 struct ad7124_channel_config {
146 unsigned int cfg_slot;
147 enum ad7124_ref_sel refsel;
151 unsigned int vref_mv;
152 unsigned int pga_bits;
154 unsigned int odr_sel_bits;
155 unsigned int filter_type;
158 struct ad7124_channel {
160 struct ad7124_channel_config cfg;
165 struct ad7124_state {
166 const struct ad7124_chip_info *chip_info;
167 struct ad_sigma_delta sd;
168 struct ad7124_channel *channels;
169 struct regulator *vref[4];
171 unsigned int adc_control;
172 unsigned int num_channels;
173 struct mutex cfgs_lock; /* lock for configs access */
174 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */
175 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS);
178 static const struct iio_chan_spec ad7124_channel_template = {
182 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
183 BIT(IIO_CHAN_INFO_SCALE) |
184 BIT(IIO_CHAN_INFO_OFFSET) |
185 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
186 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
192 .endianness = IIO_BE,
196 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
199 .chip_id = CHIPID_AD7124_4,
204 .chip_id = CHIPID_AD7124_8,
209 static int ad7124_find_closest_match(const int *array,
210 unsigned int size, int val)
213 unsigned int diff_new, diff_old;
218 for (i = 0; i < size; i++) {
219 diff_new = abs(val - array[i]);
220 if (diff_new < diff_old) {
229 static int ad7124_spi_write_mask(struct ad7124_state *st,
235 unsigned int readval;
238 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
245 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
248 static int ad7124_set_mode(struct ad_sigma_delta *sd,
249 enum ad_sigma_delta_mode mode)
251 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
253 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
254 st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
256 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
259 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr)
261 unsigned int fclk, odr_sel_bits;
263 fclk = clk_get_rate(st->mclk);
265 * FS[10:0] = fCLK / (fADC x 32) where:
266 * fADC is the output data rate
267 * fCLK is the master clock frequency
268 * FS[10:0] are the bits in the filter register
269 * FS[10:0] can have a value from 1 to 2047
271 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
272 if (odr_sel_bits < 1)
274 else if (odr_sel_bits > 2047)
277 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits)
278 st->channels[channel].cfg.live = false;
280 /* fADC = fCLK / (FS[10:0] x 32) */
281 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
282 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
285 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
286 unsigned int channel)
290 fadc = st->channels[channel].cfg.odr;
292 switch (st->channels[channel].cfg.filter_type) {
293 case AD7124_SINC3_FILTER:
294 return DIV_ROUND_CLOSEST(fadc * 230, 1000);
295 case AD7124_SINC4_FILTER:
296 return DIV_ROUND_CLOSEST(fadc * 262, 1000);
302 static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel,
305 unsigned int sinc4_3db_odr;
306 unsigned int sinc3_3db_odr;
307 unsigned int new_filter;
308 unsigned int new_odr;
310 sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
311 sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
313 if (sinc4_3db_odr > sinc3_3db_odr) {
314 new_filter = AD7124_SINC3_FILTER;
315 new_odr = sinc4_3db_odr;
317 new_filter = AD7124_SINC4_FILTER;
318 new_odr = sinc3_3db_odr;
321 if (new_odr != st->channels[channel].cfg.odr)
322 st->channels[channel].cfg.live = false;
324 st->channels[channel].cfg.filter_type = new_filter;
325 st->channels[channel].cfg.odr = new_odr;
328 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st,
329 struct ad7124_channel_config *cfg)
331 struct ad7124_channel_config *cfg_aux;
335 cmp_size = (u8 *)&cfg->live - (u8 *)cfg;
336 for (i = 0; i < st->num_channels; i++) {
337 cfg_aux = &st->channels[i].cfg;
339 if (cfg_aux->live && !memcmp(cfg, cfg_aux, cmp_size))
346 static int ad7124_find_free_config_slot(struct ad7124_state *st)
348 unsigned int free_cfg_slot;
350 free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS);
351 if (free_cfg_slot == AD7124_MAX_CONFIGS)
354 return free_cfg_slot;
357 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
359 unsigned int refsel = cfg->refsel;
364 case AD7124_AVDD_REF:
365 if (IS_ERR(st->vref[refsel])) {
366 dev_err(&st->sd.spi->dev,
367 "Error, trying to use external voltage reference without a %s regulator.\n",
368 ad7124_ref_names[refsel]);
369 return PTR_ERR(st->vref[refsel]);
371 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
372 /* Conversion from uV to mV */
373 cfg->vref_mv /= 1000;
377 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
378 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
379 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
382 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
387 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
388 unsigned int cfg_slot)
394 cfg->cfg_slot = cfg_slot;
396 tmp = (cfg->buf_positive << 1) + cfg->buf_negative;
397 val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) |
398 AD7124_CONFIG_IN_BUFF(tmp);
399 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val);
403 tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type);
404 ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_TYPE_MSK,
409 ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_FS_MSK,
410 AD7124_FILTER_FS(cfg->odr_sel_bits), 3);
414 return ad7124_spi_write_mask(st, AD7124_CONFIG(cfg->cfg_slot), AD7124_CONFIG_PGA_MSK,
415 AD7124_CONFIG_PGA(cfg->pga_bits), 2);
418 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st)
420 struct ad7124_channel_config *lru_cfg;
421 struct ad7124_channel_config *cfg;
426 * Pop least recently used config from the fifo
427 * in order to make room for the new one
429 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg);
433 lru_cfg->live = false;
435 /* mark slot as free */
436 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0);
438 /* invalidate all other configs that pointed to this one */
439 for (i = 0; i < st->num_channels; i++) {
440 cfg = &st->channels[i].cfg;
442 if (cfg->cfg_slot == lru_cfg->cfg_slot)
449 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg)
451 struct ad7124_channel_config *lru_cfg;
454 free_cfg_slot = ad7124_find_free_config_slot(st);
455 if (free_cfg_slot >= 0) {
456 /* push the new config in configs queue */
457 kfifo_put(&st->live_cfgs_fifo, cfg);
459 /* pop one config to make room for the new one */
460 lru_cfg = ad7124_pop_config(st);
464 /* push the new config in configs queue */
465 free_cfg_slot = lru_cfg->cfg_slot;
466 kfifo_put(&st->live_cfgs_fifo, cfg);
469 /* mark slot as used */
470 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1);
472 return ad7124_write_config(st, cfg, free_cfg_slot);
475 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch)
478 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain |
479 AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1));
482 static int ad7124_prepare_read(struct ad7124_state *st, int address)
484 struct ad7124_channel_config *cfg = &st->channels[address].cfg;
485 struct ad7124_channel_config *live_cfg;
488 * Before doing any reads assign the channel a configuration.
489 * Check if channel's config is on the device
492 /* check if config matches another one */
493 live_cfg = ad7124_find_similar_live_cfg(st, cfg);
495 ad7124_push_config(st, cfg);
497 cfg->cfg_slot = live_cfg->cfg_slot;
500 /* point channel to the config slot and enable */
501 return ad7124_enable_channel(st, &st->channels[address]);
504 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
506 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
509 mutex_lock(&st->cfgs_lock);
510 ret = ad7124_prepare_read(st, channel);
511 mutex_unlock(&st->cfgs_lock);
516 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
517 .set_channel = ad7124_set_channel,
518 .set_mode = ad7124_set_mode,
519 .has_registers = true,
522 .data_reg = AD7124_DATA,
523 .irq_flags = IRQF_TRIGGER_FALLING
526 static int ad7124_read_raw(struct iio_dev *indio_dev,
527 struct iio_chan_spec const *chan,
528 int *val, int *val2, long info)
530 struct ad7124_state *st = iio_priv(indio_dev);
534 case IIO_CHAN_INFO_RAW:
535 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
539 /* After the conversion is performed, disable the channel */
540 ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan->address), 2,
541 st->channels[chan->address].ain | AD7124_CHANNEL_EN(0));
546 case IIO_CHAN_INFO_SCALE:
547 mutex_lock(&st->cfgs_lock);
549 idx = st->channels[chan->address].cfg.pga_bits;
550 *val = st->channels[chan->address].cfg.vref_mv;
551 if (st->channels[chan->address].cfg.bipolar)
552 *val2 = chan->scan_type.realbits - 1 + idx;
554 *val2 = chan->scan_type.realbits + idx;
556 mutex_unlock(&st->cfgs_lock);
557 return IIO_VAL_FRACTIONAL_LOG2;
558 case IIO_CHAN_INFO_OFFSET:
559 mutex_lock(&st->cfgs_lock);
560 if (st->channels[chan->address].cfg.bipolar)
561 *val = -(1 << (chan->scan_type.realbits - 1));
565 mutex_unlock(&st->cfgs_lock);
567 case IIO_CHAN_INFO_SAMP_FREQ:
568 mutex_lock(&st->cfgs_lock);
569 *val = st->channels[chan->address].cfg.odr;
570 mutex_unlock(&st->cfgs_lock);
573 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
574 mutex_lock(&st->cfgs_lock);
575 *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
576 mutex_unlock(&st->cfgs_lock);
584 static int ad7124_write_raw(struct iio_dev *indio_dev,
585 struct iio_chan_spec const *chan,
586 int val, int val2, long info)
588 struct ad7124_state *st = iio_priv(indio_dev);
589 unsigned int res, gain, full_scale, vref;
592 mutex_lock(&st->cfgs_lock);
595 case IIO_CHAN_INFO_SAMP_FREQ:
601 ad7124_set_channel_odr(st, chan->address, val);
603 case IIO_CHAN_INFO_SCALE:
609 if (st->channels[chan->address].cfg.bipolar)
610 full_scale = 1 << (chan->scan_type.realbits - 1);
612 full_scale = 1 << chan->scan_type.realbits;
614 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
615 res = DIV_ROUND_CLOSEST(vref, full_scale);
616 gain = DIV_ROUND_CLOSEST(res, val2);
617 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
619 if (st->channels[chan->address].cfg.pga_bits != res)
620 st->channels[chan->address].cfg.live = false;
622 st->channels[chan->address].cfg.pga_bits = res;
624 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
630 ad7124_set_3db_filter_freq(st, chan->address, val);
636 mutex_unlock(&st->cfgs_lock);
640 static int ad7124_reg_access(struct iio_dev *indio_dev,
642 unsigned int writeval,
643 unsigned int *readval)
645 struct ad7124_state *st = iio_priv(indio_dev);
648 if (reg >= ARRAY_SIZE(ad7124_reg_size))
652 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
655 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
661 static IIO_CONST_ATTR(in_voltage_scale_available,
662 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
664 static struct attribute *ad7124_attributes[] = {
665 &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
669 static const struct attribute_group ad7124_attrs_group = {
670 .attrs = ad7124_attributes,
673 static const struct iio_info ad7124_info = {
674 .read_raw = ad7124_read_raw,
675 .write_raw = ad7124_write_raw,
676 .debugfs_reg_access = &ad7124_reg_access,
677 .validate_trigger = ad_sd_validate_trigger,
678 .attrs = &ad7124_attrs_group,
681 static int ad7124_soft_reset(struct ad7124_state *st)
683 unsigned int readval, timeout;
686 ret = ad_sd_reset(&st->sd, 64);
692 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
696 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
699 /* The AD7124 requires typically 2ms to power up and settle */
700 usleep_range(100, 2000);
703 dev_err(&st->sd.spi->dev, "Soft reset failed\n");
708 static int ad7124_check_chip_id(struct ad7124_state *st)
710 unsigned int readval, chip_id, silicon_rev;
713 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
717 chip_id = AD7124_DEVICE_ID_GET(readval);
718 silicon_rev = AD7124_SILICON_REV_GET(readval);
720 if (chip_id != st->chip_info->chip_id) {
721 dev_err(&st->sd.spi->dev,
722 "Chip ID mismatch: expected %u, got %u\n",
723 st->chip_info->chip_id, chip_id);
727 if (silicon_rev == 0) {
728 dev_err(&st->sd.spi->dev,
729 "Silicon revision empty. Chip may not be present\n");
736 static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
737 struct device_node *np)
739 struct ad7124_state *st = iio_priv(indio_dev);
740 struct ad7124_channel_config *cfg;
741 struct ad7124_channel *channels;
742 struct device_node *child;
743 struct iio_chan_spec *chan;
744 unsigned int ain[2], channel = 0, tmp;
747 st->num_channels = of_get_available_child_count(np);
748 if (!st->num_channels) {
749 dev_err(indio_dev->dev.parent, "no channel children\n");
753 chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
754 sizeof(*chan), GFP_KERNEL);
758 channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels),
763 indio_dev->channels = chan;
764 indio_dev->num_channels = st->num_channels;
765 st->channels = channels;
767 for_each_available_child_of_node(np, child) {
768 cfg = &st->channels[channel].cfg;
770 ret = of_property_read_u32(child, "reg", &channel);
774 if (channel >= indio_dev->num_channels) {
775 dev_err(indio_dev->dev.parent,
776 "Channel index >= number of channels\n");
781 ret = of_property_read_u32_array(child, "diff-channels",
786 st->channels[channel].nr = channel;
787 st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
788 AD7124_CHANNEL_AINM(ain[1]);
790 cfg->bipolar = of_property_read_bool(child, "bipolar");
792 ret = of_property_read_u32(child, "adi,reference-select", &tmp);
794 cfg->refsel = AD7124_INT_REF;
798 cfg->buf_positive = of_property_read_bool(child, "adi,buffered-positive");
799 cfg->buf_negative = of_property_read_bool(child, "adi,buffered-negative");
801 chan[channel] = ad7124_channel_template;
802 chan[channel].address = channel;
803 chan[channel].scan_index = channel;
804 chan[channel].channel = ain[0];
805 chan[channel].channel2 = ain[1];
815 static int ad7124_setup(struct ad7124_state *st)
817 unsigned int fclk, power_mode;
820 fclk = clk_get_rate(st->mclk);
824 /* The power mode changes the master clock frequency */
825 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
826 ARRAY_SIZE(ad7124_master_clk_freq_hz),
828 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
829 ret = clk_set_rate(st->mclk, fclk);
834 /* Set the power mode */
835 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
836 st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
837 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
841 mutex_init(&st->cfgs_lock);
842 INIT_KFIFO(st->live_cfgs_fifo);
843 for (i = 0; i < st->num_channels; i++) {
845 ret = ad7124_init_config_vref(st, &st->channels[i].cfg);
850 * 9.38 SPS is the minimum output data rate supported
851 * regardless of the selected power mode. Round it up to 10 and
852 * set all channels to this default value.
854 ad7124_set_channel_odr(st, i, 10);
860 static void ad7124_reg_disable(void *r)
862 regulator_disable(r);
865 static void ad7124_clk_disable(void *c)
867 clk_disable_unprepare(c);
870 static int ad7124_probe(struct spi_device *spi)
872 const struct ad7124_chip_info *info;
873 struct ad7124_state *st;
874 struct iio_dev *indio_dev;
877 info = of_device_get_match_data(&spi->dev);
881 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
885 st = iio_priv(indio_dev);
887 st->chip_info = info;
889 ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
891 indio_dev->name = st->chip_info->name;
892 indio_dev->modes = INDIO_DIRECT_MODE;
893 indio_dev->info = &ad7124_info;
895 ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
899 for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
900 if (i == AD7124_INT_REF)
903 st->vref[i] = devm_regulator_get_optional(&spi->dev,
904 ad7124_ref_names[i]);
905 if (PTR_ERR(st->vref[i]) == -ENODEV)
907 else if (IS_ERR(st->vref[i]))
908 return PTR_ERR(st->vref[i]);
910 ret = regulator_enable(st->vref[i]);
914 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
920 st->mclk = devm_clk_get(&spi->dev, "mclk");
921 if (IS_ERR(st->mclk))
922 return PTR_ERR(st->mclk);
924 ret = clk_prepare_enable(st->mclk);
928 ret = devm_add_action_or_reset(&spi->dev, ad7124_clk_disable, st->mclk);
932 ret = ad7124_soft_reset(st);
936 ret = ad7124_check_chip_id(st);
940 ret = ad7124_setup(st);
944 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
948 return devm_iio_device_register(&spi->dev, indio_dev);
952 static const struct of_device_id ad7124_of_match[] = {
953 { .compatible = "adi,ad7124-4",
954 .data = &ad7124_chip_info_tbl[ID_AD7124_4], },
955 { .compatible = "adi,ad7124-8",
956 .data = &ad7124_chip_info_tbl[ID_AD7124_8], },
959 MODULE_DEVICE_TABLE(of, ad7124_of_match);
961 static struct spi_driver ad71124_driver = {
964 .of_match_table = ad7124_of_match,
966 .probe = ad7124_probe,
968 module_spi_driver(ad71124_driver);
970 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
971 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
972 MODULE_LICENSE("GPL");