drivers/iio/adc/ad4130.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2022 Analog Devices, Inc.
   4  * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
   5  */
   6
   7 #include <linux/bitfield.h>
   8 #include <linux/bitops.h>
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/delay.h>
  12 #include <linux/device.h>
  13 #include <linux/err.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/property.h>
  20 #include <linux/regmap.h>
  21 #include <linux/regulator/consumer.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/units.h>
  24
  25 #include <asm/div64.h>
  26 #include <asm/unaligned.h>
  27
  28 #include <linux/iio/buffer.h>
  29 #include <linux/iio/iio.h>
  30 #include <linux/iio/kfifo_buf.h>
  31 #include <linux/iio/sysfs.h>
  32
  33 #define AD4130_NAME                             "ad4130"
  34
  35 #define AD4130_COMMS_READ_MASK                  BIT(6)
  36
  37 #define AD4130_STATUS_REG                       0x00
  38
  39 #define AD4130_ADC_CONTROL_REG                  0x01
  40 #define AD4130_ADC_CONTROL_BIPOLAR_MASK         BIT(14)
  41 #define AD4130_ADC_CONTROL_INT_REF_VAL_MASK     BIT(13)
  42 #define AD4130_INT_REF_2_5V                     2500000
  43 #define AD4130_INT_REF_1_25V                    1250000
  44 #define AD4130_ADC_CONTROL_CSB_EN_MASK          BIT(9)
  45 #define AD4130_ADC_CONTROL_INT_REF_EN_MASK      BIT(8)
  46 #define AD4130_ADC_CONTROL_MODE_MASK            GENMASK(5, 2)
  47 #define AD4130_ADC_CONTROL_MCLK_SEL_MASK        GENMASK(1, 0)
  48 #define AD4130_MCLK_FREQ_76_8KHZ                76800
  49 #define AD4130_MCLK_FREQ_153_6KHZ               153600
  50
  51 #define AD4130_DATA_REG                         0x02
  52
  53 #define AD4130_IO_CONTROL_REG                   0x03
  54 #define AD4130_IO_CONTROL_INT_PIN_SEL_MASK      GENMASK(9, 8)
  55 #define AD4130_IO_CONTROL_GPIO_DATA_MASK        GENMASK(7, 4)
  56 #define AD4130_IO_CONTROL_GPIO_CTRL_MASK        GENMASK(3, 0)
  57
  58 #define AD4130_VBIAS_REG                        0x04
  59
  60 #define AD4130_ID_REG                           0x05
  61
  62 #define AD4130_ERROR_REG                        0x06
  63
  64 #define AD4130_ERROR_EN_REG                     0x07
  65
  66 #define AD4130_MCLK_COUNT_REG                   0x08
  67
  68 #define AD4130_CHANNEL_X_REG(x)                 (0x09 + (x))
  69 #define AD4130_CHANNEL_EN_MASK                  BIT(23)
  70 #define AD4130_CHANNEL_SETUP_MASK               GENMASK(22, 20)
  71 #define AD4130_CHANNEL_AINP_MASK                GENMASK(17, 13)
  72 #define AD4130_CHANNEL_AINM_MASK                GENMASK(12, 8)
  73 #define AD4130_CHANNEL_IOUT1_MASK               GENMASK(7, 4)
  74 #define AD4130_CHANNEL_IOUT2_MASK               GENMASK(3, 0)
  75
  76 #define AD4130_CONFIG_X_REG(x)                  (0x19 + (x))
  77 #define AD4130_CONFIG_IOUT1_VAL_MASK            GENMASK(15, 13)
  78 #define AD4130_CONFIG_IOUT2_VAL_MASK            GENMASK(12, 10)
  79 #define AD4130_CONFIG_BURNOUT_MASK              GENMASK(9, 8)
  80 #define AD4130_CONFIG_REF_BUFP_MASK             BIT(7)
  81 #define AD4130_CONFIG_REF_BUFM_MASK             BIT(6)
  82 #define AD4130_CONFIG_REF_SEL_MASK              GENMASK(5, 4)
  83 #define AD4130_CONFIG_PGA_MASK                  GENMASK(3, 1)
  84
  85 #define AD4130_FILTER_X_REG(x)                  (0x21 + (x))
  86 #define AD4130_FILTER_MODE_MASK                 GENMASK(15, 12)
  87 #define AD4130_FILTER_SELECT_MASK               GENMASK(10, 0)
  88 #define AD4130_FILTER_SELECT_MIN                1
  89
  90 #define AD4130_OFFSET_X_REG(x)                  (0x29 + (x))
  91
  92 #define AD4130_GAIN_X_REG(x)                    (0x31 + (x))
  93
  94 #define AD4130_MISC_REG                         0x39
  95
  96 #define AD4130_FIFO_CONTROL_REG                 0x3a
  97 #define AD4130_FIFO_CONTROL_HEADER_MASK         BIT(18)
  98 #define AD4130_FIFO_CONTROL_MODE_MASK           GENMASK(17, 16)
  99 #define AD4130_FIFO_CONTROL_WM_INT_EN_MASK      BIT(9)
 100 #define AD4130_FIFO_CONTROL_WM_MASK             GENMASK(7, 0)
 101 #define AD4130_WATERMARK_256                    0
 102
 103 #define AD4130_FIFO_STATUS_REG                  0x3b
 104
 105 #define AD4130_FIFO_THRESHOLD_REG               0x3c
 106
 107 #define AD4130_FIFO_DATA_REG                    0x3d
 108 #define AD4130_FIFO_SIZE                        256
 109 #define AD4130_FIFO_MAX_SAMPLE_SIZE             3
 110
 111 #define AD4130_MAX_ANALOG_PINS                  16
 112 #define AD4130_MAX_CHANNELS                     16
 113 #define AD4130_MAX_DIFF_INPUTS                  30
 114 #define AD4130_MAX_GPIOS                        4
 115 #define AD4130_MAX_ODR                          2400
 116 #define AD4130_MAX_PGA                          8
 117 #define AD4130_MAX_SETUPS                       8
 118
 119 #define AD4130_AIN2_P1                          0x2
 120 #define AD4130_AIN3_P2                          0x3
 121
 122 #define AD4130_RESET_BUF_SIZE                   8
 123 #define AD4130_RESET_SLEEP_US                   (160 * MICRO / AD4130_MCLK_FREQ_76_8KHZ)
 124
 125 #define AD4130_INVALID_SLOT                     -1
 126
 127 static const unsigned int ad4130_reg_size[] = {
 128         [AD4130_STATUS_REG] = 1,
 129         [AD4130_ADC_CONTROL_REG] = 2,
 130         [AD4130_DATA_REG] = 3,
 131         [AD4130_IO_CONTROL_REG] = 2,
 132         [AD4130_VBIAS_REG] = 2,
 133         [AD4130_ID_REG] = 1,
 134         [AD4130_ERROR_REG] = 2,
 135         [AD4130_ERROR_EN_REG] = 2,
 136         [AD4130_MCLK_COUNT_REG] = 1,
 137         [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3,
 138         [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2,
 139         [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
 140         [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
 141         [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
 142         [AD4130_MISC_REG] = 2,
 143         [AD4130_FIFO_CONTROL_REG] = 3,
 144         [AD4130_FIFO_STATUS_REG] = 1,
 145         [AD4130_FIFO_THRESHOLD_REG] = 3,
 146         [AD4130_FIFO_DATA_REG] = 3,
 147 };
 148
 149 enum ad4130_int_ref_val {
 150         AD4130_INT_REF_VAL_2_5V,
 151         AD4130_INT_REF_VAL_1_25V,
 152 };
 153
 154 enum ad4130_mclk_sel {
 155         AD4130_MCLK_76_8KHZ,
 156         AD4130_MCLK_76_8KHZ_OUT,
 157         AD4130_MCLK_76_8KHZ_EXT,
 158         AD4130_MCLK_153_6KHZ_EXT,
 159 };
 160
 161 enum ad4130_int_pin_sel {
 162         AD4130_INT_PIN_INT,
 163         AD4130_INT_PIN_CLK,
 164         AD4130_INT_PIN_P2,
 165         AD4130_INT_PIN_DOUT,
 166 };
 167
 168 enum ad4130_iout {
 169         AD4130_IOUT_OFF,
 170         AD4130_IOUT_10000NA,
 171         AD4130_IOUT_20000NA,
 172         AD4130_IOUT_50000NA,
 173         AD4130_IOUT_100000NA,
 174         AD4130_IOUT_150000NA,
 175         AD4130_IOUT_200000NA,
 176         AD4130_IOUT_100NA,
 177         AD4130_IOUT_MAX
 178 };
 179
 180 enum ad4130_burnout {
 181         AD4130_BURNOUT_OFF,
 182         AD4130_BURNOUT_500NA,
 183         AD4130_BURNOUT_2000NA,
 184         AD4130_BURNOUT_4000NA,
 185         AD4130_BURNOUT_MAX
 186 };
 187
 188 enum ad4130_ref_sel {
 189         AD4130_REF_REFIN1,
 190         AD4130_REF_REFIN2,
 191         AD4130_REF_REFOUT_AVSS,
 192         AD4130_REF_AVDD_AVSS,
 193         AD4130_REF_SEL_MAX
 194 };
 195
 196 enum ad4130_fifo_mode {
 197         AD4130_FIFO_MODE_DISABLED = 0b00,
 198         AD4130_FIFO_MODE_WM = 0b01,
 199 };
 200
 201 enum ad4130_mode {
 202         AD4130_MODE_CONTINUOUS = 0b0000,
 203         AD4130_MODE_IDLE = 0b0100,
 204 };
 205
 206 enum ad4130_filter_mode {
 207         AD4130_FILTER_SINC4,
 208         AD4130_FILTER_SINC4_SINC1,
 209         AD4130_FILTER_SINC3,
 210         AD4130_FILTER_SINC3_REJ60,
 211         AD4130_FILTER_SINC3_SINC1,
 212         AD4130_FILTER_SINC3_PF1,
 213         AD4130_FILTER_SINC3_PF2,
 214         AD4130_FILTER_SINC3_PF3,
 215         AD4130_FILTER_SINC3_PF4,
 216 };
 217
 218 enum ad4130_pin_function {
 219         AD4130_PIN_FN_NONE,
 220         AD4130_PIN_FN_SPECIAL = BIT(0),
 221         AD4130_PIN_FN_DIFF = BIT(1),
 222         AD4130_PIN_FN_EXCITATION = BIT(2),
 223         AD4130_PIN_FN_VBIAS = BIT(3),
 224 };
 225
 226 struct ad4130_setup_info {
 227         unsigned int                    iout0_val;
 228         unsigned int                    iout1_val;
 229         unsigned int                    burnout;
 230         unsigned int                    pga;
 231         unsigned int                    fs;
 232         u32                             ref_sel;
 233         enum ad4130_filter_mode         filter_mode;
 234         bool                            ref_bufp;
 235         bool                            ref_bufm;
 236 };
 237
 238 struct ad4130_slot_info {
 239         struct ad4130_setup_info        setup;
 240         unsigned int                    enabled_channels;
 241         unsigned int                    channels;
 242 };
 243
 244 struct ad4130_chan_info {
 245         struct ad4130_setup_info        setup;
 246         u32                             iout0;
 247         u32                             iout1;
 248         int                             slot;
 249         bool                            enabled;
 250         bool                            initialized;
 251 };
 252
 253 struct ad4130_filter_config {
 254         enum ad4130_filter_mode         filter_mode;
 255         unsigned int                    odr_div;
 256         unsigned int                    fs_max;
 257         enum iio_available_type         samp_freq_avail_type;
 258         int                             samp_freq_avail_len;
 259         int                             samp_freq_avail[3][2];
 260 };
 261
 262 struct ad4130_state {
 263         struct regmap                   *regmap;
 264         struct spi_device               *spi;
 265         struct clk                      *mclk;
 266         struct regulator_bulk_data      regulators[4];
 267         u32                             irq_trigger;
 268         u32                             inv_irq_trigger;
 269
 270         /*
 271          * Synchronize access to members the of driver state, and ensure
 272          * atomicity of consecutive regmap operations.
 273          */
 274         struct mutex                    lock;
 275         struct completion               completion;
 276
 277         struct iio_chan_spec            chans[AD4130_MAX_CHANNELS];
 278         struct ad4130_chan_info         chans_info[AD4130_MAX_CHANNELS];
 279         struct ad4130_slot_info         slots_info[AD4130_MAX_SETUPS];
 280         enum ad4130_pin_function        pins_fn[AD4130_MAX_ANALOG_PINS];
 281         u32                             vbias_pins[AD4130_MAX_ANALOG_PINS];
 282         u32                             num_vbias_pins;
 283         int                             scale_tbls[AD4130_REF_SEL_MAX][AD4130_MAX_PGA][2];
 284         struct gpio_chip                gc;
 285         struct clk_hw                   int_clk_hw;
 286
 287         u32                     int_pin_sel;
 288         u32                     int_ref_uv;
 289         u32                     mclk_sel;
 290         bool                    int_ref_en;
 291         bool                    bipolar;
 292
 293         unsigned int            num_enabled_channels;
 294         unsigned int            effective_watermark;
 295         unsigned int            watermark;
 296
 297         struct spi_message      fifo_msg;
 298         struct spi_transfer     fifo_xfer[2];
 299
 300         /*
 301          * DMA (thus cache coherency maintenance) requires any transfer
 302          * buffers to live in their own cache lines. As the use of these
 303          * buffers is synchronous, all of the buffers used for DMA in this
 304          * driver may share a cache line.
 305          */
 306         u8                      reset_buf[AD4130_RESET_BUF_SIZE] __aligned(IIO_DMA_MINALIGN);
 307         u8                      reg_write_tx_buf[4];
 308         u8                      reg_read_tx_buf[1];
 309         u8                      reg_read_rx_buf[3];
 310         u8                      fifo_tx_buf[2];
 311         u8                      fifo_rx_buf[AD4130_FIFO_SIZE *
 312                                             AD4130_FIFO_MAX_SAMPLE_SIZE];
 313 };
 314
 315 static const char * const ad4130_int_pin_names[] = {
 316         [AD4130_INT_PIN_INT] = "int",
 317         [AD4130_INT_PIN_CLK] = "clk",
 318         [AD4130_INT_PIN_P2] = "p2",
 319         [AD4130_INT_PIN_DOUT] = "dout",
 320 };
 321
 322 static const unsigned int ad4130_iout_current_na_tbl[AD4130_IOUT_MAX] = {
 323         [AD4130_IOUT_OFF] = 0,
 324         [AD4130_IOUT_100NA] = 100,
 325         [AD4130_IOUT_10000NA] = 10000,
 326         [AD4130_IOUT_20000NA] = 20000,
 327         [AD4130_IOUT_50000NA] = 50000,
 328         [AD4130_IOUT_100000NA] = 100000,
 329         [AD4130_IOUT_150000NA] = 150000,
 330         [AD4130_IOUT_200000NA] = 200000,
 331 };
 332
 333 static const unsigned int ad4130_burnout_current_na_tbl[AD4130_BURNOUT_MAX] = {
 334         [AD4130_BURNOUT_OFF] = 0,
 335         [AD4130_BURNOUT_500NA] = 500,
 336         [AD4130_BURNOUT_2000NA] = 2000,
 337         [AD4130_BURNOUT_4000NA] = 4000,
 338 };
 339
 340 #define AD4130_VARIABLE_ODR_CONFIG(_filter_mode, _odr_div, _fs_max)     \
 341 {                                                                       \
 342                 .filter_mode = (_filter_mode),                          \
 343                 .odr_div = (_odr_div),                                  \
 344                 .fs_max = (_fs_max),                                    \
 345                 .samp_freq_avail_type = IIO_AVAIL_RANGE,                \
 346                 .samp_freq_avail = {                                    \
 347                         { AD4130_MAX_ODR, (_odr_div) * (_fs_max) },     \
 348                         { AD4130_MAX_ODR, (_odr_div) * (_fs_max) },     \
 349                         { AD4130_MAX_ODR, (_odr_div) },                 \
 350                 },                                                      \
 351 }
 352
 353 #define AD4130_FIXED_ODR_CONFIG(_filter_mode, _odr_div)                 \
 354 {                                                                       \
 355                 .filter_mode = (_filter_mode),                          \
 356                 .odr_div = (_odr_div),                                  \
 357                 .fs_max = AD4130_FILTER_SELECT_MIN,                     \
 358                 .samp_freq_avail_type = IIO_AVAIL_LIST,                 \
 359                 .samp_freq_avail_len = 1,                               \
 360                 .samp_freq_avail = {                                    \
 361                         { AD4130_MAX_ODR, (_odr_div) },                 \
 362                 },                                                      \
 363 }
 364
 365 static const struct ad4130_filter_config ad4130_filter_configs[] = {
 366         AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4,       1,  10),
 367         AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4_SINC1, 11, 10),
 368         AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3,       1,  2047),
 369         AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_REJ60, 1,  2047),
 370         AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_SINC1, 10, 2047),
 371         AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF1,      92),
 372         AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF2,      100),
 373         AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF3,      124),
 374         AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF4,      148),
 375 };
 376
 377 static const char * const ad4130_filter_modes_str[] = {
 378         [AD4130_FILTER_SINC4] = "sinc4",
 379         [AD4130_FILTER_SINC4_SINC1] = "sinc4+sinc1",
 380         [AD4130_FILTER_SINC3] = "sinc3",
 381         [AD4130_FILTER_SINC3_REJ60] = "sinc3+rej60",
 382         [AD4130_FILTER_SINC3_SINC1] = "sinc3+sinc1",
 383         [AD4130_FILTER_SINC3_PF1] = "sinc3+pf1",
 384         [AD4130_FILTER_SINC3_PF2] = "sinc3+pf2",
 385         [AD4130_FILTER_SINC3_PF3] = "sinc3+pf3",
 386         [AD4130_FILTER_SINC3_PF4] = "sinc3+pf4",
 387 };
 388
 389 static int ad4130_get_reg_size(struct ad4130_state *st, unsigned int reg,
 390                                unsigned int *size)
 391 {
 392         if (reg >= ARRAY_SIZE(ad4130_reg_size))
 393                 return -EINVAL;
 394
 395         *size = ad4130_reg_size[reg];
 396
 397         return 0;
 398 }
 399
 400 static unsigned int ad4130_data_reg_size(struct ad4130_state *st)
 401 {
 402         unsigned int data_reg_size;
 403         int ret;
 404
 405         ret = ad4130_get_reg_size(st, AD4130_DATA_REG, &data_reg_size);
 406         if (ret)
 407                 return 0;
 408
 409         return data_reg_size;
 410 }
 411
 412 static unsigned int ad4130_resolution(struct ad4130_state *st)
 413 {
 414         return ad4130_data_reg_size(st) * BITS_PER_BYTE;
 415 }
 416
 417 static int ad4130_reg_write(void *context, unsigned int reg, unsigned int val)
 418 {
 419         struct ad4130_state *st = context;
 420         unsigned int size;
 421         int ret;
 422
 423         ret = ad4130_get_reg_size(st, reg, &size);
 424         if (ret)
 425                 return ret;
 426
 427         st->reg_write_tx_buf[0] = reg;
 428
 429         switch (size) {
 430         case 3:
 431                 put_unaligned_be24(val, &st->reg_write_tx_buf[1]);
 432                 break;
 433         case 2:
 434                 put_unaligned_be16(val, &st->reg_write_tx_buf[1]);
 435                 break;
 436         case 1:
 437                 st->reg_write_tx_buf[1] = val;
 438                 break;
 439         default:
 440                 return -EINVAL;
 441         }
 442
 443         return spi_write(st->spi, st->reg_write_tx_buf, size + 1);
 444 }
 445
 446 static int ad4130_reg_read(void *context, unsigned int reg, unsigned int *val)
 447 {
 448         struct ad4130_state *st = context;
 449         struct spi_transfer t[] = {
 450                 {
 451                         .tx_buf = st->reg_read_tx_buf,
 452                         .len = sizeof(st->reg_read_tx_buf),
 453                 },
 454                 {
 455                         .rx_buf = st->reg_read_rx_buf,
 456                 },
 457         };
 458         unsigned int size;
 459         int ret;
 460
 461         ret = ad4130_get_reg_size(st, reg, &size);
 462         if (ret)
 463                 return ret;
 464
 465         st->reg_read_tx_buf[0] = AD4130_COMMS_READ_MASK | reg;
 466         t[1].len = size;
 467
 468         ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
 469         if (ret)
 470                 return ret;
 471
 472         switch (size) {
 473         case 3:
 474                 *val = get_unaligned_be24(st->reg_read_rx_buf);
 475                 break;
 476         case 2:
 477                 *val = get_unaligned_be16(st->reg_read_rx_buf);
 478                 break;
 479         case 1:
 480                 *val = st->reg_read_rx_buf[0];
 481                 break;
 482         default:
 483                 return -EINVAL;
 484         }
 485
 486         return 0;
 487 }
 488
 489 static const struct regmap_config ad4130_regmap_config = {
 490         .reg_read = ad4130_reg_read,
 491         .reg_write = ad4130_reg_write,
 492 };
 493
 494 static int ad4130_gpio_init_valid_mask(struct gpio_chip *gc,
 495                                        unsigned long *valid_mask,
 496                                        unsigned int ngpios)
 497 {
 498         struct ad4130_state *st = gpiochip_get_data(gc);
 499         unsigned int i;
 500
 501         /*
 502          * Output-only GPIO functionality is available on pins AIN2 through
 503          * AIN5. If these pins are used for anything else, do not expose them.
 504          */
 505         for (i = 0; i < ngpios; i++) {
 506                 unsigned int pin = i + AD4130_AIN2_P1;
 507                 bool valid = st->pins_fn[pin] == AD4130_PIN_FN_NONE;
 508
 509                 __assign_bit(i, valid_mask, valid);
 510         }
 511
 512         return 0;
 513 }
 514
 515 static int ad4130_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
 516 {
 517         return GPIO_LINE_DIRECTION_OUT;
 518 }
 519
 520 static void ad4130_gpio_set(struct gpio_chip *gc, unsigned int offset,
 521                             int value)
 522 {
 523         struct ad4130_state *st = gpiochip_get_data(gc);
 524         unsigned int mask = FIELD_PREP(AD4130_IO_CONTROL_GPIO_DATA_MASK,
 525                                        BIT(offset));
 526
 527         regmap_update_bits(st->regmap, AD4130_IO_CONTROL_REG, mask,
 528                            value ? mask : 0);
 529 }
 530
 531 static int ad4130_set_mode(struct ad4130_state *st, enum ad4130_mode mode)
 532 {
 533         return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG,
 534                                   AD4130_ADC_CONTROL_MODE_MASK,
 535                                   FIELD_PREP(AD4130_ADC_CONTROL_MODE_MASK, mode));
 536 }
 537
 538 static int ad4130_set_watermark_interrupt_en(struct ad4130_state *st, bool en)
 539 {
 540         return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
 541                                   AD4130_FIFO_CONTROL_WM_INT_EN_MASK,
 542                                   FIELD_PREP(AD4130_FIFO_CONTROL_WM_INT_EN_MASK, en));
 543 }
 544
 545 static unsigned int ad4130_watermark_reg_val(unsigned int val)
 546 {
 547         if (val == AD4130_FIFO_SIZE)
 548                 val = AD4130_WATERMARK_256;
 549
 550         return val;
 551 }
 552
 553 static int ad4130_set_fifo_mode(struct ad4130_state *st,
 554                                 enum ad4130_fifo_mode mode)
 555 {
 556         return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
 557                                   AD4130_FIFO_CONTROL_MODE_MASK,
 558                                   FIELD_PREP(AD4130_FIFO_CONTROL_MODE_MASK, mode));
 559 }
 560
 561 static void ad4130_push_fifo_data(struct iio_dev *indio_dev)
 562 {
 563         struct ad4130_state *st = iio_priv(indio_dev);
 564         unsigned int data_reg_size = ad4130_data_reg_size(st);
 565         unsigned int transfer_len = st->effective_watermark * data_reg_size;
 566         unsigned int set_size = st->num_enabled_channels * data_reg_size;
 567         unsigned int i;
 568         int ret;
 569
 570         st->fifo_tx_buf[1] = ad4130_watermark_reg_val(st->effective_watermark);
 571         st->fifo_xfer[1].len = transfer_len;
 572
 573         ret = spi_sync(st->spi, &st->fifo_msg);
 574         if (ret)
 575                 return;
 576
 577         for (i = 0; i < transfer_len; i += set_size)
 578                 iio_push_to_buffers(indio_dev, &st->fifo_rx_buf[i]);
 579 }
 580
 581 static irqreturn_t ad4130_irq_handler(int irq, void *private)
 582 {
 583         struct iio_dev *indio_dev = private;
 584         struct ad4130_state *st = iio_priv(indio_dev);
 585
 586         if (iio_buffer_enabled(indio_dev))
 587                 ad4130_push_fifo_data(indio_dev);
 588         else
 589                 complete(&st->completion);
 590
 591         return IRQ_HANDLED;
 592 }
 593
 594 static int ad4130_find_slot(struct ad4130_state *st,
 595                             struct ad4130_setup_info *target_setup_info,
 596                             unsigned int *slot, bool *overwrite)
 597 {
 598         unsigned int i;
 599
 600         *slot = AD4130_INVALID_SLOT;
 601         *overwrite = false;
 602
 603         for (i = 0; i < AD4130_MAX_SETUPS; i++) {
 604                 struct ad4130_slot_info *slot_info = &st->slots_info[i];
 605
 606                 /* Immediately accept a matching setup info. */
 607                 if (!memcmp(target_setup_info, &slot_info->setup,
 608                             sizeof(*target_setup_info))) {
 609                         *slot = i;
 610                         return 0;
 611                 }
 612
 613                 /* Ignore all setups which are used by enabled channels. */
 614                 if (slot_info->enabled_channels)
 615                         continue;
 616
 617                 /* Find the least used slot. */
 618                 if (*slot == AD4130_INVALID_SLOT ||
 619                     slot_info->channels < st->slots_info[*slot].channels)
 620                         *slot = i;
 621         }
 622
 623         if (*slot == AD4130_INVALID_SLOT)
 624                 return -EINVAL;
 625
 626         *overwrite = true;
 627
 628         return 0;
 629 }
 630
 631 static void ad4130_unlink_channel(struct ad4130_state *st, unsigned int channel)
 632 {
 633         struct ad4130_chan_info *chan_info = &st->chans_info[channel];
 634         struct ad4130_slot_info *slot_info = &st->slots_info[chan_info->slot];
 635
 636         chan_info->slot = AD4130_INVALID_SLOT;
 637         slot_info->channels--;
 638 }
 639
 640 static int ad4130_unlink_slot(struct ad4130_state *st, unsigned int slot)
 641 {
 642         unsigned int i;
 643
 644         for (i = 0; i < AD4130_MAX_CHANNELS; i++) {
 645                 struct ad4130_chan_info *chan_info = &st->chans_info[i];
 646
 647                 if (!chan_info->initialized || chan_info->slot != slot)
 648                         continue;
 649
 650                 ad4130_unlink_channel(st, i);
 651         }
 652
 653         return 0;
 654 }
 655
 656 static int ad4130_link_channel_slot(struct ad4130_state *st,
 657                                     unsigned int channel, unsigned int slot)
 658 {
 659         struct ad4130_slot_info *slot_info = &st->slots_info[slot];
 660         struct ad4130_chan_info *chan_info = &st->chans_info[channel];
 661         int ret;
 662
 663         ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel),
 664                                  AD4130_CHANNEL_SETUP_MASK,
 665                                  FIELD_PREP(AD4130_CHANNEL_SETUP_MASK, slot));
 666         if (ret)
 667                 return ret;
 668
 669         chan_info->slot = slot;
 670         slot_info->channels++;
 671
 672         return 0;
 673 }
 674
 675 static int ad4130_write_slot_setup(struct ad4130_state *st,
 676                                    unsigned int slot,
 677                                    struct ad4130_setup_info *setup_info)
 678 {
 679         unsigned int val;
 680         int ret;
 681
 682         val = FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout0_val) |
 683               FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout1_val) |
 684               FIELD_PREP(AD4130_CONFIG_BURNOUT_MASK, setup_info->burnout) |
 685               FIELD_PREP(AD4130_CONFIG_REF_BUFP_MASK, setup_info->ref_bufp) |
 686               FIELD_PREP(AD4130_CONFIG_REF_BUFM_MASK, setup_info->ref_bufm) |
 687               FIELD_PREP(AD4130_CONFIG_REF_SEL_MASK, setup_info->ref_sel) |
 688               FIELD_PREP(AD4130_CONFIG_PGA_MASK, setup_info->pga);
 689
 690         ret = regmap_write(st->regmap, AD4130_CONFIG_X_REG(slot), val);
 691         if (ret)
 692                 return ret;
 693
 694         val = FIELD_PREP(AD4130_FILTER_MODE_MASK, setup_info->filter_mode) |
 695               FIELD_PREP(AD4130_FILTER_SELECT_MASK, setup_info->fs);
 696
 697         ret = regmap_write(st->regmap, AD4130_FILTER_X_REG(slot), val);
 698         if (ret)
 699                 return ret;
 700
 701         memcpy(&st->slots_info[slot].setup, setup_info, sizeof(*setup_info));
 702
 703         return 0;
 704 }
 705
 706 static int ad4130_write_channel_setup(struct ad4130_state *st,
 707                                       unsigned int channel, bool on_enable)
 708 {
 709         struct ad4130_chan_info *chan_info = &st->chans_info[channel];
 710         struct ad4130_setup_info *setup_info = &chan_info->setup;
 711         bool overwrite;
 712         int slot;
 713         int ret;
 714
 715         /*
 716          * The following cases need to be handled.
 717          *
 718          * 1. Enabled and linked channel with setup changes:
 719          *    - Find a slot. If not possible, return error.
 720          *    - Unlink channel from current slot.
 721          *    - If the slot has channels linked to it, unlink all channels, and
 722          *      write the new setup to it.
 723          *    - Link channel to new slot.
 724          *
 725          * 2. Soon to be enabled and unlinked channel:
 726          *    - Find a slot. If not possible, return error.
 727          *    - If the slot has channels linked to it, unlink all channels, and
 728          *      write the new setup to it.
 729          *    - Link channel to the slot.
 730          *
 731          * 3. Disabled and linked channel with setup changes:
 732          *    - Unlink channel from current slot.
 733          *
 734          * 4. Soon to be enabled and linked channel:
 735          * 5. Disabled and unlinked channel with setup changes:
 736          *    - Do nothing.
 737          */
 738
 739         /* Case 4 */
 740         if (on_enable && chan_info->slot != AD4130_INVALID_SLOT)
 741                 return 0;
 742
 743         if (!on_enable && !chan_info->enabled) {
 744                 if (chan_info->slot != AD4130_INVALID_SLOT)
 745                         /* Case 3 */
 746                         ad4130_unlink_channel(st, channel);
 747
 748                 /* Cases 3 & 5 */
 749                 return 0;
 750         }
 751
 752         /* Cases 1 & 2 */
 753         ret = ad4130_find_slot(st, setup_info, &slot, &overwrite);
 754         if (ret)
 755                 return ret;
 756
 757         if (chan_info->slot != AD4130_INVALID_SLOT)
 758                 /* Case 1 */
 759                 ad4130_unlink_channel(st, channel);
 760
 761         if (overwrite) {
 762                 ret = ad4130_unlink_slot(st, slot);
 763                 if (ret)
 764                         return ret;
 765
 766                 ret = ad4130_write_slot_setup(st, slot, setup_info);
 767                 if (ret)
 768                         return ret;
 769         }
 770
 771         return ad4130_link_channel_slot(st, channel, slot);
 772 }
 773
 774 static int ad4130_set_channel_enable(struct ad4130_state *st,
 775                                      unsigned int channel, bool status)
 776 {
 777         struct ad4130_chan_info *chan_info = &st->chans_info[channel];
 778         struct ad4130_slot_info *slot_info;
 779         int ret;
 780
 781         if (chan_info->enabled == status)
 782                 return 0;
 783
 784         if (status) {
 785                 ret = ad4130_write_channel_setup(st, channel, true);
 786                 if (ret)
 787                         return ret;
 788         }
 789
 790         slot_info = &st->slots_info[chan_info->slot];
 791
 792         ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel),
 793                                  AD4130_CHANNEL_EN_MASK,
 794                                  FIELD_PREP(AD4130_CHANNEL_EN_MASK, status));
 795         if (ret)
 796                 return ret;
 797
 798         slot_info->enabled_channels += status ? 1 : -1;
 799         chan_info->enabled = status;
 800
 801         return 0;
 802 }
 803
 804 /*
 805  * Table 58. FILTER_MODE_n bits and Filter Types of the datasheet describes
 806  * the relation between filter mode, ODR and FS.
 807  *
 808  * Notice that the max ODR of each filter mode is not necessarily the
 809  * absolute max ODR supported by the chip.
 810  *
 811  * The ODR divider is not explicitly specified, but it can be deduced based
 812  * on the ODR range of each filter mode.
 813  *
 814  * For example, for Sinc4+Sinc1, max ODR is 218.18. That means that the
 815  * absolute max ODR is divided by 11 to achieve the max ODR of this filter
 816  * mode.
 817  *
 818  * The formulas for converting between ODR and FS for a specific filter
 819  * mode can be deduced from the same table.
 820  *
 821  * Notice that FS = 1 actually means max ODR, and that ODR decreases by
 822  * (maximum ODR / maximum FS) for each increment of FS.
 823  *
 824  * odr = MAX_ODR / odr_div * (1 - (fs - 1) / fs_max) <=>
 825  * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
 826  * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=>
 827  * odr = MAX_ODR * (fs_max - fs + 1) / (fs_max * odr_div)
 828  * (used in ad4130_fs_to_freq)
 829  *
 830  * For the opposite formula, FS can be extracted from the last one.
 831  *
 832  * MAX_ODR * (fs_max - fs + 1) = fs_max * odr_div * odr <=>
 833  * fs_max - fs + 1 = fs_max * odr_div * odr / MAX_ODR <=>
 834  * fs = 1 + fs_max - fs_max * odr_div * odr / MAX_ODR
 835  * (used in ad4130_fs_to_freq)
 836  */
 837
 838 static void ad4130_freq_to_fs(enum ad4130_filter_mode filter_mode,
 839                               int val, int val2, unsigned int *fs)
 840 {
 841         const struct ad4130_filter_config *filter_config =
 842                 &ad4130_filter_configs[filter_mode];
 843         u64 dividend, divisor;
 844         int temp;
 845
 846         dividend = filter_config->fs_max * filter_config->odr_div *
 847                    ((u64)val * NANO + val2);
 848         divisor = (u64)AD4130_MAX_ODR * NANO;
 849
 850         temp = AD4130_FILTER_SELECT_MIN + filter_config->fs_max -
 851                DIV64_U64_ROUND_CLOSEST(dividend, divisor);
 852
 853         if (temp < AD4130_FILTER_SELECT_MIN)
 854                 temp = AD4130_FILTER_SELECT_MIN;
 855         else if (temp > filter_config->fs_max)
 856                 temp = filter_config->fs_max;
 857
 858         *fs = temp;
 859 }
 860
 861 static void ad4130_fs_to_freq(enum ad4130_filter_mode filter_mode,
 862                               unsigned int fs, int *val, int *val2)
 863 {
 864         const struct ad4130_filter_config *filter_config =
 865                 &ad4130_filter_configs[filter_mode];
 866         unsigned int dividend, divisor;
 867         u64 temp;
 868
 869         dividend = (filter_config->fs_max - fs + AD4130_FILTER_SELECT_MIN) *
 870                    AD4130_MAX_ODR;
 871         divisor = filter_config->fs_max * filter_config->odr_div;
 872
 873         temp = div_u64((u64)dividend * NANO, divisor);
 874         *val = div_u64_rem(temp, NANO, val2);
 875 }
 876
 877 static int ad4130_set_filter_mode(struct iio_dev *indio_dev,
 878                                   const struct iio_chan_spec *chan,
 879                                   unsigned int val)
 880 {
 881         struct ad4130_state *st = iio_priv(indio_dev);
 882         unsigned int channel = chan->scan_index;
 883         struct ad4130_chan_info *chan_info = &st->chans_info[channel];
 884         struct ad4130_setup_info *setup_info = &chan_info->setup;
 885         enum ad4130_filter_mode old_filter_mode;
 886         int freq_val, freq_val2;
 887         unsigned int old_fs;
 888         int ret = 0;
 889
 890         guard(mutex)(&st->lock);
 891         if (setup_info->filter_mode == val)
 892                 return 0;
 893
 894         old_fs = setup_info->fs;
 895         old_filter_mode = setup_info->filter_mode;
 896
 897         /*
 898          * When switching between filter modes, try to match the ODR as
 899          * close as possible. To do this, convert the current FS into ODR
 900          * using the old filter mode, then convert it back into FS using
 901          * the new filter mode.
 902          */
 903         ad4130_fs_to_freq(setup_info->filter_mode, setup_info->fs,
 904                           &freq_val, &freq_val2);
 905
 906         ad4130_freq_to_fs(val, freq_val, freq_val2, &setup_info->fs);
 907
 908         setup_info->filter_mode = val;
 909
 910         ret = ad4130_write_channel_setup(st, channel, false);
 911         if (ret) {
 912                 setup_info->fs = old_fs;
 913                 setup_info->filter_mode = old_filter_mode;
 914                 return ret;
 915         }
 916
 917         return 0;
 918 }
 919
 920 static int ad4130_get_filter_mode(struct iio_dev *indio_dev,
 921                                   const struct iio_chan_spec *chan)
 922 {
 923         struct ad4130_state *st = iio_priv(indio_dev);
 924         unsigned int channel = chan->scan_index;
 925         struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;
 926         enum ad4130_filter_mode filter_mode;
 927
 928         guard(mutex)(&st->lock);
 929         filter_mode = setup_info->filter_mode;
 930
 931         return filter_mode;
 932 }
 933
 934 static const struct iio_enum ad4130_filter_mode_enum = {
 935         .items = ad4130_filter_modes_str,
 936         .num_items = ARRAY_SIZE(ad4130_filter_modes_str),
 937         .set = ad4130_set_filter_mode,
 938         .get = ad4130_get_filter_mode,
 939 };
 940
 941 static const struct iio_chan_spec_ext_info ad4130_filter_mode_ext_info[] = {
 942         IIO_ENUM("filter_mode", IIO_SEPARATE, &ad4130_filter_mode_enum),
 943         IIO_ENUM_AVAILABLE("filter_mode", IIO_SHARED_BY_TYPE,
 944                            &ad4130_filter_mode_enum),
 945         { }
 946 };
 947
 948 static const struct iio_chan_spec ad4130_channel_template = {
 949         .type = IIO_VOLTAGE,
 950         .indexed = 1,
 951         .differential = 1,
 952         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 953                               BIT(IIO_CHAN_INFO_SCALE) |
 954                               BIT(IIO_CHAN_INFO_OFFSET) |
 955                               BIT(IIO_CHAN_INFO_SAMP_FREQ),
 956         .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE) |
 957                                         BIT(IIO_CHAN_INFO_SAMP_FREQ),
 958         .ext_info = ad4130_filter_mode_ext_info,
 959         .scan_type = {
 960                 .sign = 'u',
 961                 .endianness = IIO_BE,
 962         },
 963 };
 964
 965 static int ad4130_set_channel_pga(struct ad4130_state *st, unsigned int channel,
 966                                   int val, int val2)
 967 {
 968         struct ad4130_chan_info *chan_info = &st->chans_info[channel];
 969         struct ad4130_setup_info *setup_info = &chan_info->setup;
 970         unsigned int pga, old_pga;
 971         int ret;
 972
 973         for (pga = 0; pga < AD4130_MAX_PGA; pga++)
 974                 if (val == st->scale_tbls[setup_info->ref_sel][pga][0] &&
 975                     val2 == st->scale_tbls[setup_info->ref_sel][pga][1])
 976                         break;
 977
 978         if (pga == AD4130_MAX_PGA)
 979                 return -EINVAL;
 980
 981         guard(mutex)(&st->lock);
 982         if (pga == setup_info->pga)
 983                 return 0;
 984
 985         old_pga = setup_info->pga;
 986         setup_info->pga = pga;
 987
 988         ret = ad4130_write_channel_setup(st, channel, false);
 989         if (ret) {
 990                 setup_info->pga = old_pga;
 991                 return ret;
 992         }
 993
 994         return 0;
 995 }
 996
 997 static int ad4130_set_channel_freq(struct ad4130_state *st,
 998                                    unsigned int channel, int val, int val2)
 999 {
1000         struct ad4130_chan_info *chan_info = &st->chans_info[channel];
1001         struct ad4130_setup_info *setup_info = &chan_info->setup;
1002         unsigned int fs, old_fs;
1003         int ret;
1004
1005         guard(mutex)(&st->lock);
1006         old_fs = setup_info->fs;
1007
1008         ad4130_freq_to_fs(setup_info->filter_mode, val, val2, &fs);
1009
1010         if (fs == setup_info->fs)
1011                 return 0;
1012
1013         setup_info->fs = fs;
1014
1015         ret = ad4130_write_channel_setup(st, channel, false);
1016         if (ret) {
1017                 setup_info->fs = old_fs;
1018                 return ret;
1019         }
1020
1021         return 0;
1022 }
1023
1024 static int _ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel,
1025                                int *val)
1026 {
1027         struct ad4130_state *st = iio_priv(indio_dev);
1028         int ret;
1029
1030         ret = ad4130_set_channel_enable(st, channel, true);
1031         if (ret)
1032                 return ret;
1033
1034         reinit_completion(&st->completion);
1035
1036         ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS);
1037         if (ret)
1038                 return ret;
1039
1040         ret = wait_for_completion_timeout(&st->completion,
1041                                           msecs_to_jiffies(1000));
1042         if (!ret)
1043                 return -ETIMEDOUT;
1044
1045         ret = ad4130_set_mode(st, AD4130_MODE_IDLE);
1046         if (ret)
1047                 return ret;
1048
1049         ret = regmap_read(st->regmap, AD4130_DATA_REG, val);
1050         if (ret)
1051                 return ret;
1052
1053         ret = ad4130_set_channel_enable(st, channel, false);
1054         if (ret)
1055                 return ret;
1056
1057         return IIO_VAL_INT;
1058 }
1059
1060 static int ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel,
1061                               int *val)
1062 {
1063         iio_device_claim_direct_scoped(return -EBUSY, indio_dev) {
1064                 struct ad4130_state *st = iio_priv(indio_dev);
1065
1066                 guard(mutex)(&st->lock);
1067                 return _ad4130_read_sample(indio_dev, channel, val);
1068         }
1069         unreachable();
1070 }
1071
1072 static int ad4130_read_raw(struct iio_dev *indio_dev,
1073                            struct iio_chan_spec const *chan,
1074                            int *val, int *val2, long info)
1075 {
1076         struct ad4130_state *st = iio_priv(indio_dev);
1077         unsigned int channel = chan->scan_index;
1078         struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;
1079
1080         switch (info) {
1081         case IIO_CHAN_INFO_RAW:
1082                 return ad4130_read_sample(indio_dev, channel, val);
1083         case IIO_CHAN_INFO_SCALE: {
1084                 guard(mutex)(&st->lock);
1085                 *val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0];
1086                 *val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1];
1087
1088                 return IIO_VAL_INT_PLUS_NANO;
1089         }
1090         case IIO_CHAN_INFO_OFFSET:
1091                 *val = st->bipolar ? -BIT(chan->scan_type.realbits - 1) : 0;
1092
1093                 return IIO_VAL_INT;
1094         case IIO_CHAN_INFO_SAMP_FREQ: {
1095                 guard(mutex)(&st->lock);
1096                 ad4130_fs_to_freq(setup_info->filter_mode, setup_info->fs,
1097                                   val, val2);
1098
1099                 return IIO_VAL_INT_PLUS_NANO;
1100         }
1101         default:
1102                 return -EINVAL;
1103         }
1104 }
1105
1106 static int ad4130_read_avail(struct iio_dev *indio_dev,
1107                              struct iio_chan_spec const *chan,
1108                              const int **vals, int *type, int *length,
1109                              long info)
1110 {
1111         struct ad4130_state *st = iio_priv(indio_dev);
1112         unsigned int channel = chan->scan_index;
1113         struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup;
1114         const struct ad4130_filter_config *filter_config;
1115
1116         switch (info) {
1117         case IIO_CHAN_INFO_SCALE:
1118                 *vals = (int *)st->scale_tbls[setup_info->ref_sel];
1119                 *length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2;
1120
1121                 *type = IIO_VAL_INT_PLUS_NANO;
1122
1123                 return IIO_AVAIL_LIST;
1124         case IIO_CHAN_INFO_SAMP_FREQ:
1125                 scoped_guard(mutex, &st->lock) {
1126                         filter_config = &ad4130_filter_configs[setup_info->filter_mode];
1127                 }
1128
1129                 *vals = (int *)filter_config->samp_freq_avail;
1130                 *length = filter_config->samp_freq_avail_len * 2;
1131                 *type = IIO_VAL_FRACTIONAL;
1132
1133                 return filter_config->samp_freq_avail_type;
1134         default:
1135                 return -EINVAL;
1136         }
1137 }
1138
1139 static int ad4130_write_raw_get_fmt(struct iio_dev *indio_dev,
1140                                     struct iio_chan_spec const *chan,
1141                                     long info)
1142 {
1143         switch (info) {
1144         case IIO_CHAN_INFO_SCALE:
1145         case IIO_CHAN_INFO_SAMP_FREQ:
1146                 return IIO_VAL_INT_PLUS_NANO;
1147         default:
1148                 return -EINVAL;
1149         }
1150 }
1151
1152 static int ad4130_write_raw(struct iio_dev *indio_dev,
1153                             struct iio_chan_spec const *chan,
1154                             int val, int val2, long info)
1155 {
1156         struct ad4130_state *st = iio_priv(indio_dev);
1157         unsigned int channel = chan->scan_index;
1158
1159         switch (info) {
1160         case IIO_CHAN_INFO_SCALE:
1161                 return ad4130_set_channel_pga(st, channel, val, val2);
1162         case IIO_CHAN_INFO_SAMP_FREQ:
1163                 return ad4130_set_channel_freq(st, channel, val, val2);
1164         default:
1165                 return -EINVAL;
1166         }
1167 }
1168
1169 static int ad4130_reg_access(struct iio_dev *indio_dev, unsigned int reg,
1170                              unsigned int writeval, unsigned int *readval)
1171 {
1172         struct ad4130_state *st = iio_priv(indio_dev);
1173
1174         if (readval)
1175                 return regmap_read(st->regmap, reg, readval);
1176
1177         return regmap_write(st->regmap, reg, writeval);
1178 }
1179
1180 static int ad4130_update_scan_mode(struct iio_dev *indio_dev,
1181                                    const unsigned long *scan_mask)
1182 {
1183         struct ad4130_state *st = iio_priv(indio_dev);
1184         unsigned int channel;
1185         unsigned int val = 0;
1186         int ret;
1187
1188         guard(mutex)(&st->lock);
1189
1190         for_each_set_bit(channel, scan_mask, indio_dev->num_channels) {
1191                 ret = ad4130_set_channel_enable(st, channel, true);
1192                 if (ret)
1193                         return ret;
1194
1195                 val++;
1196         }
1197
1198         st->num_enabled_channels = val;
1199
1200         return 0;
1201 }
1202
1203 static int ad4130_set_fifo_watermark(struct iio_dev *indio_dev, unsigned int val)
1204 {
1205         struct ad4130_state *st = iio_priv(indio_dev);
1206         unsigned int eff;
1207         int ret;
1208
1209         if (val > AD4130_FIFO_SIZE)
1210                 return -EINVAL;
1211
1212         eff = val * st->num_enabled_channels;
1213         if (eff > AD4130_FIFO_SIZE)
1214                 /*
1215                  * Always set watermark to a multiple of the number of
1216                  * enabled channels to avoid making the FIFO unaligned.
1217                  */
1218                 eff = rounddown(AD4130_FIFO_SIZE, st->num_enabled_channels);
1219
1220         guard(mutex)(&st->lock);
1221
1222         ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
1223                                  AD4130_FIFO_CONTROL_WM_MASK,
1224                                  FIELD_PREP(AD4130_FIFO_CONTROL_WM_MASK,
1225                                             ad4130_watermark_reg_val(eff)));
1226         if (ret)
1227                 return ret;
1228
1229         st->effective_watermark = eff;
1230         st->watermark = val;
1231
1232         return 0;
1233 }
1234
1235 static const struct iio_info ad4130_info = {
1236         .read_raw = ad4130_read_raw,
1237         .read_avail = ad4130_read_avail,
1238         .write_raw_get_fmt = ad4130_write_raw_get_fmt,
1239         .write_raw = ad4130_write_raw,
1240         .update_scan_mode = ad4130_update_scan_mode,
1241         .hwfifo_set_watermark = ad4130_set_fifo_watermark,
1242         .debugfs_reg_access = ad4130_reg_access,
1243 };
1244
1245 static int ad4130_buffer_postenable(struct iio_dev *indio_dev)
1246 {
1247         struct ad4130_state *st = iio_priv(indio_dev);
1248         int ret;
1249
1250         guard(mutex)(&st->lock);
1251
1252         ret = ad4130_set_watermark_interrupt_en(st, true);
1253         if (ret)
1254                 return ret;
1255
1256         ret = irq_set_irq_type(st->spi->irq, st->inv_irq_trigger);
1257         if (ret)
1258                 return ret;
1259
1260         ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_WM);
1261         if (ret)
1262                 return ret;
1263
1264         return ad4130_set_mode(st, AD4130_MODE_CONTINUOUS);
1265 }
1266
1267 static int ad4130_buffer_predisable(struct iio_dev *indio_dev)
1268 {
1269         struct ad4130_state *st = iio_priv(indio_dev);
1270         unsigned int i;
1271         int ret;
1272
1273         guard(mutex)(&st->lock);
1274
1275         ret = ad4130_set_mode(st, AD4130_MODE_IDLE);
1276         if (ret)
1277                 return ret;
1278
1279         ret = irq_set_irq_type(st->spi->irq, st->irq_trigger);
1280         if (ret)
1281                 return ret;
1282
1283         ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_DISABLED);
1284         if (ret)
1285                 return ret;
1286
1287         ret = ad4130_set_watermark_interrupt_en(st, false);
1288         if (ret)
1289                 return ret;
1290
1291         /*
1292          * update_scan_mode() is not called in the disable path, disable all
1293          * channels here.
1294          */
1295         for (i = 0; i < indio_dev->num_channels; i++) {
1296                 ret = ad4130_set_channel_enable(st, i, false);
1297                 if (ret)
1298                         return ret;
1299         }
1300
1301         return 0;
1302 }
1303
1304 static const struct iio_buffer_setup_ops ad4130_buffer_ops = {
1305         .postenable = ad4130_buffer_postenable,
1306         .predisable = ad4130_buffer_predisable,
1307 };
1308
1309 static ssize_t hwfifo_watermark_show(struct device *dev,
1310                                      struct device_attribute *attr, char *buf)
1311 {
1312         struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev));
1313         unsigned int val;
1314
1315         guard(mutex)(&st->lock);
1316         val = st->watermark;
1317
1318         return sysfs_emit(buf, "%d\n", val);
1319 }
1320
1321 static ssize_t hwfifo_enabled_show(struct device *dev,
1322                                    struct device_attribute *attr, char *buf)
1323 {
1324         struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev));
1325         unsigned int val;
1326         int ret;
1327
1328         ret = regmap_read(st->regmap, AD4130_FIFO_CONTROL_REG, &val);
1329         if (ret)
1330                 return ret;
1331
1332         val = FIELD_GET(AD4130_FIFO_CONTROL_MODE_MASK, val);
1333
1334         return sysfs_emit(buf, "%d\n", val != AD4130_FIFO_MODE_DISABLED);
1335 }
1336
1337 static ssize_t hwfifo_watermark_min_show(struct device *dev,
1338                                          struct device_attribute *attr,
1339                                          char *buf)
1340 {
1341         return sysfs_emit(buf, "%s\n", "1");
1342 }
1343
1344 static ssize_t hwfifo_watermark_max_show(struct device *dev,
1345                                          struct device_attribute *attr,
1346                                          char *buf)
1347 {
1348         return sysfs_emit(buf, "%s\n", __stringify(AD4130_FIFO_SIZE));
1349 }
1350
1351 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0);
1352 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0);
1353 static IIO_DEVICE_ATTR_RO(hwfifo_watermark, 0);
1354 static IIO_DEVICE_ATTR_RO(hwfifo_enabled, 0);
1355
1356 static const struct iio_dev_attr *ad4130_fifo_attributes[] = {
1357         &iio_dev_attr_hwfifo_watermark_min,
1358         &iio_dev_attr_hwfifo_watermark_max,
1359         &iio_dev_attr_hwfifo_watermark,
1360         &iio_dev_attr_hwfifo_enabled,
1361         NULL
1362 };
1363
1364 static int _ad4130_find_table_index(const unsigned int *tbl, size_t len,
1365                                     unsigned int val)
1366 {
1367         unsigned int i;
1368
1369         for (i = 0; i < len; i++)
1370                 if (tbl[i] == val)
1371                         return i;
1372
1373         return -EINVAL;
1374 }
1375
1376 #define ad4130_find_table_index(table, val) \
1377         _ad4130_find_table_index(table, ARRAY_SIZE(table), val)
1378
1379 static int ad4130_get_ref_voltage(struct ad4130_state *st,
1380                                   enum ad4130_ref_sel ref_sel)
1381 {
1382         switch (ref_sel) {
1383         case AD4130_REF_REFIN1:
1384                 return regulator_get_voltage(st->regulators[2].consumer);
1385         case AD4130_REF_REFIN2:
1386                 return regulator_get_voltage(st->regulators[3].consumer);
1387         case AD4130_REF_AVDD_AVSS:
1388                 return regulator_get_voltage(st->regulators[0].consumer);
1389         case AD4130_REF_REFOUT_AVSS:
1390                 return st->int_ref_uv;
1391         default:
1392                 return -EINVAL;
1393         }
1394 }
1395
1396 static int ad4130_parse_fw_setup(struct ad4130_state *st,
1397                                  struct fwnode_handle *child,
1398                                  struct ad4130_setup_info *setup_info)
1399 {
1400         struct device *dev = &st->spi->dev;
1401         u32 tmp;
1402         int ret;
1403
1404         tmp = 0;
1405         fwnode_property_read_u32(child, "adi,excitation-current-0-nanoamp", &tmp);
1406         ret = ad4130_find_table_index(ad4130_iout_current_na_tbl, tmp);
1407         if (ret < 0)
1408                 return dev_err_probe(dev, ret,
1409                                      "Invalid excitation current %unA\n", tmp);
1410         setup_info->iout0_val = ret;
1411
1412         tmp = 0;
1413         fwnode_property_read_u32(child, "adi,excitation-current-1-nanoamp", &tmp);
1414         ret = ad4130_find_table_index(ad4130_iout_current_na_tbl, tmp);
1415         if (ret < 0)
1416                 return dev_err_probe(dev, ret,
1417                                      "Invalid excitation current %unA\n", tmp);
1418         setup_info->iout1_val = ret;
1419
1420         tmp = 0;
1421         fwnode_property_read_u32(child, "adi,burnout-current-nanoamp", &tmp);
1422         ret = ad4130_find_table_index(ad4130_burnout_current_na_tbl, tmp);
1423         if (ret < 0)
1424                 return dev_err_probe(dev, ret,
1425                                      "Invalid burnout current %unA\n", tmp);
1426         setup_info->burnout = ret;
1427
1428         setup_info->ref_bufp = fwnode_property_read_bool(child, "adi,buffered-positive");
1429         setup_info->ref_bufm = fwnode_property_read_bool(child, "adi,buffered-negative");
1430
1431         setup_info->ref_sel = AD4130_REF_REFIN1;
1432         fwnode_property_read_u32(child, "adi,reference-select",
1433                                  &setup_info->ref_sel);
1434         if (setup_info->ref_sel >= AD4130_REF_SEL_MAX)
1435                 return dev_err_probe(dev, -EINVAL,
1436                                      "Invalid reference selected %u\n",
1437                                      setup_info->ref_sel);
1438
1439         if (setup_info->ref_sel == AD4130_REF_REFOUT_AVSS)
1440                 st->int_ref_en = true;
1441
1442         ret = ad4130_get_ref_voltage(st, setup_info->ref_sel);
1443         if (ret < 0)
1444                 return dev_err_probe(dev, ret, "Cannot use reference %u\n",
1445                                      setup_info->ref_sel);
1446
1447         return 0;
1448 }
1449
1450 static int ad4130_validate_diff_channel(struct ad4130_state *st, u32 pin)
1451 {
1452         struct device *dev = &st->spi->dev;
1453
1454         if (pin >= AD4130_MAX_DIFF_INPUTS)
1455                 return dev_err_probe(dev, -EINVAL,
1456                                      "Invalid differential channel %u\n", pin);
1457
1458         if (pin >= AD4130_MAX_ANALOG_PINS)
1459                 return 0;
1460
1461         if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)
1462                 return dev_err_probe(dev, -EINVAL,
1463                                      "Pin %u already used with fn %u\n", pin,
1464                                      st->pins_fn[pin]);
1465
1466         st->pins_fn[pin] |= AD4130_PIN_FN_DIFF;
1467
1468         return 0;
1469 }
1470
1471 static int ad4130_validate_diff_channels(struct ad4130_state *st,
1472                                          u32 *pins, unsigned int len)
1473 {
1474         unsigned int i;
1475         int ret;
1476
1477         for (i = 0; i < len; i++) {
1478                 ret = ad4130_validate_diff_channel(st, pins[i]);
1479                 if (ret)
1480                         return ret;
1481         }
1482
1483         return 0;
1484 }
1485
1486 static int ad4130_validate_excitation_pin(struct ad4130_state *st, u32 pin)
1487 {
1488         struct device *dev = &st->spi->dev;
1489
1490         if (pin >= AD4130_MAX_ANALOG_PINS)
1491                 return dev_err_probe(dev, -EINVAL,
1492                                      "Invalid excitation pin %u\n", pin);
1493
1494         if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)
1495                 return dev_err_probe(dev, -EINVAL,
1496                                      "Pin %u already used with fn %u\n", pin,
1497                                      st->pins_fn[pin]);
1498
1499         st->pins_fn[pin] |= AD4130_PIN_FN_EXCITATION;
1500
1501         return 0;
1502 }
1503
1504 static int ad4130_validate_vbias_pin(struct ad4130_state *st, u32 pin)
1505 {
1506         struct device *dev = &st->spi->dev;
1507
1508         if (pin >= AD4130_MAX_ANALOG_PINS)
1509                 return dev_err_probe(dev, -EINVAL, "Invalid vbias pin %u\n",
1510                                      pin);
1511
1512         if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL)
1513                 return dev_err_probe(dev, -EINVAL,
1514                                      "Pin %u already used with fn %u\n", pin,
1515                                      st->pins_fn[pin]);
1516
1517         st->pins_fn[pin] |= AD4130_PIN_FN_VBIAS;
1518
1519         return 0;
1520 }
1521
1522 static int ad4130_validate_vbias_pins(struct ad4130_state *st,
1523                                       u32 *pins, unsigned int len)
1524 {
1525         unsigned int i;
1526         int ret;
1527
1528         for (i = 0; i < st->num_vbias_pins; i++) {
1529                 ret = ad4130_validate_vbias_pin(st, pins[i]);
1530                 if (ret)
1531                         return ret;
1532         }
1533
1534         return 0;
1535 }
1536
1537 static int ad4130_parse_fw_channel(struct iio_dev *indio_dev,
1538                                    struct fwnode_handle *child)
1539 {
1540         struct ad4130_state *st = iio_priv(indio_dev);
1541         unsigned int resolution = ad4130_resolution(st);
1542         unsigned int index = indio_dev->num_channels++;
1543         struct device *dev = &st->spi->dev;
1544         struct ad4130_chan_info *chan_info;
1545         struct iio_chan_spec *chan;
1546         u32 pins[2];
1547         int ret;
1548
1549         if (index >= AD4130_MAX_CHANNELS)
1550                 return dev_err_probe(dev, -EINVAL, "Too many channels\n");
1551
1552         chan = &st->chans[index];
1553         chan_info = &st->chans_info[index];
1554
1555         *chan = ad4130_channel_template;
1556         chan->scan_type.realbits = resolution;
1557         chan->scan_type.storagebits = resolution;
1558         chan->scan_index = index;
1559
1560         chan_info->slot = AD4130_INVALID_SLOT;
1561         chan_info->setup.fs = AD4130_FILTER_SELECT_MIN;
1562         chan_info->initialized = true;
1563
1564         ret = fwnode_property_read_u32_array(child, "diff-channels", pins,
1565                                              ARRAY_SIZE(pins));
1566         if (ret)
1567                 return ret;
1568
1569         ret = ad4130_validate_diff_channels(st, pins, ARRAY_SIZE(pins));
1570         if (ret)
1571                 return ret;
1572
1573         chan->channel = pins[0];
1574         chan->channel2 = pins[1];
1575
1576         ret = ad4130_parse_fw_setup(st, child, &chan_info->setup);
1577         if (ret)
1578                 return ret;
1579
1580         fwnode_property_read_u32(child, "adi,excitation-pin-0",
1581                                  &chan_info->iout0);
1582         if (chan_info->setup.iout0_val != AD4130_IOUT_OFF) {
1583                 ret = ad4130_validate_excitation_pin(st, chan_info->iout0);
1584                 if (ret)
1585                         return ret;
1586         }
1587
1588         fwnode_property_read_u32(child, "adi,excitation-pin-1",
1589                                  &chan_info->iout1);
1590         if (chan_info->setup.iout1_val != AD4130_IOUT_OFF) {
1591                 ret = ad4130_validate_excitation_pin(st, chan_info->iout1);
1592                 if (ret)
1593                         return ret;
1594         }
1595
1596         return 0;
1597 }
1598
1599 static int ad4130_parse_fw_children(struct iio_dev *indio_dev)
1600 {
1601         struct ad4130_state *st = iio_priv(indio_dev);
1602         struct device *dev = &st->spi->dev;
1603         struct fwnode_handle *child;
1604         int ret;
1605
1606         indio_dev->channels = st->chans;
1607
1608         device_for_each_child_node(dev, child) {
1609                 ret = ad4130_parse_fw_channel(indio_dev, child);
1610                 if (ret) {
1611                         fwnode_handle_put(child);
1612                         return ret;
1613                 }
1614         }
1615
1616         return 0;
1617 }
1618
1619 static int ad4310_parse_fw(struct iio_dev *indio_dev)
1620 {
1621         struct ad4130_state *st = iio_priv(indio_dev);
1622         struct device *dev = &st->spi->dev;
1623         u32 ext_clk_freq = AD4130_MCLK_FREQ_76_8KHZ;
1624         unsigned int i;
1625         int avdd_uv;
1626         int irq;
1627         int ret;
1628
1629         st->mclk = devm_clk_get_optional(dev, "mclk");
1630         if (IS_ERR(st->mclk))
1631                 return dev_err_probe(dev, PTR_ERR(st->mclk),
1632                                      "Failed to get mclk\n");
1633
1634         st->int_pin_sel = AD4130_INT_PIN_INT;
1635
1636         for (i = 0; i < ARRAY_SIZE(ad4130_int_pin_names); i++) {
1637                 irq = fwnode_irq_get_byname(dev_fwnode(dev),
1638                                             ad4130_int_pin_names[i]);
1639                 if (irq > 0) {
1640                         st->int_pin_sel = i;
1641                         break;
1642                 }
1643         }
1644
1645         if (st->int_pin_sel == AD4130_INT_PIN_DOUT)
1646                 return dev_err_probe(dev, -EINVAL,
1647                                      "Cannot use DOUT as interrupt pin\n");
1648
1649         if (st->int_pin_sel == AD4130_INT_PIN_P2)
1650                 st->pins_fn[AD4130_AIN3_P2] = AD4130_PIN_FN_SPECIAL;
1651
1652         device_property_read_u32(dev, "adi,ext-clk-freq-hz", &ext_clk_freq);
1653         if (ext_clk_freq != AD4130_MCLK_FREQ_153_6KHZ &&
1654             ext_clk_freq != AD4130_MCLK_FREQ_76_8KHZ)
1655                 return dev_err_probe(dev, -EINVAL,
1656                                      "Invalid external clock frequency %u\n",
1657                                      ext_clk_freq);
1658
1659         if (st->mclk && ext_clk_freq == AD4130_MCLK_FREQ_153_6KHZ)
1660                 st->mclk_sel = AD4130_MCLK_153_6KHZ_EXT;
1661         else if (st->mclk)
1662                 st->mclk_sel = AD4130_MCLK_76_8KHZ_EXT;
1663         else
1664                 st->mclk_sel = AD4130_MCLK_76_8KHZ;
1665
1666         if (st->int_pin_sel == AD4130_INT_PIN_CLK &&
1667             st->mclk_sel != AD4130_MCLK_76_8KHZ)
1668                 return dev_err_probe(dev, -EINVAL,
1669                                      "Invalid clock %u for interrupt pin %u\n",
1670                                      st->mclk_sel, st->int_pin_sel);
1671
1672         st->int_ref_uv = AD4130_INT_REF_2_5V;
1673
1674         /*
1675          * When the AVDD supply is set to below 2.5V the internal reference of
1676          * 1.25V should be selected.
1677          * See datasheet page 37, section ADC REFERENCE.
1678          */
1679         avdd_uv = regulator_get_voltage(st->regulators[0].consumer);
1680         if (avdd_uv > 0 && avdd_uv < AD4130_INT_REF_2_5V)
1681                 st->int_ref_uv = AD4130_INT_REF_1_25V;
1682
1683         st->bipolar = device_property_read_bool(dev, "adi,bipolar");
1684
1685         ret = device_property_count_u32(dev, "adi,vbias-pins");
1686         if (ret > 0) {
1687                 if (ret > AD4130_MAX_ANALOG_PINS)
1688                         return dev_err_probe(dev, -EINVAL,
1689                                              "Too many vbias pins %u\n", ret);
1690
1691                 st->num_vbias_pins = ret;
1692
1693                 ret = device_property_read_u32_array(dev, "adi,vbias-pins",
1694                                                      st->vbias_pins,
1695                                                      st->num_vbias_pins);
1696                 if (ret)
1697                         return dev_err_probe(dev, ret,
1698                                              "Failed to read vbias pins\n");
1699
1700                 ret = ad4130_validate_vbias_pins(st, st->vbias_pins,
1701                                                  st->num_vbias_pins);
1702                 if (ret)
1703                         return ret;
1704         }
1705
1706         ret = ad4130_parse_fw_children(indio_dev);
1707         if (ret)
1708                 return ret;
1709
1710         return 0;
1711 }
1712
1713 static void ad4130_fill_scale_tbls(struct ad4130_state *st)
1714 {
1715         unsigned int pow = ad4130_resolution(st) - st->bipolar;
1716         unsigned int i, j;
1717
1718         for (i = 0; i < AD4130_REF_SEL_MAX; i++) {
1719                 int ret;
1720                 u64 nv;
1721
1722                 ret = ad4130_get_ref_voltage(st, i);
1723                 if (ret < 0)
1724                         continue;
1725
1726                 nv = (u64)ret * NANO;
1727
1728                 for (j = 0; j < AD4130_MAX_PGA; j++)
1729                         st->scale_tbls[i][j][1] = div_u64(nv >> (pow + j), MILLI);
1730         }
1731 }
1732
1733 static void ad4130_clk_disable_unprepare(void *clk)
1734 {
1735         clk_disable_unprepare(clk);
1736 }
1737
1738 static int ad4130_set_mclk_sel(struct ad4130_state *st,
1739                                enum ad4130_mclk_sel mclk_sel)
1740 {
1741         return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG,
1742                                  AD4130_ADC_CONTROL_MCLK_SEL_MASK,
1743                                  FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK,
1744                                             mclk_sel));
1745 }
1746
1747 static unsigned long ad4130_int_clk_recalc_rate(struct clk_hw *hw,
1748                                                 unsigned long parent_rate)
1749 {
1750         return AD4130_MCLK_FREQ_76_8KHZ;
1751 }
1752
1753 static int ad4130_int_clk_is_enabled(struct clk_hw *hw)
1754 {
1755         struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);
1756
1757         return st->mclk_sel == AD4130_MCLK_76_8KHZ_OUT;
1758 }
1759
1760 static int ad4130_int_clk_prepare(struct clk_hw *hw)
1761 {
1762         struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);
1763         int ret;
1764
1765         ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ_OUT);
1766         if (ret)
1767                 return ret;
1768
1769         st->mclk_sel = AD4130_MCLK_76_8KHZ_OUT;
1770
1771         return 0;
1772 }
1773
1774 static void ad4130_int_clk_unprepare(struct clk_hw *hw)
1775 {
1776         struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw);
1777         int ret;
1778
1779         ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ);
1780         if (ret)
1781                 return;
1782
1783         st->mclk_sel = AD4130_MCLK_76_8KHZ;
1784 }
1785
1786 static const struct clk_ops ad4130_int_clk_ops = {
1787         .recalc_rate = ad4130_int_clk_recalc_rate,
1788         .is_enabled = ad4130_int_clk_is_enabled,
1789         .prepare = ad4130_int_clk_prepare,
1790         .unprepare = ad4130_int_clk_unprepare,
1791 };
1792
1793 static int ad4130_setup_int_clk(struct ad4130_state *st)
1794 {
1795         struct device *dev = &st->spi->dev;
1796         struct device_node *of_node = dev_of_node(dev);
1797         struct clk_init_data init = {};
1798         const char *clk_name;
1799         int ret;
1800
1801         if (st->int_pin_sel == AD4130_INT_PIN_CLK ||
1802             st->mclk_sel != AD4130_MCLK_76_8KHZ)
1803                 return 0;
1804
1805         if (!of_node)
1806                 return 0;
1807
1808         clk_name = of_node->name;
1809         of_property_read_string(of_node, "clock-output-names", &clk_name);
1810
1811         init.name = clk_name;
1812         init.ops = &ad4130_int_clk_ops;
1813
1814         st->int_clk_hw.init = &init;
1815         ret = devm_clk_hw_register(dev, &st->int_clk_hw);
1816         if (ret)
1817                 return ret;
1818
1819         return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
1820                                            &st->int_clk_hw);
1821 }
1822
1823 static int ad4130_setup(struct iio_dev *indio_dev)
1824 {
1825         struct ad4130_state *st = iio_priv(indio_dev);
1826         struct device *dev = &st->spi->dev;
1827         unsigned int int_ref_val;
1828         unsigned long rate = AD4130_MCLK_FREQ_76_8KHZ;
1829         unsigned int val;
1830         unsigned int i;
1831         int ret;
1832
1833         if (st->mclk_sel == AD4130_MCLK_153_6KHZ_EXT)
1834                 rate = AD4130_MCLK_FREQ_153_6KHZ;
1835
1836         ret = clk_set_rate(st->mclk, rate);
1837         if (ret)
1838                 return ret;
1839
1840         ret = clk_prepare_enable(st->mclk);
1841         if (ret)
1842                 return ret;
1843
1844         ret = devm_add_action_or_reset(dev, ad4130_clk_disable_unprepare,
1845                                        st->mclk);
1846         if (ret)
1847                 return ret;
1848
1849         if (st->int_ref_uv == AD4130_INT_REF_2_5V)
1850                 int_ref_val = AD4130_INT_REF_VAL_2_5V;
1851         else
1852                 int_ref_val = AD4130_INT_REF_VAL_1_25V;
1853
1854         /* Switch to SPI 4-wire mode. */
1855         val =  FIELD_PREP(AD4130_ADC_CONTROL_CSB_EN_MASK, 1);
1856         val |= FIELD_PREP(AD4130_ADC_CONTROL_BIPOLAR_MASK, st->bipolar);
1857         val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_EN_MASK, st->int_ref_en);
1858         val |= FIELD_PREP(AD4130_ADC_CONTROL_MODE_MASK, AD4130_MODE_IDLE);
1859         val |= FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, st->mclk_sel);
1860         val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_VAL_MASK, int_ref_val);
1861
1862         ret = regmap_write(st->regmap, AD4130_ADC_CONTROL_REG, val);
1863         if (ret)
1864                 return ret;
1865
1866         /*
1867          * Configure unused GPIOs for output. If configured, the interrupt
1868          * function of P2 takes priority over the GPIO out function.
1869          */
1870         val = 0;
1871         for (i = 0; i < AD4130_MAX_GPIOS; i++)
1872                 if (st->pins_fn[i + AD4130_AIN2_P1] == AD4130_PIN_FN_NONE)
1873                         val |= FIELD_PREP(AD4130_IO_CONTROL_GPIO_CTRL_MASK, BIT(i));
1874
1875         val |= FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st->int_pin_sel);
1876
1877         ret = regmap_write(st->regmap, AD4130_IO_CONTROL_REG, val);
1878         if (ret)
1879                 return ret;
1880
1881         val = 0;
1882         for (i = 0; i < st->num_vbias_pins; i++)
1883                 val |= BIT(st->vbias_pins[i]);
1884
1885         ret = regmap_write(st->regmap, AD4130_VBIAS_REG, val);
1886         if (ret)
1887                 return ret;
1888
1889         ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG,
1890                                  AD4130_FIFO_CONTROL_HEADER_MASK, 0);
1891         if (ret)
1892                 return ret;
1893
1894         /* FIFO watermark interrupt starts out as enabled, disable it. */
1895         ret = ad4130_set_watermark_interrupt_en(st, false);
1896         if (ret)
1897                 return ret;
1898
1899         /* Setup channels. */
1900         for (i = 0; i < indio_dev->num_channels; i++) {
1901                 struct ad4130_chan_info *chan_info = &st->chans_info[i];
1902                 struct iio_chan_spec *chan = &st->chans[i];
1903                 unsigned int val;
1904
1905                 val = FIELD_PREP(AD4130_CHANNEL_AINP_MASK, chan->channel) |
1906                       FIELD_PREP(AD4130_CHANNEL_AINM_MASK, chan->channel2) |
1907                       FIELD_PREP(AD4130_CHANNEL_IOUT1_MASK, chan_info->iout0) |
1908                       FIELD_PREP(AD4130_CHANNEL_IOUT2_MASK, chan_info->iout1);
1909
1910                 ret = regmap_write(st->regmap, AD4130_CHANNEL_X_REG(i), val);
1911                 if (ret)
1912                         return ret;
1913         }
1914
1915         return 0;
1916 }
1917
1918 static int ad4130_soft_reset(struct ad4130_state *st)
1919 {
1920         int ret;
1921
1922         ret = spi_write(st->spi, st->reset_buf, sizeof(st->reset_buf));
1923         if (ret)
1924                 return ret;
1925
1926         fsleep(AD4130_RESET_SLEEP_US);
1927
1928         return 0;
1929 }
1930
1931 static void ad4130_disable_regulators(void *data)
1932 {
1933         struct ad4130_state *st = data;
1934
1935         regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);
1936 }
1937
1938 static int ad4130_probe(struct spi_device *spi)
1939 {
1940         struct device *dev = &spi->dev;
1941         struct iio_dev *indio_dev;
1942         struct ad4130_state *st;
1943         int ret;
1944
1945         indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1946         if (!indio_dev)
1947                 return -ENOMEM;
1948
1949         st = iio_priv(indio_dev);
1950
1951         memset(st->reset_buf, 0xff, sizeof(st->reset_buf));
1952         init_completion(&st->completion);
1953         mutex_init(&st->lock);
1954         st->spi = spi;
1955
1956         /*
1957          * Xfer:   [ XFR1 ] [         XFR2         ]
1958          * Master:  0x7D N   ......................
1959          * Slave:   ......   DATA1 DATA2 ... DATAN
1960          */
1961         st->fifo_tx_buf[0] = AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG;
1962         st->fifo_xfer[0].tx_buf = st->fifo_tx_buf;
1963         st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf);
1964         st->fifo_xfer[1].rx_buf = st->fifo_rx_buf;
1965         spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer,
1966                                         ARRAY_SIZE(st->fifo_xfer));
1967
1968         indio_dev->name = AD4130_NAME;
1969         indio_dev->modes = INDIO_DIRECT_MODE;
1970         indio_dev->info = &ad4130_info;
1971
1972         st->regmap = devm_regmap_init(dev, NULL, st, &ad4130_regmap_config);
1973         if (IS_ERR(st->regmap))
1974                 return PTR_ERR(st->regmap);
1975
1976         st->regulators[0].supply = "avdd";
1977         st->regulators[1].supply = "iovdd";
1978         st->regulators[2].supply = "refin1";
1979         st->regulators[3].supply = "refin2";
1980
1981         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators),
1982                                       st->regulators);
1983         if (ret)
1984                 return dev_err_probe(dev, ret, "Failed to get regulators\n");
1985
1986         ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);
1987         if (ret)
1988                 return dev_err_probe(dev, ret, "Failed to enable regulators\n");
1989
1990         ret = devm_add_action_or_reset(dev, ad4130_disable_regulators, st);
1991         if (ret)
1992                 return dev_err_probe(dev, ret,
1993                                      "Failed to add regulators disable action\n");
1994
1995         ret = ad4130_soft_reset(st);
1996         if (ret)
1997                 return ret;
1998
1999         ret = ad4310_parse_fw(indio_dev);
2000         if (ret)
2001                 return ret;
2002
2003         ret = ad4130_setup(indio_dev);
2004         if (ret)
2005                 return ret;
2006
2007         ret = ad4130_setup_int_clk(st);
2008         if (ret)
2009                 return ret;
2010
2011         ad4130_fill_scale_tbls(st);
2012
2013         st->gc.owner = THIS_MODULE;
2014         st->gc.label = AD4130_NAME;
2015         st->gc.base = -1;
2016         st->gc.ngpio = AD4130_MAX_GPIOS;
2017         st->gc.parent = dev;
2018         st->gc.can_sleep = true;
2019         st->gc.init_valid_mask = ad4130_gpio_init_valid_mask;
2020         st->gc.get_direction = ad4130_gpio_get_direction;
2021         st->gc.set = ad4130_gpio_set;
2022
2023         ret = devm_gpiochip_add_data(dev, &st->gc, st);
2024         if (ret)
2025                 return ret;
2026
2027         ret = devm_iio_kfifo_buffer_setup_ext(dev, indio_dev,
2028                                               &ad4130_buffer_ops,
2029                                               ad4130_fifo_attributes);
2030         if (ret)
2031                 return ret;
2032
2033         ret = devm_request_threaded_irq(dev, spi->irq, NULL,
2034                                         ad4130_irq_handler, IRQF_ONESHOT,
2035                                         indio_dev->name, indio_dev);
2036         if (ret)
2037                 return dev_err_probe(dev, ret, "Failed to request irq\n");
2038
2039         /*
2040          * When the chip enters FIFO mode, IRQ polarity is inverted.
2041          * When the chip exits FIFO mode, IRQ polarity returns to normal.
2042          * See datasheet pages: 65, FIFO Watermark Interrupt section,
2043          * and 71, Bit Descriptions for STATUS Register, RDYB.
2044          * Cache the normal and inverted IRQ triggers to set them when
2045          * entering and exiting FIFO mode.
2046          */
2047         st->irq_trigger = irq_get_trigger_type(spi->irq);
2048         if (st->irq_trigger & IRQF_TRIGGER_RISING)
2049                 st->inv_irq_trigger = IRQF_TRIGGER_FALLING;
2050         else if (st->irq_trigger & IRQF_TRIGGER_FALLING)
2051                 st->inv_irq_trigger = IRQF_TRIGGER_RISING;
2052         else
2053                 return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n",
2054                                      st->irq_trigger);
2055
2056         return devm_iio_device_register(dev, indio_dev);
2057 }
2058
2059 static const struct of_device_id ad4130_of_match[] = {
2060         {
2061                 .compatible = "adi,ad4130",
2062         },
2063         { }
2064 };
2065 MODULE_DEVICE_TABLE(of, ad4130_of_match);
2066
2067 static struct spi_driver ad4130_driver = {
2068         .driver = {
2069                 .name = AD4130_NAME,
2070                 .of_match_table = ad4130_of_match,
2071         },
2072         .probe = ad4130_probe,
2073 };
2074 module_spi_driver(ad4130_driver);
2075
2076 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
2077 MODULE_DESCRIPTION("Analog Devices AD4130 SPI driver");
2078 MODULE_LICENSE("GPL");