1 // SPDX-License-Identifier: GPL-2.0
3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
5 * device name digital output 7-bit I2C slave address (pin selectable)
6 * ---------------------------------------------------------------------
7 * MMA8451Q 14 bit 0x1c / 0x1d
8 * MMA8452Q 12 bit 0x1c / 0x1d
9 * MMA8453Q 10 bit 0x1c / 0x1d
10 * MMA8652FC 12 bit 0x1d
11 * MMA8653FC 10 bit 0x1d
12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f
14 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
18 * TODO: orientation events
21 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/iio/events.h>
30 #include <linux/delay.h>
31 #include <linux/of_device.h>
32 #include <linux/of_irq.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/regulator/consumer.h>
36 #define MMA8452_STATUS 0x00
37 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
38 #define MMA8452_OUT_X 0x01 /* MSB first */
39 #define MMA8452_OUT_Y 0x03
40 #define MMA8452_OUT_Z 0x05
41 #define MMA8452_INT_SRC 0x0c
42 #define MMA8452_WHO_AM_I 0x0d
43 #define MMA8452_DATA_CFG 0x0e
44 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
45 #define MMA8452_DATA_CFG_FS_2G 0
46 #define MMA8452_DATA_CFG_FS_4G 1
47 #define MMA8452_DATA_CFG_FS_8G 2
48 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
49 #define MMA8452_HP_FILTER_CUTOFF 0x0f
50 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
51 #define MMA8452_FF_MT_CFG 0x15
52 #define MMA8452_FF_MT_CFG_OAE BIT(6)
53 #define MMA8452_FF_MT_CFG_ELE BIT(7)
54 #define MMA8452_FF_MT_SRC 0x16
55 #define MMA8452_FF_MT_SRC_XHE BIT(1)
56 #define MMA8452_FF_MT_SRC_YHE BIT(3)
57 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
58 #define MMA8452_FF_MT_THS 0x17
59 #define MMA8452_FF_MT_THS_MASK 0x7f
60 #define MMA8452_FF_MT_COUNT 0x18
61 #define MMA8452_FF_MT_CHAN_SHIFT 3
62 #define MMA8452_TRANSIENT_CFG 0x1d
63 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
64 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
65 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
66 #define MMA8452_TRANSIENT_SRC 0x1e
67 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
68 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
69 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
70 #define MMA8452_TRANSIENT_THS 0x1f
71 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
72 #define MMA8452_TRANSIENT_COUNT 0x20
73 #define MMA8452_TRANSIENT_CHAN_SHIFT 1
74 #define MMA8452_CTRL_REG1 0x2a
75 #define MMA8452_CTRL_ACTIVE BIT(0)
76 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
77 #define MMA8452_CTRL_DR_SHIFT 3
78 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
79 #define MMA8452_CTRL_REG2 0x2b
80 #define MMA8452_CTRL_REG2_RST BIT(6)
81 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
82 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
83 #define MMA8452_CTRL_REG4 0x2d
84 #define MMA8452_CTRL_REG5 0x2e
85 #define MMA8452_OFF_X 0x2f
86 #define MMA8452_OFF_Y 0x30
87 #define MMA8452_OFF_Z 0x31
89 #define MMA8452_MAX_REG 0x31
91 #define MMA8452_INT_DRDY BIT(0)
92 #define MMA8452_INT_FF_MT BIT(2)
93 #define MMA8452_INT_TRANS BIT(5)
95 #define MMA8451_DEVICE_ID 0x1a
96 #define MMA8452_DEVICE_ID 0x2a
97 #define MMA8453_DEVICE_ID 0x3a
98 #define MMA8652_DEVICE_ID 0x4a
99 #define MMA8653_DEVICE_ID 0x5a
100 #define FXLS8471_DEVICE_ID 0x6a
102 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
104 struct mma8452_data {
105 struct i2c_client *client;
107 struct iio_mount_matrix orientation;
110 const struct mma_chip_info *chip_info;
112 struct regulator *vdd_reg;
113 struct regulator *vddio_reg;
115 /* Ensure correct alignment of time stamp when present */
123 * struct mma8452_event_regs - chip specific data related to events
124 * @ev_cfg: event config register address
125 * @ev_cfg_ele: latch bit in event config register
126 * @ev_cfg_chan_shift: number of the bit to enable events in X
127 * direction; in event config register
128 * @ev_src: event source register address
129 * @ev_ths: event threshold register address
130 * @ev_ths_mask: mask for the threshold value
131 * @ev_count: event count (period) register address
133 * Since not all chips supported by the driver support comparing high pass
134 * filtered data for events (interrupts), different interrupt sources are
135 * used for different chips and the relevant registers are included here.
137 struct mma8452_event_regs {
140 u8 ev_cfg_chan_shift;
147 static const struct mma8452_event_regs ff_mt_ev_regs = {
148 .ev_cfg = MMA8452_FF_MT_CFG,
149 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
150 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
151 .ev_src = MMA8452_FF_MT_SRC,
152 .ev_ths = MMA8452_FF_MT_THS,
153 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
154 .ev_count = MMA8452_FF_MT_COUNT
157 static const struct mma8452_event_regs trans_ev_regs = {
158 .ev_cfg = MMA8452_TRANSIENT_CFG,
159 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
160 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
161 .ev_src = MMA8452_TRANSIENT_SRC,
162 .ev_ths = MMA8452_TRANSIENT_THS,
163 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
164 .ev_count = MMA8452_TRANSIENT_COUNT,
168 * struct mma_chip_info - chip specific data
169 * @chip_id: WHO_AM_I register's value
170 * @channels: struct iio_chan_spec matching the device's
172 * @num_channels: number of channels
173 * @mma_scales: scale factors for converting register values
174 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
175 * per mode: m/s^2 and micro m/s^2
176 * @all_events: all events supported by this chip
177 * @enabled_events: event flags enabled and handled by this driver
179 struct mma_chip_info {
182 const struct iio_chan_spec *channels;
184 const int mma_scales[3][2];
196 static int mma8452_drdy(struct mma8452_data *data)
200 while (tries-- > 0) {
201 int ret = i2c_smbus_read_byte_data(data->client,
205 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
208 if (data->sleep_val <= 20)
209 usleep_range(data->sleep_val * 250,
210 data->sleep_val * 500);
215 dev_err(&data->client->dev, "data not ready\n");
220 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
226 ret = pm_runtime_resume_and_get(&client->dev);
228 pm_runtime_mark_last_busy(&client->dev);
229 ret = pm_runtime_put_autosuspend(&client->dev);
233 dev_err(&client->dev,
234 "failed to change power state to %d\n", on);
243 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
245 int ret = mma8452_drdy(data);
250 ret = mma8452_set_runtime_pm_state(data->client, true);
254 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
255 3 * sizeof(__be16), (u8 *)buf);
257 ret = mma8452_set_runtime_pm_state(data->client, false);
262 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
268 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
269 vals[n][0], vals[n][1]);
271 /* replace trailing space by newline */
277 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
281 if (val == vals[n][0] && val2 == vals[n][1])
287 static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
289 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
290 MMA8452_CTRL_DR_SHIFT;
293 static const int mma8452_samp_freq[8][2] = {
294 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
295 {6, 250000}, {1, 560000}
298 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
299 static const unsigned int mma8452_time_step_us[4][8] = {
300 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
301 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
302 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
303 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
306 /* Datasheet table "High-Pass Filter Cutoff Options" */
307 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
309 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
310 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
311 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
312 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
313 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
314 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
315 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
316 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
318 { /* low noise low power */
319 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
320 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
321 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
322 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
323 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
324 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
325 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
326 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
328 { /* high resolution */
329 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
334 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
335 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
336 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
339 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
340 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
341 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
342 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
343 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
344 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
345 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
346 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
350 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
351 static const u16 mma8452_os_ratio[4][8] = {
352 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
353 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
354 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
355 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
356 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
359 static int mma8452_get_power_mode(struct mma8452_data *data)
363 reg = i2c_smbus_read_byte_data(data->client,
368 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
369 MMA8452_CTRL_REG2_MODS_SHIFT);
372 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
373 struct device_attribute *attr,
376 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
377 ARRAY_SIZE(mma8452_samp_freq));
380 static ssize_t mma8452_show_scale_avail(struct device *dev,
381 struct device_attribute *attr,
384 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
385 to_i2c_client(dev)));
387 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
388 ARRAY_SIZE(data->chip_info->mma_scales));
391 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
392 struct device_attribute *attr,
395 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
396 struct mma8452_data *data = iio_priv(indio_dev);
399 i = mma8452_get_odr_index(data);
400 j = mma8452_get_power_mode(data);
404 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
405 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
408 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
409 struct device_attribute *attr,
412 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
413 struct mma8452_data *data = iio_priv(indio_dev);
414 int i = mma8452_get_odr_index(data);
419 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
420 if (val == mma8452_os_ratio[j][i])
423 val = mma8452_os_ratio[j][i];
425 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
432 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
433 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
434 mma8452_show_scale_avail, NULL, 0);
435 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
436 0444, mma8452_show_hp_cutoff_avail, NULL, 0);
437 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444,
438 mma8452_show_os_ratio_avail, NULL, 0);
440 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
443 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
444 ARRAY_SIZE(mma8452_samp_freq),
448 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
450 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
451 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
454 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
459 i = mma8452_get_odr_index(data);
460 j = mma8452_get_power_mode(data);
464 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
465 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
468 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
472 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
476 i = mma8452_get_odr_index(data);
477 j = mma8452_get_power_mode(data);
481 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
482 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
483 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
488 static int mma8452_read_raw(struct iio_dev *indio_dev,
489 struct iio_chan_spec const *chan,
490 int *val, int *val2, long mask)
492 struct mma8452_data *data = iio_priv(indio_dev);
497 case IIO_CHAN_INFO_RAW:
498 ret = iio_device_claim_direct_mode(indio_dev);
502 mutex_lock(&data->lock);
503 ret = mma8452_read(data, buffer);
504 mutex_unlock(&data->lock);
505 iio_device_release_direct_mode(indio_dev);
509 *val = sign_extend32(be16_to_cpu(
510 buffer[chan->scan_index]) >> chan->scan_type.shift,
511 chan->scan_type.realbits - 1);
514 case IIO_CHAN_INFO_SCALE:
515 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
516 *val = data->chip_info->mma_scales[i][0];
517 *val2 = data->chip_info->mma_scales[i][1];
519 return IIO_VAL_INT_PLUS_MICRO;
520 case IIO_CHAN_INFO_SAMP_FREQ:
521 i = mma8452_get_odr_index(data);
522 *val = mma8452_samp_freq[i][0];
523 *val2 = mma8452_samp_freq[i][1];
525 return IIO_VAL_INT_PLUS_MICRO;
526 case IIO_CHAN_INFO_CALIBBIAS:
527 ret = i2c_smbus_read_byte_data(data->client,
533 *val = sign_extend32(ret, 7);
536 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
537 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
538 ret = mma8452_read_hp_filter(data, val, val2);
546 return IIO_VAL_INT_PLUS_MICRO;
547 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
548 ret = mma8452_get_power_mode(data);
552 i = mma8452_get_odr_index(data);
554 *val = mma8452_os_ratio[ret][i];
561 static int mma8452_calculate_sleep(struct mma8452_data *data)
563 int ret, i = mma8452_get_odr_index(data);
565 if (mma8452_samp_freq[i][0] > 0)
566 ret = 1000 / mma8452_samp_freq[i][0];
570 return ret == 0 ? 1 : ret;
573 static int mma8452_standby(struct mma8452_data *data)
575 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
576 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
579 static int mma8452_active(struct mma8452_data *data)
581 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
585 /* returns >0 if active, 0 if in standby and <0 on error */
586 static int mma8452_is_active(struct mma8452_data *data)
590 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
594 return reg & MMA8452_CTRL_ACTIVE;
597 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
602 mutex_lock(&data->lock);
604 is_active = mma8452_is_active(data);
610 /* config can only be changed when in standby */
612 ret = mma8452_standby(data);
617 ret = i2c_smbus_write_byte_data(data->client, reg, val);
622 ret = mma8452_active(data);
629 mutex_unlock(&data->lock);
634 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
638 reg = i2c_smbus_read_byte_data(data->client,
643 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
644 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
646 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
649 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
650 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
654 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
658 return !(val & MMA8452_FF_MT_CFG_OAE);
661 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
665 if ((state && mma8452_freefall_mode_enabled(data)) ||
666 (!state && !(mma8452_freefall_mode_enabled(data))))
669 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
674 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
675 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
676 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
677 val &= ~MMA8452_FF_MT_CFG_OAE;
679 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
680 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
681 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
682 val |= MMA8452_FF_MT_CFG_OAE;
685 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val);
688 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
693 i = mma8452_get_hp_filter_index(data, val, val2);
697 reg = i2c_smbus_read_byte_data(data->client,
698 MMA8452_HP_FILTER_CUTOFF);
702 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
705 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
708 static int mma8452_write_raw(struct iio_dev *indio_dev,
709 struct iio_chan_spec const *chan,
710 int val, int val2, long mask)
712 struct mma8452_data *data = iio_priv(indio_dev);
715 ret = iio_device_claim_direct_mode(indio_dev);
720 case IIO_CHAN_INFO_SAMP_FREQ:
721 i = mma8452_get_samp_freq_index(data, val, val2);
726 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
727 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
729 data->sleep_val = mma8452_calculate_sleep(data);
731 ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
734 case IIO_CHAN_INFO_SCALE:
735 i = mma8452_get_scale_index(data, val, val2);
741 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
744 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
747 case IIO_CHAN_INFO_CALIBBIAS:
748 if (val < -128 || val > 127) {
753 ret = mma8452_change_config(data,
754 MMA8452_OFF_X + chan->scan_index,
758 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
759 if (val == 0 && val2 == 0) {
760 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
762 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
763 ret = mma8452_set_hp_filter_frequency(data, val, val2);
768 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
772 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
773 ret = mma8452_get_odr_index(data);
775 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
776 if (mma8452_os_ratio[i][ret] == val) {
777 ret = mma8452_set_power_mode(data, i);
787 iio_device_release_direct_mode(indio_dev);
791 static int mma8452_get_event_regs(struct mma8452_data *data,
792 const struct iio_chan_spec *chan, enum iio_event_direction dir,
793 const struct mma8452_event_regs **ev_reg)
798 switch (chan->type) {
801 case IIO_EV_DIR_RISING:
802 if ((data->chip_info->all_events
803 & MMA8452_INT_TRANS) &&
804 (data->chip_info->enabled_events
805 & MMA8452_INT_TRANS))
806 *ev_reg = &trans_ev_regs;
808 *ev_reg = &ff_mt_ev_regs;
810 case IIO_EV_DIR_FALLING:
811 *ev_reg = &ff_mt_ev_regs;
821 static int mma8452_read_event_value(struct iio_dev *indio_dev,
822 const struct iio_chan_spec *chan,
823 enum iio_event_type type,
824 enum iio_event_direction dir,
825 enum iio_event_info info,
828 struct mma8452_data *data = iio_priv(indio_dev);
829 int ret, us, power_mode;
830 const struct mma8452_event_regs *ev_regs;
832 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
837 case IIO_EV_INFO_VALUE:
838 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths);
842 *val = ret & ev_regs->ev_ths_mask;
846 case IIO_EV_INFO_PERIOD:
847 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count);
851 power_mode = mma8452_get_power_mode(data);
855 us = ret * mma8452_time_step_us[power_mode][
856 mma8452_get_odr_index(data)];
857 *val = us / USEC_PER_SEC;
858 *val2 = us % USEC_PER_SEC;
860 return IIO_VAL_INT_PLUS_MICRO;
862 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
863 ret = i2c_smbus_read_byte_data(data->client,
864 MMA8452_TRANSIENT_CFG);
868 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
872 ret = mma8452_read_hp_filter(data, val, val2);
877 return IIO_VAL_INT_PLUS_MICRO;
884 static int mma8452_write_event_value(struct iio_dev *indio_dev,
885 const struct iio_chan_spec *chan,
886 enum iio_event_type type,
887 enum iio_event_direction dir,
888 enum iio_event_info info,
891 struct mma8452_data *data = iio_priv(indio_dev);
893 const struct mma8452_event_regs *ev_regs;
895 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
900 case IIO_EV_INFO_VALUE:
901 if (val < 0 || val > ev_regs->ev_ths_mask)
904 return mma8452_change_config(data, ev_regs->ev_ths, val);
906 case IIO_EV_INFO_PERIOD:
907 ret = mma8452_get_power_mode(data);
911 steps = (val * USEC_PER_SEC + val2) /
912 mma8452_time_step_us[ret][
913 mma8452_get_odr_index(data)];
915 if (steps < 0 || steps > 0xff)
918 return mma8452_change_config(data, ev_regs->ev_count, steps);
920 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
921 reg = i2c_smbus_read_byte_data(data->client,
922 MMA8452_TRANSIENT_CFG);
926 if (val == 0 && val2 == 0) {
927 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
929 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
930 ret = mma8452_set_hp_filter_frequency(data, val, val2);
935 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
942 static int mma8452_read_event_config(struct iio_dev *indio_dev,
943 const struct iio_chan_spec *chan,
944 enum iio_event_type type,
945 enum iio_event_direction dir)
947 struct mma8452_data *data = iio_priv(indio_dev);
949 const struct mma8452_event_regs *ev_regs;
951 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
956 case IIO_EV_DIR_FALLING:
957 return mma8452_freefall_mode_enabled(data);
958 case IIO_EV_DIR_RISING:
959 ret = i2c_smbus_read_byte_data(data->client,
964 return !!(ret & BIT(chan->scan_index +
965 ev_regs->ev_cfg_chan_shift));
971 static int mma8452_write_event_config(struct iio_dev *indio_dev,
972 const struct iio_chan_spec *chan,
973 enum iio_event_type type,
974 enum iio_event_direction dir,
977 struct mma8452_data *data = iio_priv(indio_dev);
979 const struct mma8452_event_regs *ev_regs;
981 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
985 ret = mma8452_set_runtime_pm_state(data->client, state);
990 case IIO_EV_DIR_FALLING:
991 return mma8452_set_freefall_mode(data, state);
992 case IIO_EV_DIR_RISING:
993 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg);
998 if (mma8452_freefall_mode_enabled(data)) {
999 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift);
1000 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift);
1001 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift);
1002 val |= MMA8452_FF_MT_CFG_OAE;
1004 val |= BIT(chan->scan_index +
1005 ev_regs->ev_cfg_chan_shift);
1007 if (mma8452_freefall_mode_enabled(data))
1010 val &= ~BIT(chan->scan_index +
1011 ev_regs->ev_cfg_chan_shift);
1014 val |= ev_regs->ev_cfg_ele;
1016 return mma8452_change_config(data, ev_regs->ev_cfg, val);
1022 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
1024 struct mma8452_data *data = iio_priv(indio_dev);
1025 s64 ts = iio_get_time_ns(indio_dev);
1028 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
1032 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
1033 iio_push_event(indio_dev,
1034 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1039 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
1040 iio_push_event(indio_dev,
1041 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
1046 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
1047 iio_push_event(indio_dev,
1048 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
1054 static irqreturn_t mma8452_interrupt(int irq, void *p)
1056 struct iio_dev *indio_dev = p;
1057 struct mma8452_data *data = iio_priv(indio_dev);
1058 irqreturn_t ret = IRQ_NONE;
1061 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
1065 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY)))
1068 if (src & MMA8452_INT_DRDY) {
1069 iio_trigger_poll_chained(indio_dev->trig);
1073 if (src & MMA8452_INT_FF_MT) {
1074 if (mma8452_freefall_mode_enabled(data)) {
1075 s64 ts = iio_get_time_ns(indio_dev);
1077 iio_push_event(indio_dev,
1078 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1079 IIO_MOD_X_AND_Y_AND_Z,
1081 IIO_EV_DIR_FALLING),
1087 if (src & MMA8452_INT_TRANS) {
1088 mma8452_transient_interrupt(indio_dev);
1095 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1097 struct iio_poll_func *pf = p;
1098 struct iio_dev *indio_dev = pf->indio_dev;
1099 struct mma8452_data *data = iio_priv(indio_dev);
1102 ret = mma8452_read(data, data->buffer.channels);
1106 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1107 iio_get_time_ns(indio_dev));
1110 iio_trigger_notify_done(indio_dev->trig);
1115 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1116 unsigned int reg, unsigned int writeval,
1117 unsigned int *readval)
1120 struct mma8452_data *data = iio_priv(indio_dev);
1122 if (reg > MMA8452_MAX_REG)
1126 return mma8452_change_config(data, reg, writeval);
1128 ret = i2c_smbus_read_byte_data(data->client, reg);
1137 static const struct iio_event_spec mma8452_freefall_event[] = {
1139 .type = IIO_EV_TYPE_MAG,
1140 .dir = IIO_EV_DIR_FALLING,
1141 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1142 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1143 BIT(IIO_EV_INFO_PERIOD) |
1144 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1148 static const struct iio_event_spec mma8652_freefall_event[] = {
1150 .type = IIO_EV_TYPE_MAG,
1151 .dir = IIO_EV_DIR_FALLING,
1152 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1153 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1154 BIT(IIO_EV_INFO_PERIOD)
1158 static const struct iio_event_spec mma8452_transient_event[] = {
1160 .type = IIO_EV_TYPE_MAG,
1161 .dir = IIO_EV_DIR_RISING,
1162 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1163 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1164 BIT(IIO_EV_INFO_PERIOD) |
1165 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1169 static const struct iio_event_spec mma8452_motion_event[] = {
1171 .type = IIO_EV_TYPE_MAG,
1172 .dir = IIO_EV_DIR_RISING,
1173 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1174 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1175 BIT(IIO_EV_INFO_PERIOD)
1180 * Threshold is configured in fixed 8G/127 steps regardless of
1181 * currently selected scale for measurement.
1183 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1185 static struct attribute *mma8452_event_attributes[] = {
1186 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1190 static const struct attribute_group mma8452_event_attribute_group = {
1191 .attrs = mma8452_event_attributes,
1194 static const struct iio_mount_matrix *
1195 mma8452_get_mount_matrix(const struct iio_dev *indio_dev,
1196 const struct iio_chan_spec *chan)
1198 struct mma8452_data *data = iio_priv(indio_dev);
1200 return &data->orientation;
1203 static const struct iio_chan_spec_ext_info mma8452_ext_info[] = {
1204 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mma8452_get_mount_matrix),
1208 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1209 .type = IIO_ACCEL, \
1211 .channel2 = modifier, \
1213 .event_spec = mma8452_freefall_event, \
1214 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1217 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1218 .type = IIO_ACCEL, \
1220 .channel2 = modifier, \
1222 .event_spec = mma8652_freefall_event, \
1223 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1226 #define MMA8452_CHANNEL(axis, idx, bits) { \
1227 .type = IIO_ACCEL, \
1229 .channel2 = IIO_MOD_##axis, \
1230 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1231 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1232 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1233 BIT(IIO_CHAN_INFO_SCALE) | \
1234 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1235 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1236 .scan_index = idx, \
1239 .realbits = (bits), \
1240 .storagebits = 16, \
1241 .shift = 16 - (bits), \
1242 .endianness = IIO_BE, \
1244 .event_spec = mma8452_transient_event, \
1245 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1246 .ext_info = mma8452_ext_info, \
1249 #define MMA8652_CHANNEL(axis, idx, bits) { \
1250 .type = IIO_ACCEL, \
1252 .channel2 = IIO_MOD_##axis, \
1253 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1254 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1255 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1256 BIT(IIO_CHAN_INFO_SCALE) | \
1257 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1258 .scan_index = idx, \
1261 .realbits = (bits), \
1262 .storagebits = 16, \
1263 .shift = 16 - (bits), \
1264 .endianness = IIO_BE, \
1266 .event_spec = mma8452_motion_event, \
1267 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1268 .ext_info = mma8452_ext_info, \
1271 static const struct iio_chan_spec mma8451_channels[] = {
1272 MMA8452_CHANNEL(X, idx_x, 14),
1273 MMA8452_CHANNEL(Y, idx_y, 14),
1274 MMA8452_CHANNEL(Z, idx_z, 14),
1275 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1276 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1279 static const struct iio_chan_spec mma8452_channels[] = {
1280 MMA8452_CHANNEL(X, idx_x, 12),
1281 MMA8452_CHANNEL(Y, idx_y, 12),
1282 MMA8452_CHANNEL(Z, idx_z, 12),
1283 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1284 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1287 static const struct iio_chan_spec mma8453_channels[] = {
1288 MMA8452_CHANNEL(X, idx_x, 10),
1289 MMA8452_CHANNEL(Y, idx_y, 10),
1290 MMA8452_CHANNEL(Z, idx_z, 10),
1291 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1292 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1295 static const struct iio_chan_spec mma8652_channels[] = {
1296 MMA8652_CHANNEL(X, idx_x, 12),
1297 MMA8652_CHANNEL(Y, idx_y, 12),
1298 MMA8652_CHANNEL(Z, idx_z, 12),
1299 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1300 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1303 static const struct iio_chan_spec mma8653_channels[] = {
1304 MMA8652_CHANNEL(X, idx_x, 10),
1305 MMA8652_CHANNEL(Y, idx_y, 10),
1306 MMA8652_CHANNEL(Z, idx_z, 10),
1307 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1308 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1320 static const struct mma_chip_info mma_chip_info_table[] = {
1323 .chip_id = MMA8451_DEVICE_ID,
1324 .channels = mma8451_channels,
1325 .num_channels = ARRAY_SIZE(mma8451_channels),
1327 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1328 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1330 * The userspace interface uses m/s^2 and we declare micro units
1331 * So scale factor for 12 bit here is given by:
1332 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1334 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1336 * Although we enable the interrupt sources once and for
1337 * all here the event detection itself is not enabled until
1338 * userspace asks for it by mma8452_write_event_config()
1340 .all_events = MMA8452_INT_DRDY |
1343 .enabled_events = MMA8452_INT_TRANS |
1348 .chip_id = MMA8452_DEVICE_ID,
1349 .channels = mma8452_channels,
1350 .num_channels = ARRAY_SIZE(mma8452_channels),
1351 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1353 * Although we enable the interrupt sources once and for
1354 * all here the event detection itself is not enabled until
1355 * userspace asks for it by mma8452_write_event_config()
1357 .all_events = MMA8452_INT_DRDY |
1360 .enabled_events = MMA8452_INT_TRANS |
1365 .chip_id = MMA8453_DEVICE_ID,
1366 .channels = mma8453_channels,
1367 .num_channels = ARRAY_SIZE(mma8453_channels),
1368 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1370 * Although we enable the interrupt sources once and for
1371 * all here the event detection itself is not enabled until
1372 * userspace asks for it by mma8452_write_event_config()
1374 .all_events = MMA8452_INT_DRDY |
1377 .enabled_events = MMA8452_INT_TRANS |
1382 .chip_id = MMA8652_DEVICE_ID,
1383 .channels = mma8652_channels,
1384 .num_channels = ARRAY_SIZE(mma8652_channels),
1385 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1386 .all_events = MMA8452_INT_DRDY |
1388 .enabled_events = MMA8452_INT_FF_MT,
1392 .chip_id = MMA8653_DEVICE_ID,
1393 .channels = mma8653_channels,
1394 .num_channels = ARRAY_SIZE(mma8653_channels),
1395 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1397 * Although we enable the interrupt sources once and for
1398 * all here the event detection itself is not enabled until
1399 * userspace asks for it by mma8452_write_event_config()
1401 .all_events = MMA8452_INT_DRDY |
1403 .enabled_events = MMA8452_INT_FF_MT,
1407 .chip_id = FXLS8471_DEVICE_ID,
1408 .channels = mma8451_channels,
1409 .num_channels = ARRAY_SIZE(mma8451_channels),
1410 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1412 * Although we enable the interrupt sources once and for
1413 * all here the event detection itself is not enabled until
1414 * userspace asks for it by mma8452_write_event_config()
1416 .all_events = MMA8452_INT_DRDY |
1419 .enabled_events = MMA8452_INT_TRANS |
1424 static struct attribute *mma8452_attributes[] = {
1425 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1426 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1427 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1428 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1432 static const struct attribute_group mma8452_group = {
1433 .attrs = mma8452_attributes,
1436 static const struct iio_info mma8452_info = {
1437 .attrs = &mma8452_group,
1438 .read_raw = &mma8452_read_raw,
1439 .write_raw = &mma8452_write_raw,
1440 .event_attrs = &mma8452_event_attribute_group,
1441 .read_event_value = &mma8452_read_event_value,
1442 .write_event_value = &mma8452_write_event_value,
1443 .read_event_config = &mma8452_read_event_config,
1444 .write_event_config = &mma8452_write_event_config,
1445 .debugfs_reg_access = &mma8452_reg_access_dbg,
1448 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1450 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1453 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1454 struct mma8452_data *data = iio_priv(indio_dev);
1457 ret = mma8452_set_runtime_pm_state(data->client, state);
1461 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1466 reg |= MMA8452_INT_DRDY;
1468 reg &= ~MMA8452_INT_DRDY;
1470 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1473 static const struct iio_trigger_ops mma8452_trigger_ops = {
1474 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1475 .validate_device = iio_trigger_validate_own_device,
1478 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1480 struct mma8452_data *data = iio_priv(indio_dev);
1481 struct iio_trigger *trig;
1484 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1486 iio_device_id(indio_dev));
1490 trig->ops = &mma8452_trigger_ops;
1491 iio_trigger_set_drvdata(trig, indio_dev);
1493 ret = iio_trigger_register(trig);
1497 indio_dev->trig = iio_trigger_get(trig);
1502 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1504 if (indio_dev->trig)
1505 iio_trigger_unregister(indio_dev->trig);
1508 static int mma8452_reset(struct i2c_client *client)
1513 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1514 MMA8452_CTRL_REG2_RST);
1518 for (i = 0; i < 10; i++) {
1519 usleep_range(100, 200);
1520 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1522 continue; /* I2C comm reset */
1525 if (!(ret & MMA8452_CTRL_REG2_RST))
1532 static const struct of_device_id mma8452_dt_ids[] = {
1533 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1534 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1535 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1536 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1537 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1538 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1541 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1543 static int mma8452_probe(struct i2c_client *client,
1544 const struct i2c_device_id *id)
1546 struct mma8452_data *data;
1547 struct iio_dev *indio_dev;
1550 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1554 data = iio_priv(indio_dev);
1555 data->client = client;
1556 mutex_init(&data->lock);
1558 data->chip_info = device_get_match_data(&client->dev);
1559 if (!data->chip_info && id) {
1560 data->chip_info = &mma_chip_info_table[id->driver_data];
1562 dev_err(&client->dev, "unknown device model\n");
1566 ret = iio_read_mount_matrix(&client->dev, &data->orientation);
1570 data->vdd_reg = devm_regulator_get(&client->dev, "vdd");
1571 if (IS_ERR(data->vdd_reg))
1572 return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg),
1573 "failed to get VDD regulator!\n");
1575 data->vddio_reg = devm_regulator_get(&client->dev, "vddio");
1576 if (IS_ERR(data->vddio_reg))
1577 return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg),
1578 "failed to get VDDIO regulator!\n");
1580 ret = regulator_enable(data->vdd_reg);
1582 dev_err(&client->dev, "failed to enable VDD regulator!\n");
1586 ret = regulator_enable(data->vddio_reg);
1588 dev_err(&client->dev, "failed to enable VDDIO regulator!\n");
1589 goto disable_regulator_vdd;
1592 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1594 goto disable_regulators;
1597 case MMA8451_DEVICE_ID:
1598 case MMA8452_DEVICE_ID:
1599 case MMA8453_DEVICE_ID:
1600 case MMA8652_DEVICE_ID:
1601 case MMA8653_DEVICE_ID:
1602 case FXLS8471_DEVICE_ID:
1603 if (ret == data->chip_info->chip_id)
1608 goto disable_regulators;
1611 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1612 data->chip_info->name, data->chip_info->chip_id);
1614 i2c_set_clientdata(client, indio_dev);
1615 indio_dev->info = &mma8452_info;
1616 indio_dev->name = data->chip_info->name;
1617 indio_dev->modes = INDIO_DIRECT_MODE;
1618 indio_dev->channels = data->chip_info->channels;
1619 indio_dev->num_channels = data->chip_info->num_channels;
1620 indio_dev->available_scan_masks = mma8452_scan_masks;
1622 ret = mma8452_reset(client);
1624 goto disable_regulators;
1626 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1627 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1630 goto disable_regulators;
1633 * By default set transient threshold to max to avoid events if
1634 * enabling without configuring threshold.
1636 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1637 MMA8452_TRANSIENT_THS_MASK);
1639 goto disable_regulators;
1644 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1646 if (irq2 == client->irq) {
1647 dev_dbg(&client->dev, "using interrupt line INT2\n");
1649 ret = i2c_smbus_write_byte_data(client,
1651 data->chip_info->all_events);
1653 goto disable_regulators;
1655 dev_dbg(&client->dev, "using interrupt line INT1\n");
1658 ret = i2c_smbus_write_byte_data(client,
1660 data->chip_info->enabled_events);
1662 goto disable_regulators;
1664 ret = mma8452_trigger_setup(indio_dev);
1666 goto disable_regulators;
1669 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1670 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1672 data->sleep_val = mma8452_calculate_sleep(data);
1674 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1677 goto trigger_cleanup;
1679 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1680 mma8452_trigger_handler, NULL);
1682 goto trigger_cleanup;
1685 ret = devm_request_threaded_irq(&client->dev,
1687 NULL, mma8452_interrupt,
1688 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1689 client->name, indio_dev);
1691 goto buffer_cleanup;
1694 ret = pm_runtime_set_active(&client->dev);
1696 goto buffer_cleanup;
1698 pm_runtime_enable(&client->dev);
1699 pm_runtime_set_autosuspend_delay(&client->dev,
1700 MMA8452_AUTO_SUSPEND_DELAY_MS);
1701 pm_runtime_use_autosuspend(&client->dev);
1703 ret = iio_device_register(indio_dev);
1705 goto buffer_cleanup;
1707 ret = mma8452_set_freefall_mode(data, false);
1709 goto unregister_device;
1714 iio_device_unregister(indio_dev);
1717 iio_triggered_buffer_cleanup(indio_dev);
1720 mma8452_trigger_cleanup(indio_dev);
1723 regulator_disable(data->vddio_reg);
1725 disable_regulator_vdd:
1726 regulator_disable(data->vdd_reg);
1731 static int mma8452_remove(struct i2c_client *client)
1733 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1734 struct mma8452_data *data = iio_priv(indio_dev);
1736 iio_device_unregister(indio_dev);
1738 pm_runtime_disable(&client->dev);
1739 pm_runtime_set_suspended(&client->dev);
1741 iio_triggered_buffer_cleanup(indio_dev);
1742 mma8452_trigger_cleanup(indio_dev);
1743 mma8452_standby(iio_priv(indio_dev));
1745 regulator_disable(data->vddio_reg);
1746 regulator_disable(data->vdd_reg);
1752 static int mma8452_runtime_suspend(struct device *dev)
1754 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1755 struct mma8452_data *data = iio_priv(indio_dev);
1758 mutex_lock(&data->lock);
1759 ret = mma8452_standby(data);
1760 mutex_unlock(&data->lock);
1762 dev_err(&data->client->dev, "powering off device failed\n");
1766 ret = regulator_disable(data->vddio_reg);
1768 dev_err(dev, "failed to disable VDDIO regulator\n");
1772 ret = regulator_disable(data->vdd_reg);
1774 dev_err(dev, "failed to disable VDD regulator\n");
1781 static int mma8452_runtime_resume(struct device *dev)
1783 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1784 struct mma8452_data *data = iio_priv(indio_dev);
1787 ret = regulator_enable(data->vdd_reg);
1789 dev_err(dev, "failed to enable VDD regulator\n");
1793 ret = regulator_enable(data->vddio_reg);
1795 dev_err(dev, "failed to enable VDDIO regulator\n");
1796 regulator_disable(data->vdd_reg);
1800 ret = mma8452_active(data);
1802 goto runtime_resume_failed;
1804 ret = mma8452_get_odr_index(data);
1805 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1807 usleep_range(sleep_val * 1000, 20000);
1809 msleep_interruptible(sleep_val);
1813 runtime_resume_failed:
1814 regulator_disable(data->vddio_reg);
1815 regulator_disable(data->vdd_reg);
1821 static const struct dev_pm_ops mma8452_pm_ops = {
1822 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1823 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1824 mma8452_runtime_resume, NULL)
1827 static const struct i2c_device_id mma8452_id[] = {
1828 { "mma8451", mma8451 },
1829 { "mma8452", mma8452 },
1830 { "mma8453", mma8453 },
1831 { "mma8652", mma8652 },
1832 { "mma8653", mma8653 },
1833 { "fxls8471", fxls8471 },
1836 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1838 static struct i2c_driver mma8452_driver = {
1841 .of_match_table = mma8452_dt_ids,
1842 .pm = &mma8452_pm_ops,
1844 .probe = mma8452_probe,
1845 .remove = mma8452_remove,
1846 .id_table = mma8452_id,
1848 module_i2c_driver(mma8452_driver);
1850 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1851 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1852 MODULE_LICENSE("GPL");