drivers/iio/accel/bmc150-accel-core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
   4  *  - BMC150
   5  *  - BMI055
   6  *  - BMA255
   7  *  - BMA250E
   8  *  - BMA222
   9  *  - BMA222E
  10  *  - BMA280
  11  *
  12  * Copyright (c) 2014, Intel Corporation.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/i2c.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/delay.h>
  19 #include <linux/slab.h>
  20 #include <linux/acpi.h>
  21 #include <linux/pm.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/iio/iio.h>
  24 #include <linux/iio/sysfs.h>
  25 #include <linux/iio/buffer.h>
  26 #include <linux/iio/events.h>
  27 #include <linux/iio/trigger.h>
  28 #include <linux/iio/trigger_consumer.h>
  29 #include <linux/iio/triggered_buffer.h>
  30 #include <linux/regmap.h>
  31 #include <linux/regulator/consumer.h>
  32
  33 #include "bmc150-accel.h"
  34
  35 #define BMC150_ACCEL_DRV_NAME                   "bmc150_accel"
  36 #define BMC150_ACCEL_IRQ_NAME                   "bmc150_accel_event"
  37
  38 #define BMC150_ACCEL_REG_CHIP_ID                0x00
  39
  40 #define BMC150_ACCEL_REG_INT_STATUS_2           0x0B
  41 #define BMC150_ACCEL_ANY_MOTION_MASK            0x07
  42 #define BMC150_ACCEL_ANY_MOTION_BIT_X           BIT(0)
  43 #define BMC150_ACCEL_ANY_MOTION_BIT_Y           BIT(1)
  44 #define BMC150_ACCEL_ANY_MOTION_BIT_Z           BIT(2)
  45 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN        BIT(3)
  46
  47 #define BMC150_ACCEL_REG_PMU_LPW                0x11
  48 #define BMC150_ACCEL_PMU_MODE_MASK              0xE0
  49 #define BMC150_ACCEL_PMU_MODE_SHIFT             5
  50 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK     0x17
  51 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT    1
  52
  53 #define BMC150_ACCEL_REG_PMU_RANGE              0x0F
  54
  55 #define BMC150_ACCEL_DEF_RANGE_2G               0x03
  56 #define BMC150_ACCEL_DEF_RANGE_4G               0x05
  57 #define BMC150_ACCEL_DEF_RANGE_8G               0x08
  58 #define BMC150_ACCEL_DEF_RANGE_16G              0x0C
  59
  60 /* Default BW: 125Hz */
  61 #define BMC150_ACCEL_REG_PMU_BW         0x10
  62 #define BMC150_ACCEL_DEF_BW                     125
  63
  64 #define BMC150_ACCEL_REG_RESET                  0x14
  65 #define BMC150_ACCEL_RESET_VAL                  0xB6
  66
  67 #define BMC150_ACCEL_REG_INT_MAP_0              0x19
  68 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE        BIT(2)
  69
  70 #define BMC150_ACCEL_REG_INT_MAP_1              0x1A
  71 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA         BIT(0)
  72 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM          BIT(1)
  73 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL        BIT(2)
  74
  75 #define BMC150_ACCEL_REG_INT_RST_LATCH          0x21
  76 #define BMC150_ACCEL_INT_MODE_LATCH_RESET       0x80
  77 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
  78 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT     0x00
  79
  80 #define BMC150_ACCEL_REG_INT_EN_0               0x16
  81 #define BMC150_ACCEL_INT_EN_BIT_SLP_X           BIT(0)
  82 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y           BIT(1)
  83 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z           BIT(2)
  84
  85 #define BMC150_ACCEL_REG_INT_EN_1               0x17
  86 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN         BIT(4)
  87 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN        BIT(5)
  88 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN          BIT(6)
  89
  90 #define BMC150_ACCEL_REG_INT_OUT_CTRL           0x20
  91 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL      BIT(0)
  92
  93 #define BMC150_ACCEL_REG_INT_5                  0x27
  94 #define BMC150_ACCEL_SLOPE_DUR_MASK             0x03
  95
  96 #define BMC150_ACCEL_REG_INT_6                  0x28
  97 #define BMC150_ACCEL_SLOPE_THRES_MASK           0xFF
  98
  99 /* Slope duration in terms of number of samples */
 100 #define BMC150_ACCEL_DEF_SLOPE_DURATION         1
 101 /* in terms of multiples of g's/LSB, based on range */
 102 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD        1
 103
 104 #define BMC150_ACCEL_REG_XOUT_L         0x02
 105
 106 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS        100
 107
 108 /* Sleep Duration values */
 109 #define BMC150_ACCEL_SLEEP_500_MICRO            0x05
 110 #define BMC150_ACCEL_SLEEP_1_MS         0x06
 111 #define BMC150_ACCEL_SLEEP_2_MS         0x07
 112 #define BMC150_ACCEL_SLEEP_4_MS         0x08
 113 #define BMC150_ACCEL_SLEEP_6_MS         0x09
 114 #define BMC150_ACCEL_SLEEP_10_MS                0x0A
 115 #define BMC150_ACCEL_SLEEP_25_MS                0x0B
 116 #define BMC150_ACCEL_SLEEP_50_MS                0x0C
 117 #define BMC150_ACCEL_SLEEP_100_MS               0x0D
 118 #define BMC150_ACCEL_SLEEP_500_MS               0x0E
 119 #define BMC150_ACCEL_SLEEP_1_SEC                0x0F
 120
 121 #define BMC150_ACCEL_REG_TEMP                   0x08
 122 #define BMC150_ACCEL_TEMP_CENTER_VAL            23
 123
 124 #define BMC150_ACCEL_AXIS_TO_REG(axis)  (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
 125 #define BMC150_AUTO_SUSPEND_DELAY_MS            2000
 126
 127 #define BMC150_ACCEL_REG_FIFO_STATUS            0x0E
 128 #define BMC150_ACCEL_REG_FIFO_CONFIG0           0x30
 129 #define BMC150_ACCEL_REG_FIFO_CONFIG1           0x3E
 130 #define BMC150_ACCEL_REG_FIFO_DATA              0x3F
 131 #define BMC150_ACCEL_FIFO_LENGTH                32
 132
 133 enum bmc150_accel_axis {
 134         AXIS_X,
 135         AXIS_Y,
 136         AXIS_Z,
 137         AXIS_MAX,
 138 };
 139
 140 enum bmc150_power_modes {
 141         BMC150_ACCEL_SLEEP_MODE_NORMAL,
 142         BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
 143         BMC150_ACCEL_SLEEP_MODE_LPM,
 144         BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
 145 };
 146
 147 struct bmc150_scale_info {
 148         int scale;
 149         u8 reg_range;
 150 };
 151
 152 struct bmc150_accel_chip_info {
 153         const char *name;
 154         u8 chip_id;
 155         const struct iio_chan_spec *channels;
 156         int num_channels;
 157         const struct bmc150_scale_info scale_table[4];
 158 };
 159
 160 struct bmc150_accel_interrupt {
 161         const struct bmc150_accel_interrupt_info *info;
 162         atomic_t users;
 163 };
 164
 165 struct bmc150_accel_trigger {
 166         struct bmc150_accel_data *data;
 167         struct iio_trigger *indio_trig;
 168         int (*setup)(struct bmc150_accel_trigger *t, bool state);
 169         int intr;
 170         bool enabled;
 171 };
 172
 173 enum bmc150_accel_interrupt_id {
 174         BMC150_ACCEL_INT_DATA_READY,
 175         BMC150_ACCEL_INT_ANY_MOTION,
 176         BMC150_ACCEL_INT_WATERMARK,
 177         BMC150_ACCEL_INTERRUPTS,
 178 };
 179
 180 enum bmc150_accel_trigger_id {
 181         BMC150_ACCEL_TRIGGER_DATA_READY,
 182         BMC150_ACCEL_TRIGGER_ANY_MOTION,
 183         BMC150_ACCEL_TRIGGERS,
 184 };
 185
 186 struct bmc150_accel_data {
 187         struct regmap *regmap;
 188         struct regulator_bulk_data regulators[2];
 189         struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
 190         struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
 191         struct mutex mutex;
 192         u8 fifo_mode, watermark;
 193         s16 buffer[8];
 194         /*
 195          * Ensure there is sufficient space and correct alignment for
 196          * the timestamp if enabled
 197          */
 198         struct {
 199                 __le16 channels[3];
 200                 s64 ts __aligned(8);
 201         } scan;
 202         u8 bw_bits;
 203         u32 slope_dur;
 204         u32 slope_thres;
 205         u32 range;
 206         int ev_enable_state;
 207         int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
 208         const struct bmc150_accel_chip_info *chip_info;
 209         struct i2c_client *second_device;
 210         struct iio_mount_matrix orientation;
 211 };
 212
 213 static const struct {
 214         int val;
 215         int val2;
 216         u8 bw_bits;
 217 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
 218                                      {31, 260000, 0x09},
 219                                      {62, 500000, 0x0A},
 220                                      {125, 0, 0x0B},
 221                                      {250, 0, 0x0C},
 222                                      {500, 0, 0x0D},
 223                                      {1000, 0, 0x0E},
 224                                      {2000, 0, 0x0F} };
 225
 226 static const struct {
 227         int bw_bits;
 228         int msec;
 229 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
 230                                      {0x09, 32},
 231                                      {0x0A, 16},
 232                                      {0x0B, 8},
 233                                      {0x0C, 4},
 234                                      {0x0D, 2},
 235                                      {0x0E, 1},
 236                                      {0x0F, 1} };
 237
 238 static const struct {
 239         int sleep_dur;
 240         u8 reg_value;
 241 } bmc150_accel_sleep_value_table[] = { {0, 0},
 242                                        {500, BMC150_ACCEL_SLEEP_500_MICRO},
 243                                        {1000, BMC150_ACCEL_SLEEP_1_MS},
 244                                        {2000, BMC150_ACCEL_SLEEP_2_MS},
 245                                        {4000, BMC150_ACCEL_SLEEP_4_MS},
 246                                        {6000, BMC150_ACCEL_SLEEP_6_MS},
 247                                        {10000, BMC150_ACCEL_SLEEP_10_MS},
 248                                        {25000, BMC150_ACCEL_SLEEP_25_MS},
 249                                        {50000, BMC150_ACCEL_SLEEP_50_MS},
 250                                        {100000, BMC150_ACCEL_SLEEP_100_MS},
 251                                        {500000, BMC150_ACCEL_SLEEP_500_MS},
 252                                        {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
 253
 254 const struct regmap_config bmc150_regmap_conf = {
 255         .reg_bits = 8,
 256         .val_bits = 8,
 257         .max_register = 0x3f,
 258 };
 259 EXPORT_SYMBOL_GPL(bmc150_regmap_conf);
 260
 261 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
 262                                  enum bmc150_power_modes mode,
 263                                  int dur_us)
 264 {
 265         struct device *dev = regmap_get_device(data->regmap);
 266         int i;
 267         int ret;
 268         u8 lpw_bits;
 269         int dur_val = -1;
 270
 271         if (dur_us > 0) {
 272                 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
 273                                                                          ++i) {
 274                         if (bmc150_accel_sleep_value_table[i].sleep_dur ==
 275                                                                         dur_us)
 276                                 dur_val =
 277                                 bmc150_accel_sleep_value_table[i].reg_value;
 278                 }
 279         } else {
 280                 dur_val = 0;
 281         }
 282
 283         if (dur_val < 0)
 284                 return -EINVAL;
 285
 286         lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
 287         lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
 288
 289         dev_dbg(dev, "Set Mode bits %x\n", lpw_bits);
 290
 291         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
 292         if (ret < 0) {
 293                 dev_err(dev, "Error writing reg_pmu_lpw\n");
 294                 return ret;
 295         }
 296
 297         return 0;
 298 }
 299
 300 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
 301                                int val2)
 302 {
 303         int i;
 304         int ret;
 305
 306         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 307                 if (bmc150_accel_samp_freq_table[i].val == val &&
 308                     bmc150_accel_samp_freq_table[i].val2 == val2) {
 309                         ret = regmap_write(data->regmap,
 310                                 BMC150_ACCEL_REG_PMU_BW,
 311                                 bmc150_accel_samp_freq_table[i].bw_bits);
 312                         if (ret < 0)
 313                                 return ret;
 314
 315                         data->bw_bits =
 316                                 bmc150_accel_samp_freq_table[i].bw_bits;
 317                         return 0;
 318                 }
 319         }
 320
 321         return -EINVAL;
 322 }
 323
 324 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
 325 {
 326         struct device *dev = regmap_get_device(data->regmap);
 327         int ret;
 328
 329         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
 330                                         data->slope_thres);
 331         if (ret < 0) {
 332                 dev_err(dev, "Error writing reg_int_6\n");
 333                 return ret;
 334         }
 335
 336         ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
 337                                  BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
 338         if (ret < 0) {
 339                 dev_err(dev, "Error updating reg_int_5\n");
 340                 return ret;
 341         }
 342
 343         dev_dbg(dev, "%x %x\n", data->slope_thres, data->slope_dur);
 344
 345         return ret;
 346 }
 347
 348 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
 349                                          bool state)
 350 {
 351         if (state)
 352                 return bmc150_accel_update_slope(t->data);
 353
 354         return 0;
 355 }
 356
 357 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
 358                                int *val2)
 359 {
 360         int i;
 361
 362         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 363                 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
 364                         *val = bmc150_accel_samp_freq_table[i].val;
 365                         *val2 = bmc150_accel_samp_freq_table[i].val2;
 366                         return IIO_VAL_INT_PLUS_MICRO;
 367                 }
 368         }
 369
 370         return -EINVAL;
 371 }
 372
 373 #ifdef CONFIG_PM
 374 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
 375 {
 376         int i;
 377
 378         for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
 379                 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
 380                         return bmc150_accel_sample_upd_time[i].msec;
 381         }
 382
 383         return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
 384 }
 385
 386 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 387 {
 388         struct device *dev = regmap_get_device(data->regmap);
 389         int ret;
 390
 391         if (on) {
 392                 ret = pm_runtime_resume_and_get(dev);
 393         } else {
 394                 pm_runtime_mark_last_busy(dev);
 395                 ret = pm_runtime_put_autosuspend(dev);
 396         }
 397
 398         if (ret < 0) {
 399                 dev_err(dev,
 400                         "Failed: %s for %d\n", __func__, on);
 401                 return ret;
 402         }
 403
 404         return 0;
 405 }
 406 #else
 407 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 408 {
 409         return 0;
 410 }
 411 #endif
 412
 413 #ifdef CONFIG_ACPI
 414 /*
 415  * Support for getting accelerometer information from BOSC0200 ACPI nodes.
 416  *
 417  * There are 2 variants of the BOSC0200 ACPI node. Some 2-in-1s with 360 degree
 418  * hinges declare 2 I2C ACPI-resources for 2 accelerometers, 1 in the display
 419  * and 1 in the base of the 2-in-1. On these 2-in-1s the ROMS ACPI object
 420  * contains the mount-matrix for the sensor in the display and ROMK contains
 421  * the mount-matrix for the sensor in the base. On devices using a single
 422  * sensor there is a ROTM ACPI object which contains the mount-matrix.
 423  *
 424  * Here is an incomplete list of devices known to use 1 of these setups:
 425  *
 426  * Yoga devices with 2 accelerometers using ROMS + ROMK for the mount-matrices:
 427  * Lenovo Thinkpad Yoga 11e 3th gen
 428  * Lenovo Thinkpad Yoga 11e 4th gen
 429  *
 430  * Tablets using a single accelerometer using ROTM for the mount-matrix:
 431  * Chuwi Hi8 Pro (CWI513)
 432  * Chuwi Vi8 Plus (CWI519)
 433  * Chuwi Hi13
 434  * Irbis TW90
 435  * Jumper EZpad mini 3
 436  * Onda V80 plus
 437  * Predia Basic Tablet
 438  */
 439 static bool bmc150_apply_acpi_orientation(struct device *dev,
 440                                           struct iio_mount_matrix *orientation)
 441 {
 442         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
 443         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 444         struct acpi_device *adev = ACPI_COMPANION(dev);
 445         char *name, *alt_name, *label, *str;
 446         union acpi_object *obj, *elements;
 447         acpi_status status;
 448         int i, j, val[3];
 449
 450         if (!adev || !acpi_dev_hid_uid_match(adev, "BOSC0200", NULL))
 451                 return false;
 452
 453         if (strcmp(dev_name(dev), "i2c-BOSC0200:base") == 0) {
 454                 alt_name = "ROMK";
 455                 label = "accel-base";
 456         } else {
 457                 alt_name = "ROMS";
 458                 label = "accel-display";
 459         }
 460
 461         if (acpi_has_method(adev->handle, "ROTM")) {
 462                 name = "ROTM";
 463         } else if (acpi_has_method(adev->handle, alt_name)) {
 464                 name = alt_name;
 465                 indio_dev->label = label;
 466         } else {
 467                 return false;
 468         }
 469
 470         status = acpi_evaluate_object(adev->handle, name, NULL, &buffer);
 471         if (ACPI_FAILURE(status)) {
 472                 dev_warn(dev, "Failed to get ACPI mount matrix: %d\n", status);
 473                 return false;
 474         }
 475
 476         obj = buffer.pointer;
 477         if (obj->type != ACPI_TYPE_PACKAGE || obj->package.count != 3)
 478                 goto unknown_format;
 479
 480         elements = obj->package.elements;
 481         for (i = 0; i < 3; i++) {
 482                 if (elements[i].type != ACPI_TYPE_STRING)
 483                         goto unknown_format;
 484
 485                 str = elements[i].string.pointer;
 486                 if (sscanf(str, "%d %d %d", &val[0], &val[1], &val[2]) != 3)
 487                         goto unknown_format;
 488
 489                 for (j = 0; j < 3; j++) {
 490                         switch (val[j]) {
 491                         case -1: str = "-1"; break;
 492                         case 0:  str = "0";  break;
 493                         case 1:  str = "1";  break;
 494                         default: goto unknown_format;
 495                         }
 496                         orientation->rotation[i * 3 + j] = str;
 497                 }
 498         }
 499
 500         kfree(buffer.pointer);
 501         return true;
 502
 503 unknown_format:
 504         dev_warn(dev, "Unknown ACPI mount matrix format, ignoring\n");
 505         kfree(buffer.pointer);
 506         return false;
 507 }
 508 #else
 509 static bool bmc150_apply_acpi_orientation(struct device *dev,
 510                                           struct iio_mount_matrix *orientation)
 511 {
 512         return false;
 513 }
 514 #endif
 515
 516 static const struct bmc150_accel_interrupt_info {
 517         u8 map_reg;
 518         u8 map_bitmask;
 519         u8 en_reg;
 520         u8 en_bitmask;
 521 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
 522         { /* data ready interrupt */
 523                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 524                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
 525                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 526                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
 527         },
 528         {  /* motion interrupt */
 529                 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
 530                 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
 531                 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
 532                 .en_bitmask =  BMC150_ACCEL_INT_EN_BIT_SLP_X |
 533                         BMC150_ACCEL_INT_EN_BIT_SLP_Y |
 534                         BMC150_ACCEL_INT_EN_BIT_SLP_Z
 535         },
 536         { /* fifo watermark interrupt */
 537                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 538                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
 539                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 540                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
 541         },
 542 };
 543
 544 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
 545                                           struct bmc150_accel_data *data)
 546 {
 547         int i;
 548
 549         for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
 550                 data->interrupts[i].info = &bmc150_accel_interrupts[i];
 551 }
 552
 553 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
 554                                       bool state)
 555 {
 556         struct device *dev = regmap_get_device(data->regmap);
 557         struct bmc150_accel_interrupt *intr = &data->interrupts[i];
 558         const struct bmc150_accel_interrupt_info *info = intr->info;
 559         int ret;
 560
 561         if (state) {
 562                 if (atomic_inc_return(&intr->users) > 1)
 563                         return 0;
 564         } else {
 565                 if (atomic_dec_return(&intr->users) > 0)
 566                         return 0;
 567         }
 568
 569         /*
 570          * We will expect the enable and disable to do operation in reverse
 571          * order. This will happen here anyway, as our resume operation uses
 572          * sync mode runtime pm calls. The suspend operation will be delayed
 573          * by autosuspend delay.
 574          * So the disable operation will still happen in reverse order of
 575          * enable operation. When runtime pm is disabled the mode is always on,
 576          * so sequence doesn't matter.
 577          */
 578         ret = bmc150_accel_set_power_state(data, state);
 579         if (ret < 0)
 580                 return ret;
 581
 582         /* map the interrupt to the appropriate pins */
 583         ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
 584                                  (state ? info->map_bitmask : 0));
 585         if (ret < 0) {
 586                 dev_err(dev, "Error updating reg_int_map\n");
 587                 goto out_fix_power_state;
 588         }
 589
 590         /* enable/disable the interrupt */
 591         ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
 592                                  (state ? info->en_bitmask : 0));
 593         if (ret < 0) {
 594                 dev_err(dev, "Error updating reg_int_en\n");
 595                 goto out_fix_power_state;
 596         }
 597
 598         return 0;
 599
 600 out_fix_power_state:
 601         bmc150_accel_set_power_state(data, false);
 602         return ret;
 603 }
 604
 605 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
 606 {
 607         struct device *dev = regmap_get_device(data->regmap);
 608         int ret, i;
 609
 610         for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
 611                 if (data->chip_info->scale_table[i].scale == val) {
 612                         ret = regmap_write(data->regmap,
 613                                      BMC150_ACCEL_REG_PMU_RANGE,
 614                                      data->chip_info->scale_table[i].reg_range);
 615                         if (ret < 0) {
 616                                 dev_err(dev, "Error writing pmu_range\n");
 617                                 return ret;
 618                         }
 619
 620                         data->range = data->chip_info->scale_table[i].reg_range;
 621                         return 0;
 622                 }
 623         }
 624
 625         return -EINVAL;
 626 }
 627
 628 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
 629 {
 630         struct device *dev = regmap_get_device(data->regmap);
 631         int ret;
 632         unsigned int value;
 633
 634         mutex_lock(&data->mutex);
 635
 636         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
 637         if (ret < 0) {
 638                 dev_err(dev, "Error reading reg_temp\n");
 639                 mutex_unlock(&data->mutex);
 640                 return ret;
 641         }
 642         *val = sign_extend32(value, 7);
 643
 644         mutex_unlock(&data->mutex);
 645
 646         return IIO_VAL_INT;
 647 }
 648
 649 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
 650                                  struct iio_chan_spec const *chan,
 651                                  int *val)
 652 {
 653         struct device *dev = regmap_get_device(data->regmap);
 654         int ret;
 655         int axis = chan->scan_index;
 656         __le16 raw_val;
 657
 658         mutex_lock(&data->mutex);
 659         ret = bmc150_accel_set_power_state(data, true);
 660         if (ret < 0) {
 661                 mutex_unlock(&data->mutex);
 662                 return ret;
 663         }
 664
 665         ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
 666                                &raw_val, sizeof(raw_val));
 667         if (ret < 0) {
 668                 dev_err(dev, "Error reading axis %d\n", axis);
 669                 bmc150_accel_set_power_state(data, false);
 670                 mutex_unlock(&data->mutex);
 671                 return ret;
 672         }
 673         *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
 674                              chan->scan_type.realbits - 1);
 675         ret = bmc150_accel_set_power_state(data, false);
 676         mutex_unlock(&data->mutex);
 677         if (ret < 0)
 678                 return ret;
 679
 680         return IIO_VAL_INT;
 681 }
 682
 683 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
 684                                  struct iio_chan_spec const *chan,
 685                                  int *val, int *val2, long mask)
 686 {
 687         struct bmc150_accel_data *data = iio_priv(indio_dev);
 688         int ret;
 689
 690         switch (mask) {
 691         case IIO_CHAN_INFO_RAW:
 692                 switch (chan->type) {
 693                 case IIO_TEMP:
 694                         return bmc150_accel_get_temp(data, val);
 695                 case IIO_ACCEL:
 696                         if (iio_buffer_enabled(indio_dev))
 697                                 return -EBUSY;
 698                         else
 699                                 return bmc150_accel_get_axis(data, chan, val);
 700                 default:
 701                         return -EINVAL;
 702                 }
 703         case IIO_CHAN_INFO_OFFSET:
 704                 if (chan->type == IIO_TEMP) {
 705                         *val = BMC150_ACCEL_TEMP_CENTER_VAL;
 706                         return IIO_VAL_INT;
 707                 } else {
 708                         return -EINVAL;
 709                 }
 710         case IIO_CHAN_INFO_SCALE:
 711                 *val = 0;
 712                 switch (chan->type) {
 713                 case IIO_TEMP:
 714                         *val2 = 500000;
 715                         return IIO_VAL_INT_PLUS_MICRO;
 716                 case IIO_ACCEL:
 717                 {
 718                         int i;
 719                         const struct bmc150_scale_info *si;
 720                         int st_size = ARRAY_SIZE(data->chip_info->scale_table);
 721
 722                         for (i = 0; i < st_size; ++i) {
 723                                 si = &data->chip_info->scale_table[i];
 724                                 if (si->reg_range == data->range) {
 725                                         *val2 = si->scale;
 726                                         return IIO_VAL_INT_PLUS_MICRO;
 727                                 }
 728                         }
 729                         return -EINVAL;
 730                 }
 731                 default:
 732                         return -EINVAL;
 733                 }
 734         case IIO_CHAN_INFO_SAMP_FREQ:
 735                 mutex_lock(&data->mutex);
 736                 ret = bmc150_accel_get_bw(data, val, val2);
 737                 mutex_unlock(&data->mutex);
 738                 return ret;
 739         default:
 740                 return -EINVAL;
 741         }
 742 }
 743
 744 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
 745                                   struct iio_chan_spec const *chan,
 746                                   int val, int val2, long mask)
 747 {
 748         struct bmc150_accel_data *data = iio_priv(indio_dev);
 749         int ret;
 750
 751         switch (mask) {
 752         case IIO_CHAN_INFO_SAMP_FREQ:
 753                 mutex_lock(&data->mutex);
 754                 ret = bmc150_accel_set_bw(data, val, val2);
 755                 mutex_unlock(&data->mutex);
 756                 break;
 757         case IIO_CHAN_INFO_SCALE:
 758                 if (val)
 759                         return -EINVAL;
 760
 761                 mutex_lock(&data->mutex);
 762                 ret = bmc150_accel_set_scale(data, val2);
 763                 mutex_unlock(&data->mutex);
 764                 return ret;
 765         default:
 766                 ret = -EINVAL;
 767         }
 768
 769         return ret;
 770 }
 771
 772 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
 773                                    const struct iio_chan_spec *chan,
 774                                    enum iio_event_type type,
 775                                    enum iio_event_direction dir,
 776                                    enum iio_event_info info,
 777                                    int *val, int *val2)
 778 {
 779         struct bmc150_accel_data *data = iio_priv(indio_dev);
 780
 781         *val2 = 0;
 782         switch (info) {
 783         case IIO_EV_INFO_VALUE:
 784                 *val = data->slope_thres;
 785                 break;
 786         case IIO_EV_INFO_PERIOD:
 787                 *val = data->slope_dur;
 788                 break;
 789         default:
 790                 return -EINVAL;
 791         }
 792
 793         return IIO_VAL_INT;
 794 }
 795
 796 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
 797                                     const struct iio_chan_spec *chan,
 798                                     enum iio_event_type type,
 799                                     enum iio_event_direction dir,
 800                                     enum iio_event_info info,
 801                                     int val, int val2)
 802 {
 803         struct bmc150_accel_data *data = iio_priv(indio_dev);
 804
 805         if (data->ev_enable_state)
 806                 return -EBUSY;
 807
 808         switch (info) {
 809         case IIO_EV_INFO_VALUE:
 810                 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
 811                 break;
 812         case IIO_EV_INFO_PERIOD:
 813                 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
 814                 break;
 815         default:
 816                 return -EINVAL;
 817         }
 818
 819         return 0;
 820 }
 821
 822 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
 823                                           const struct iio_chan_spec *chan,
 824                                           enum iio_event_type type,
 825                                           enum iio_event_direction dir)
 826 {
 827         struct bmc150_accel_data *data = iio_priv(indio_dev);
 828
 829         return data->ev_enable_state;
 830 }
 831
 832 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
 833                                            const struct iio_chan_spec *chan,
 834                                            enum iio_event_type type,
 835                                            enum iio_event_direction dir,
 836                                            int state)
 837 {
 838         struct bmc150_accel_data *data = iio_priv(indio_dev);
 839         int ret;
 840
 841         if (state == data->ev_enable_state)
 842                 return 0;
 843
 844         mutex_lock(&data->mutex);
 845
 846         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
 847                                          state);
 848         if (ret < 0) {
 849                 mutex_unlock(&data->mutex);
 850                 return ret;
 851         }
 852
 853         data->ev_enable_state = state;
 854         mutex_unlock(&data->mutex);
 855
 856         return 0;
 857 }
 858
 859 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
 860                                          struct iio_trigger *trig)
 861 {
 862         struct bmc150_accel_data *data = iio_priv(indio_dev);
 863         int i;
 864
 865         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
 866                 if (data->triggers[i].indio_trig == trig)
 867                         return 0;
 868         }
 869
 870         return -EINVAL;
 871 }
 872
 873 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
 874                                                struct device_attribute *attr,
 875                                                char *buf)
 876 {
 877         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 878         struct bmc150_accel_data *data = iio_priv(indio_dev);
 879         int wm;
 880
 881         mutex_lock(&data->mutex);
 882         wm = data->watermark;
 883         mutex_unlock(&data->mutex);
 884
 885         return sprintf(buf, "%d\n", wm);
 886 }
 887
 888 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
 889                                            struct device_attribute *attr,
 890                                            char *buf)
 891 {
 892         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 893         struct bmc150_accel_data *data = iio_priv(indio_dev);
 894         bool state;
 895
 896         mutex_lock(&data->mutex);
 897         state = data->fifo_mode;
 898         mutex_unlock(&data->mutex);
 899
 900         return sprintf(buf, "%d\n", state);
 901 }
 902
 903 static const struct iio_mount_matrix *
 904 bmc150_accel_get_mount_matrix(const struct iio_dev *indio_dev,
 905                                 const struct iio_chan_spec *chan)
 906 {
 907         struct bmc150_accel_data *data = iio_priv(indio_dev);
 908
 909         return &data->orientation;
 910 }
 911
 912 static const struct iio_chan_spec_ext_info bmc150_accel_ext_info[] = {
 913         IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmc150_accel_get_mount_matrix),
 914         { }
 915 };
 916
 917 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
 918 static IIO_CONST_ATTR(hwfifo_watermark_max,
 919                       __stringify(BMC150_ACCEL_FIFO_LENGTH));
 920 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
 921                        bmc150_accel_get_fifo_state, NULL, 0);
 922 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
 923                        bmc150_accel_get_fifo_watermark, NULL, 0);
 924
 925 static const struct attribute *bmc150_accel_fifo_attributes[] = {
 926         &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
 927         &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
 928         &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
 929         &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
 930         NULL,
 931 };
 932
 933 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
 934 {
 935         struct bmc150_accel_data *data = iio_priv(indio_dev);
 936
 937         if (val > BMC150_ACCEL_FIFO_LENGTH)
 938                 val = BMC150_ACCEL_FIFO_LENGTH;
 939
 940         mutex_lock(&data->mutex);
 941         data->watermark = val;
 942         mutex_unlock(&data->mutex);
 943
 944         return 0;
 945 }
 946
 947 /*
 948  * We must read at least one full frame in one burst, otherwise the rest of the
 949  * frame data is discarded.
 950  */
 951 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
 952                                       char *buffer, int samples)
 953 {
 954         struct device *dev = regmap_get_device(data->regmap);
 955         int sample_length = 3 * 2;
 956         int ret;
 957         int total_length = samples * sample_length;
 958
 959         ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
 960                               buffer, total_length);
 961         if (ret)
 962                 dev_err(dev,
 963                         "Error transferring data from fifo: %d\n", ret);
 964
 965         return ret;
 966 }
 967
 968 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
 969                                      unsigned samples, bool irq)
 970 {
 971         struct bmc150_accel_data *data = iio_priv(indio_dev);
 972         struct device *dev = regmap_get_device(data->regmap);
 973         int ret, i;
 974         u8 count;
 975         u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
 976         int64_t tstamp;
 977         uint64_t sample_period;
 978         unsigned int val;
 979
 980         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
 981         if (ret < 0) {
 982                 dev_err(dev, "Error reading reg_fifo_status\n");
 983                 return ret;
 984         }
 985
 986         count = val & 0x7F;
 987
 988         if (!count)
 989                 return 0;
 990
 991         /*
 992          * If we getting called from IRQ handler we know the stored timestamp is
 993          * fairly accurate for the last stored sample. Otherwise, if we are
 994          * called as a result of a read operation from userspace and hence
 995          * before the watermark interrupt was triggered, take a timestamp
 996          * now. We can fall anywhere in between two samples so the error in this
 997          * case is at most one sample period.
 998          */
 999         if (!irq) {
1000                 data->old_timestamp = data->timestamp;
1001                 data->timestamp = iio_get_time_ns(indio_dev);
1002         }
1003
1004         /*
1005          * Approximate timestamps for each of the sample based on the sampling
1006          * frequency, timestamp for last sample and number of samples.
1007          *
1008          * Note that we can't use the current bandwidth settings to compute the
1009          * sample period because the sample rate varies with the device
1010          * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
1011          * small variation adds when we store a large number of samples and
1012          * creates significant jitter between the last and first samples in
1013          * different batches (e.g. 32ms vs 21ms).
1014          *
1015          * To avoid this issue we compute the actual sample period ourselves
1016          * based on the timestamp delta between the last two flush operations.
1017          */
1018         sample_period = (data->timestamp - data->old_timestamp);
1019         do_div(sample_period, count);
1020         tstamp = data->timestamp - (count - 1) * sample_period;
1021
1022         if (samples && count > samples)
1023                 count = samples;
1024
1025         ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
1026         if (ret)
1027                 return ret;
1028
1029         /*
1030          * Ideally we want the IIO core to handle the demux when running in fifo
1031          * mode but not when running in triggered buffer mode. Unfortunately
1032          * this does not seem to be possible, so stick with driver demux for
1033          * now.
1034          */
1035         for (i = 0; i < count; i++) {
1036                 int j, bit;
1037
1038                 j = 0;
1039                 for_each_set_bit(bit, indio_dev->active_scan_mask,
1040                                  indio_dev->masklength)
1041                         memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit],
1042                                sizeof(data->scan.channels[0]));
1043
1044                 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
1045                                                    tstamp);
1046
1047                 tstamp += sample_period;
1048         }
1049
1050         return count;
1051 }
1052
1053 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
1054 {
1055         struct bmc150_accel_data *data = iio_priv(indio_dev);
1056         int ret;
1057
1058         mutex_lock(&data->mutex);
1059         ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
1060         mutex_unlock(&data->mutex);
1061
1062         return ret;
1063 }
1064
1065 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
1066                 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
1067
1068 static struct attribute *bmc150_accel_attributes[] = {
1069         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1070         NULL,
1071 };
1072
1073 static const struct attribute_group bmc150_accel_attrs_group = {
1074         .attrs = bmc150_accel_attributes,
1075 };
1076
1077 static const struct iio_event_spec bmc150_accel_event = {
1078                 .type = IIO_EV_TYPE_ROC,
1079                 .dir = IIO_EV_DIR_EITHER,
1080                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
1081                                  BIT(IIO_EV_INFO_ENABLE) |
1082                                  BIT(IIO_EV_INFO_PERIOD)
1083 };
1084
1085 #define BMC150_ACCEL_CHANNEL(_axis, bits) {                             \
1086         .type = IIO_ACCEL,                                              \
1087         .modified = 1,                                                  \
1088         .channel2 = IIO_MOD_##_axis,                                    \
1089         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),                   \
1090         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |          \
1091                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),           \
1092         .scan_index = AXIS_##_axis,                                     \
1093         .scan_type = {                                                  \
1094                 .sign = 's',                                            \
1095                 .realbits = (bits),                                     \
1096                 .storagebits = 16,                                      \
1097                 .shift = 16 - (bits),                                   \
1098                 .endianness = IIO_LE,                                   \
1099         },                                                              \
1100         .ext_info = bmc150_accel_ext_info,                              \
1101         .event_spec = &bmc150_accel_event,                              \
1102         .num_event_specs = 1                                            \
1103 }
1104
1105 #define BMC150_ACCEL_CHANNELS(bits) {                                   \
1106         {                                                               \
1107                 .type = IIO_TEMP,                                       \
1108                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
1109                                       BIT(IIO_CHAN_INFO_SCALE) |        \
1110                                       BIT(IIO_CHAN_INFO_OFFSET),        \
1111                 .scan_index = -1,                                       \
1112         },                                                              \
1113         BMC150_ACCEL_CHANNEL(X, bits),                                  \
1114         BMC150_ACCEL_CHANNEL(Y, bits),                                  \
1115         BMC150_ACCEL_CHANNEL(Z, bits),                                  \
1116         IIO_CHAN_SOFT_TIMESTAMP(3),                                     \
1117 }
1118
1119 static const struct iio_chan_spec bma222e_accel_channels[] =
1120         BMC150_ACCEL_CHANNELS(8);
1121 static const struct iio_chan_spec bma250e_accel_channels[] =
1122         BMC150_ACCEL_CHANNELS(10);
1123 static const struct iio_chan_spec bmc150_accel_channels[] =
1124         BMC150_ACCEL_CHANNELS(12);
1125 static const struct iio_chan_spec bma280_accel_channels[] =
1126         BMC150_ACCEL_CHANNELS(14);
1127
1128 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1129         [bmc150] = {
1130                 .name = "BMC150A",
1131                 .chip_id = 0xFA,
1132                 .channels = bmc150_accel_channels,
1133                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1134                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1135                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1136                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1137                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1138         },
1139         [bmi055] = {
1140                 .name = "BMI055A",
1141                 .chip_id = 0xFA,
1142                 .channels = bmc150_accel_channels,
1143                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1144                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1145                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1146                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1147                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1148         },
1149         [bma255] = {
1150                 .name = "BMA0255",
1151                 .chip_id = 0xFA,
1152                 .channels = bmc150_accel_channels,
1153                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1154                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1155                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1156                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1157                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1158         },
1159         [bma250e] = {
1160                 .name = "BMA250E",
1161                 .chip_id = 0xF9,
1162                 .channels = bma250e_accel_channels,
1163                 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1164                 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1165                                  {76590, BMC150_ACCEL_DEF_RANGE_4G},
1166                                  {153277, BMC150_ACCEL_DEF_RANGE_8G},
1167                                  {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1168         },
1169         [bma222] = {
1170                 .name = "BMA222",
1171                 .chip_id = 0x03,
1172                 .channels = bma222e_accel_channels,
1173                 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1174                 /*
1175                  * The datasheet page 17 says:
1176                  * 15.6, 31.3, 62.5 and 125 mg per LSB.
1177                  */
1178                 .scale_table = { {156000, BMC150_ACCEL_DEF_RANGE_2G},
1179                                  {313000, BMC150_ACCEL_DEF_RANGE_4G},
1180                                  {625000, BMC150_ACCEL_DEF_RANGE_8G},
1181                                  {1250000, BMC150_ACCEL_DEF_RANGE_16G} },
1182         },
1183         [bma222e] = {
1184                 .name = "BMA222E",
1185                 .chip_id = 0xF8,
1186                 .channels = bma222e_accel_channels,
1187                 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1188                 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1189                                  {306457, BMC150_ACCEL_DEF_RANGE_4G},
1190                                  {612915, BMC150_ACCEL_DEF_RANGE_8G},
1191                                  {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1192         },
1193         [bma280] = {
1194                 .name = "BMA0280",
1195                 .chip_id = 0xFB,
1196                 .channels = bma280_accel_channels,
1197                 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1198                 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1199                                  {4785, BMC150_ACCEL_DEF_RANGE_4G},
1200                                  {9581, BMC150_ACCEL_DEF_RANGE_8G},
1201                                  {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1202         },
1203 };
1204
1205 static const struct iio_info bmc150_accel_info = {
1206         .attrs                  = &bmc150_accel_attrs_group,
1207         .read_raw               = bmc150_accel_read_raw,
1208         .write_raw              = bmc150_accel_write_raw,
1209         .read_event_value       = bmc150_accel_read_event,
1210         .write_event_value      = bmc150_accel_write_event,
1211         .write_event_config     = bmc150_accel_write_event_config,
1212         .read_event_config      = bmc150_accel_read_event_config,
1213 };
1214
1215 static const struct iio_info bmc150_accel_info_fifo = {
1216         .attrs                  = &bmc150_accel_attrs_group,
1217         .read_raw               = bmc150_accel_read_raw,
1218         .write_raw              = bmc150_accel_write_raw,
1219         .read_event_value       = bmc150_accel_read_event,
1220         .write_event_value      = bmc150_accel_write_event,
1221         .write_event_config     = bmc150_accel_write_event_config,
1222         .read_event_config      = bmc150_accel_read_event_config,
1223         .validate_trigger       = bmc150_accel_validate_trigger,
1224         .hwfifo_set_watermark   = bmc150_accel_set_watermark,
1225         .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1226 };
1227
1228 static const unsigned long bmc150_accel_scan_masks[] = {
1229                                         BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
1230                                         0};
1231
1232 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1233 {
1234         struct iio_poll_func *pf = p;
1235         struct iio_dev *indio_dev = pf->indio_dev;
1236         struct bmc150_accel_data *data = iio_priv(indio_dev);
1237         int ret;
1238
1239         mutex_lock(&data->mutex);
1240         ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L,
1241                                data->buffer, AXIS_MAX * 2);
1242         mutex_unlock(&data->mutex);
1243         if (ret < 0)
1244                 goto err_read;
1245
1246         iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1247                                            pf->timestamp);
1248 err_read:
1249         iio_trigger_notify_done(indio_dev->trig);
1250
1251         return IRQ_HANDLED;
1252 }
1253
1254 static void bmc150_accel_trig_reen(struct iio_trigger *trig)
1255 {
1256         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1257         struct bmc150_accel_data *data = t->data;
1258         struct device *dev = regmap_get_device(data->regmap);
1259         int ret;
1260
1261         /* new data interrupts don't need ack */
1262         if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1263                 return;
1264
1265         mutex_lock(&data->mutex);
1266         /* clear any latched interrupt */
1267         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1268                            BMC150_ACCEL_INT_MODE_LATCH_INT |
1269                            BMC150_ACCEL_INT_MODE_LATCH_RESET);
1270         mutex_unlock(&data->mutex);
1271         if (ret < 0)
1272                 dev_err(dev, "Error writing reg_int_rst_latch\n");
1273 }
1274
1275 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1276                                           bool state)
1277 {
1278         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1279         struct bmc150_accel_data *data = t->data;
1280         int ret;
1281
1282         mutex_lock(&data->mutex);
1283
1284         if (t->enabled == state) {
1285                 mutex_unlock(&data->mutex);
1286                 return 0;
1287         }
1288
1289         if (t->setup) {
1290                 ret = t->setup(t, state);
1291                 if (ret < 0) {
1292                         mutex_unlock(&data->mutex);
1293                         return ret;
1294                 }
1295         }
1296
1297         ret = bmc150_accel_set_interrupt(data, t->intr, state);
1298         if (ret < 0) {
1299                 mutex_unlock(&data->mutex);
1300                 return ret;
1301         }
1302
1303         t->enabled = state;
1304
1305         mutex_unlock(&data->mutex);
1306
1307         return ret;
1308 }
1309
1310 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1311         .set_trigger_state = bmc150_accel_trigger_set_state,
1312         .reenable = bmc150_accel_trig_reen,
1313 };
1314
1315 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1316 {
1317         struct bmc150_accel_data *data = iio_priv(indio_dev);
1318         struct device *dev = regmap_get_device(data->regmap);
1319         int dir;
1320         int ret;
1321         unsigned int val;
1322
1323         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1324         if (ret < 0) {
1325                 dev_err(dev, "Error reading reg_int_status_2\n");
1326                 return ret;
1327         }
1328
1329         if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1330                 dir = IIO_EV_DIR_FALLING;
1331         else
1332                 dir = IIO_EV_DIR_RISING;
1333
1334         if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1335                 iio_push_event(indio_dev,
1336                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1337                                                   0,
1338                                                   IIO_MOD_X,
1339                                                   IIO_EV_TYPE_ROC,
1340                                                   dir),
1341                                data->timestamp);
1342
1343         if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1344                 iio_push_event(indio_dev,
1345                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1346                                                   0,
1347                                                   IIO_MOD_Y,
1348                                                   IIO_EV_TYPE_ROC,
1349                                                   dir),
1350                                data->timestamp);
1351
1352         if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1353                 iio_push_event(indio_dev,
1354                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1355                                                   0,
1356                                                   IIO_MOD_Z,
1357                                                   IIO_EV_TYPE_ROC,
1358                                                   dir),
1359                                data->timestamp);
1360
1361         return ret;
1362 }
1363
1364 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1365 {
1366         struct iio_dev *indio_dev = private;
1367         struct bmc150_accel_data *data = iio_priv(indio_dev);
1368         struct device *dev = regmap_get_device(data->regmap);
1369         bool ack = false;
1370         int ret;
1371
1372         mutex_lock(&data->mutex);
1373
1374         if (data->fifo_mode) {
1375                 ret = __bmc150_accel_fifo_flush(indio_dev,
1376                                                 BMC150_ACCEL_FIFO_LENGTH, true);
1377                 if (ret > 0)
1378                         ack = true;
1379         }
1380
1381         if (data->ev_enable_state) {
1382                 ret = bmc150_accel_handle_roc_event(indio_dev);
1383                 if (ret > 0)
1384                         ack = true;
1385         }
1386
1387         if (ack) {
1388                 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1389                                    BMC150_ACCEL_INT_MODE_LATCH_INT |
1390                                    BMC150_ACCEL_INT_MODE_LATCH_RESET);
1391                 if (ret)
1392                         dev_err(dev, "Error writing reg_int_rst_latch\n");
1393
1394                 ret = IRQ_HANDLED;
1395         } else {
1396                 ret = IRQ_NONE;
1397         }
1398
1399         mutex_unlock(&data->mutex);
1400
1401         return ret;
1402 }
1403
1404 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1405 {
1406         struct iio_dev *indio_dev = private;
1407         struct bmc150_accel_data *data = iio_priv(indio_dev);
1408         bool ack = false;
1409         int i;
1410
1411         data->old_timestamp = data->timestamp;
1412         data->timestamp = iio_get_time_ns(indio_dev);
1413
1414         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1415                 if (data->triggers[i].enabled) {
1416                         iio_trigger_poll(data->triggers[i].indio_trig);
1417                         ack = true;
1418                         break;
1419                 }
1420         }
1421
1422         if (data->ev_enable_state || data->fifo_mode)
1423                 return IRQ_WAKE_THREAD;
1424
1425         if (ack)
1426                 return IRQ_HANDLED;
1427
1428         return IRQ_NONE;
1429 }
1430
1431 static const struct {
1432         int intr;
1433         const char *name;
1434         int (*setup)(struct bmc150_accel_trigger *t, bool state);
1435 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1436         {
1437                 .intr = 0,
1438                 .name = "%s-dev%d",
1439         },
1440         {
1441                 .intr = 1,
1442                 .name = "%s-any-motion-dev%d",
1443                 .setup = bmc150_accel_any_motion_setup,
1444         },
1445 };
1446
1447 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1448                                              int from)
1449 {
1450         int i;
1451
1452         for (i = from; i >= 0; i--) {
1453                 if (data->triggers[i].indio_trig) {
1454                         iio_trigger_unregister(data->triggers[i].indio_trig);
1455                         data->triggers[i].indio_trig = NULL;
1456                 }
1457         }
1458 }
1459
1460 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1461                                        struct bmc150_accel_data *data)
1462 {
1463         struct device *dev = regmap_get_device(data->regmap);
1464         int i, ret;
1465
1466         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1467                 struct bmc150_accel_trigger *t = &data->triggers[i];
1468
1469                 t->indio_trig = devm_iio_trigger_alloc(dev,
1470                                                        bmc150_accel_triggers[i].name,
1471                                                        indio_dev->name,
1472                                                        iio_device_id(indio_dev));
1473                 if (!t->indio_trig) {
1474                         ret = -ENOMEM;
1475                         break;
1476                 }
1477
1478                 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1479                 t->intr = bmc150_accel_triggers[i].intr;
1480                 t->data = data;
1481                 t->setup = bmc150_accel_triggers[i].setup;
1482                 iio_trigger_set_drvdata(t->indio_trig, t);
1483
1484                 ret = iio_trigger_register(t->indio_trig);
1485                 if (ret)
1486                         break;
1487         }
1488
1489         if (ret)
1490                 bmc150_accel_unregister_triggers(data, i - 1);
1491
1492         return ret;
1493 }
1494
1495 #define BMC150_ACCEL_FIFO_MODE_STREAM          0x80
1496 #define BMC150_ACCEL_FIFO_MODE_FIFO            0x40
1497 #define BMC150_ACCEL_FIFO_MODE_BYPASS          0x00
1498
1499 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1500 {
1501         struct device *dev = regmap_get_device(data->regmap);
1502         u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1503         int ret;
1504
1505         ret = regmap_write(data->regmap, reg, data->fifo_mode);
1506         if (ret < 0) {
1507                 dev_err(dev, "Error writing reg_fifo_config1\n");
1508                 return ret;
1509         }
1510
1511         if (!data->fifo_mode)
1512                 return 0;
1513
1514         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1515                            data->watermark);
1516         if (ret < 0)
1517                 dev_err(dev, "Error writing reg_fifo_config0\n");
1518
1519         return ret;
1520 }
1521
1522 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1523 {
1524         struct bmc150_accel_data *data = iio_priv(indio_dev);
1525
1526         return bmc150_accel_set_power_state(data, true);
1527 }
1528
1529 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1530 {
1531         struct bmc150_accel_data *data = iio_priv(indio_dev);
1532         int ret = 0;
1533
1534         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1535                 return 0;
1536
1537         mutex_lock(&data->mutex);
1538
1539         if (!data->watermark)
1540                 goto out;
1541
1542         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1543                                          true);
1544         if (ret)
1545                 goto out;
1546
1547         data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1548
1549         ret = bmc150_accel_fifo_set_mode(data);
1550         if (ret) {
1551                 data->fifo_mode = 0;
1552                 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1553                                            false);
1554         }
1555
1556 out:
1557         mutex_unlock(&data->mutex);
1558
1559         return ret;
1560 }
1561
1562 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1563 {
1564         struct bmc150_accel_data *data = iio_priv(indio_dev);
1565
1566         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1567                 return 0;
1568
1569         mutex_lock(&data->mutex);
1570
1571         if (!data->fifo_mode)
1572                 goto out;
1573
1574         bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1575         __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1576         data->fifo_mode = 0;
1577         bmc150_accel_fifo_set_mode(data);
1578
1579 out:
1580         mutex_unlock(&data->mutex);
1581
1582         return 0;
1583 }
1584
1585 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1586 {
1587         struct bmc150_accel_data *data = iio_priv(indio_dev);
1588
1589         return bmc150_accel_set_power_state(data, false);
1590 }
1591
1592 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1593         .preenable = bmc150_accel_buffer_preenable,
1594         .postenable = bmc150_accel_buffer_postenable,
1595         .predisable = bmc150_accel_buffer_predisable,
1596         .postdisable = bmc150_accel_buffer_postdisable,
1597 };
1598
1599 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1600 {
1601         struct device *dev = regmap_get_device(data->regmap);
1602         int ret, i;
1603         unsigned int val;
1604
1605         /*
1606          * Reset chip to get it in a known good state. A delay of 1.8ms after
1607          * reset is required according to the data sheets of supported chips.
1608          */
1609         regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1610                      BMC150_ACCEL_RESET_VAL);
1611         usleep_range(1800, 2500);
1612
1613         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1614         if (ret < 0) {
1615                 dev_err(dev, "Error: Reading chip id\n");
1616                 return ret;
1617         }
1618
1619         dev_dbg(dev, "Chip Id %x\n", val);
1620         for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1621                 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1622                         data->chip_info = &bmc150_accel_chip_info_tbl[i];
1623                         break;
1624                 }
1625         }
1626
1627         if (!data->chip_info) {
1628                 dev_err(dev, "Invalid chip %x\n", val);
1629                 return -ENODEV;
1630         }
1631
1632         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1633         if (ret < 0)
1634                 return ret;
1635
1636         /* Set Bandwidth */
1637         ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1638         if (ret < 0)
1639                 return ret;
1640
1641         /* Set Default Range */
1642         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1643                            BMC150_ACCEL_DEF_RANGE_4G);
1644         if (ret < 0) {
1645                 dev_err(dev, "Error writing reg_pmu_range\n");
1646                 return ret;
1647         }
1648
1649         data->range = BMC150_ACCEL_DEF_RANGE_4G;
1650
1651         /* Set default slope duration and thresholds */
1652         data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1653         data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1654         ret = bmc150_accel_update_slope(data);
1655         if (ret < 0)
1656                 return ret;
1657
1658         /* Set default as latched interrupts */
1659         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1660                            BMC150_ACCEL_INT_MODE_LATCH_INT |
1661                            BMC150_ACCEL_INT_MODE_LATCH_RESET);
1662         if (ret < 0) {
1663                 dev_err(dev, "Error writing reg_int_rst_latch\n");
1664                 return ret;
1665         }
1666
1667         return 0;
1668 }
1669
1670 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1671                             const char *name, bool block_supported)
1672 {
1673         const struct attribute **fifo_attrs;
1674         struct bmc150_accel_data *data;
1675         struct iio_dev *indio_dev;
1676         int ret;
1677
1678         indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1679         if (!indio_dev)
1680                 return -ENOMEM;
1681
1682         data = iio_priv(indio_dev);
1683         dev_set_drvdata(dev, indio_dev);
1684
1685         data->regmap = regmap;
1686
1687         if (!bmc150_apply_acpi_orientation(dev, &data->orientation)) {
1688                 ret = iio_read_mount_matrix(dev, &data->orientation);
1689                 if (ret)
1690                         return ret;
1691         }
1692
1693         /*
1694          * VDD   is the analog and digital domain voltage supply
1695          * VDDIO is the digital I/O voltage supply
1696          */
1697         data->regulators[0].supply = "vdd";
1698         data->regulators[1].supply = "vddio";
1699         ret = devm_regulator_bulk_get(dev,
1700                                       ARRAY_SIZE(data->regulators),
1701                                       data->regulators);
1702         if (ret)
1703                 return dev_err_probe(dev, ret, "failed to get regulators\n");
1704
1705         ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators),
1706                                     data->regulators);
1707         if (ret) {
1708                 dev_err(dev, "failed to enable regulators: %d\n", ret);
1709                 return ret;
1710         }
1711         /*
1712          * 2ms or 3ms power-on time according to datasheets, let's better
1713          * be safe than sorry and set this delay to 5ms.
1714          */
1715         msleep(5);
1716
1717         ret = bmc150_accel_chip_init(data);
1718         if (ret < 0)
1719                 goto err_disable_regulators;
1720
1721         mutex_init(&data->mutex);
1722
1723         indio_dev->channels = data->chip_info->channels;
1724         indio_dev->num_channels = data->chip_info->num_channels;
1725         indio_dev->name = name ? name : data->chip_info->name;
1726         indio_dev->available_scan_masks = bmc150_accel_scan_masks;
1727         indio_dev->modes = INDIO_DIRECT_MODE;
1728         indio_dev->info = &bmc150_accel_info;
1729
1730         if (block_supported) {
1731                 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1732                 indio_dev->info = &bmc150_accel_info_fifo;
1733                 fifo_attrs = bmc150_accel_fifo_attributes;
1734         } else {
1735                 fifo_attrs = NULL;
1736         }
1737
1738         ret = iio_triggered_buffer_setup_ext(indio_dev,
1739                                              &iio_pollfunc_store_time,
1740                                              bmc150_accel_trigger_handler,
1741                                              &bmc150_accel_buffer_ops,
1742                                              fifo_attrs);
1743         if (ret < 0) {
1744                 dev_err(dev, "Failed: iio triggered buffer setup\n");
1745                 goto err_disable_regulators;
1746         }
1747
1748         if (irq > 0) {
1749                 ret = devm_request_threaded_irq(dev, irq,
1750                                                 bmc150_accel_irq_handler,
1751                                                 bmc150_accel_irq_thread_handler,
1752                                                 IRQF_TRIGGER_RISING,
1753                                                 BMC150_ACCEL_IRQ_NAME,
1754                                                 indio_dev);
1755                 if (ret)
1756                         goto err_buffer_cleanup;
1757
1758                 /*
1759                  * Set latched mode interrupt. While certain interrupts are
1760                  * non-latched regardless of this settings (e.g. new data) we
1761                  * want to use latch mode when we can to prevent interrupt
1762                  * flooding.
1763                  */
1764                 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1765                                    BMC150_ACCEL_INT_MODE_LATCH_RESET);
1766                 if (ret < 0) {
1767                         dev_err(dev, "Error writing reg_int_rst_latch\n");
1768                         goto err_buffer_cleanup;
1769                 }
1770
1771                 bmc150_accel_interrupts_setup(indio_dev, data);
1772
1773                 ret = bmc150_accel_triggers_setup(indio_dev, data);
1774                 if (ret)
1775                         goto err_buffer_cleanup;
1776         }
1777
1778         ret = pm_runtime_set_active(dev);
1779         if (ret)
1780                 goto err_trigger_unregister;
1781
1782         pm_runtime_enable(dev);
1783         pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1784         pm_runtime_use_autosuspend(dev);
1785
1786         ret = iio_device_register(indio_dev);
1787         if (ret < 0) {
1788                 dev_err(dev, "Unable to register iio device\n");
1789                 goto err_trigger_unregister;
1790         }
1791
1792         return 0;
1793
1794 err_trigger_unregister:
1795         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1796 err_buffer_cleanup:
1797         iio_triggered_buffer_cleanup(indio_dev);
1798 err_disable_regulators:
1799         regulator_bulk_disable(ARRAY_SIZE(data->regulators),
1800                                data->regulators);
1801
1802         return ret;
1803 }
1804 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1805
1806 struct i2c_client *bmc150_get_second_device(struct i2c_client *client)
1807 {
1808         struct bmc150_accel_data *data = iio_priv(i2c_get_clientdata(client));
1809
1810         return data->second_device;
1811 }
1812 EXPORT_SYMBOL_GPL(bmc150_get_second_device);
1813
1814 void bmc150_set_second_device(struct i2c_client *client)
1815 {
1816         struct bmc150_accel_data *data = iio_priv(i2c_get_clientdata(client));
1817
1818         data->second_device = client;
1819 }
1820 EXPORT_SYMBOL_GPL(bmc150_set_second_device);
1821
1822 int bmc150_accel_core_remove(struct device *dev)
1823 {
1824         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1825         struct bmc150_accel_data *data = iio_priv(indio_dev);
1826
1827         iio_device_unregister(indio_dev);
1828
1829         pm_runtime_disable(dev);
1830         pm_runtime_set_suspended(dev);
1831
1832         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1833
1834         iio_triggered_buffer_cleanup(indio_dev);
1835
1836         mutex_lock(&data->mutex);
1837         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1838         mutex_unlock(&data->mutex);
1839
1840         regulator_bulk_disable(ARRAY_SIZE(data->regulators),
1841                                data->regulators);
1842
1843         return 0;
1844 }
1845 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1846
1847 #ifdef CONFIG_PM_SLEEP
1848 static int bmc150_accel_suspend(struct device *dev)
1849 {
1850         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1851         struct bmc150_accel_data *data = iio_priv(indio_dev);
1852
1853         mutex_lock(&data->mutex);
1854         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1855         mutex_unlock(&data->mutex);
1856
1857         return 0;
1858 }
1859
1860 static int bmc150_accel_resume(struct device *dev)
1861 {
1862         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1863         struct bmc150_accel_data *data = iio_priv(indio_dev);
1864
1865         mutex_lock(&data->mutex);
1866         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1867         bmc150_accel_fifo_set_mode(data);
1868         mutex_unlock(&data->mutex);
1869
1870         return 0;
1871 }
1872 #endif
1873
1874 #ifdef CONFIG_PM
1875 static int bmc150_accel_runtime_suspend(struct device *dev)
1876 {
1877         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1878         struct bmc150_accel_data *data = iio_priv(indio_dev);
1879         int ret;
1880
1881         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1882         if (ret < 0)
1883                 return -EAGAIN;
1884
1885         return 0;
1886 }
1887
1888 static int bmc150_accel_runtime_resume(struct device *dev)
1889 {
1890         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1891         struct bmc150_accel_data *data = iio_priv(indio_dev);
1892         int ret;
1893         int sleep_val;
1894
1895         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1896         if (ret < 0)
1897                 return ret;
1898         ret = bmc150_accel_fifo_set_mode(data);
1899         if (ret < 0)
1900                 return ret;
1901
1902         sleep_val = bmc150_accel_get_startup_times(data);
1903         if (sleep_val < 20)
1904                 usleep_range(sleep_val * 1000, 20000);
1905         else
1906                 msleep_interruptible(sleep_val);
1907
1908         return 0;
1909 }
1910 #endif
1911
1912 const struct dev_pm_ops bmc150_accel_pm_ops = {
1913         SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1914         SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1915                            bmc150_accel_runtime_resume, NULL)
1916 };
1917 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1918
1919 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1920 MODULE_LICENSE("GPL v2");
1921 MODULE_DESCRIPTION("BMC150 accelerometer driver");