drivers/iio/accel/bmc150-accel-core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
   4  *  - BMC150
   5  *  - BMI055
   6  *  - BMA255
   7  *  - BMA250E
   8  *  - BMA222
   9  *  - BMA222E
  10  *  - BMA280
  11  *
  12  * Copyright (c) 2014, Intel Corporation.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/i2c.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/delay.h>
  19 #include <linux/slab.h>
  20 #include <linux/acpi.h>
  21 #include <linux/pm.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/iio/iio.h>
  24 #include <linux/iio/sysfs.h>
  25 #include <linux/iio/buffer.h>
  26 #include <linux/iio/events.h>
  27 #include <linux/iio/trigger.h>
  28 #include <linux/iio/trigger_consumer.h>
  29 #include <linux/iio/triggered_buffer.h>
  30 #include <linux/regmap.h>
  31 #include <linux/regulator/consumer.h>
  32
  33 #include "bmc150-accel.h"
  34
  35 #define BMC150_ACCEL_DRV_NAME                   "bmc150_accel"
  36 #define BMC150_ACCEL_IRQ_NAME                   "bmc150_accel_event"
  37
  38 #define BMC150_ACCEL_REG_CHIP_ID                0x00
  39
  40 #define BMC150_ACCEL_REG_INT_STATUS_2           0x0B
  41 #define BMC150_ACCEL_ANY_MOTION_MASK            0x07
  42 #define BMC150_ACCEL_ANY_MOTION_BIT_X           BIT(0)
  43 #define BMC150_ACCEL_ANY_MOTION_BIT_Y           BIT(1)
  44 #define BMC150_ACCEL_ANY_MOTION_BIT_Z           BIT(2)
  45 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN        BIT(3)
  46
  47 #define BMC150_ACCEL_REG_PMU_LPW                0x11
  48 #define BMC150_ACCEL_PMU_MODE_MASK              0xE0
  49 #define BMC150_ACCEL_PMU_MODE_SHIFT             5
  50 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK     0x17
  51 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT    1
  52
  53 #define BMC150_ACCEL_REG_PMU_RANGE              0x0F
  54
  55 #define BMC150_ACCEL_DEF_RANGE_2G               0x03
  56 #define BMC150_ACCEL_DEF_RANGE_4G               0x05
  57 #define BMC150_ACCEL_DEF_RANGE_8G               0x08
  58 #define BMC150_ACCEL_DEF_RANGE_16G              0x0C
  59
  60 /* Default BW: 125Hz */
  61 #define BMC150_ACCEL_REG_PMU_BW         0x10
  62 #define BMC150_ACCEL_DEF_BW                     125
  63
  64 #define BMC150_ACCEL_REG_RESET                  0x14
  65 #define BMC150_ACCEL_RESET_VAL                  0xB6
  66
  67 #define BMC150_ACCEL_REG_INT_MAP_0              0x19
  68 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE        BIT(2)
  69
  70 #define BMC150_ACCEL_REG_INT_MAP_1              0x1A
  71 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA         BIT(0)
  72 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM          BIT(1)
  73 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL        BIT(2)
  74
  75 #define BMC150_ACCEL_REG_INT_RST_LATCH          0x21
  76 #define BMC150_ACCEL_INT_MODE_LATCH_RESET       0x80
  77 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
  78 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT     0x00
  79
  80 #define BMC150_ACCEL_REG_INT_EN_0               0x16
  81 #define BMC150_ACCEL_INT_EN_BIT_SLP_X           BIT(0)
  82 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y           BIT(1)
  83 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z           BIT(2)
  84
  85 #define BMC150_ACCEL_REG_INT_EN_1               0x17
  86 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN         BIT(4)
  87 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN        BIT(5)
  88 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN          BIT(6)
  89
  90 #define BMC150_ACCEL_REG_INT_OUT_CTRL           0x20
  91 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL      BIT(0)
  92
  93 #define BMC150_ACCEL_REG_INT_5                  0x27
  94 #define BMC150_ACCEL_SLOPE_DUR_MASK             0x03
  95
  96 #define BMC150_ACCEL_REG_INT_6                  0x28
  97 #define BMC150_ACCEL_SLOPE_THRES_MASK           0xFF
  98
  99 /* Slope duration in terms of number of samples */
 100 #define BMC150_ACCEL_DEF_SLOPE_DURATION         1
 101 /* in terms of multiples of g's/LSB, based on range */
 102 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD        1
 103
 104 #define BMC150_ACCEL_REG_XOUT_L         0x02
 105
 106 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS        100
 107
 108 /* Sleep Duration values */
 109 #define BMC150_ACCEL_SLEEP_500_MICRO            0x05
 110 #define BMC150_ACCEL_SLEEP_1_MS         0x06
 111 #define BMC150_ACCEL_SLEEP_2_MS         0x07
 112 #define BMC150_ACCEL_SLEEP_4_MS         0x08
 113 #define BMC150_ACCEL_SLEEP_6_MS         0x09
 114 #define BMC150_ACCEL_SLEEP_10_MS                0x0A
 115 #define BMC150_ACCEL_SLEEP_25_MS                0x0B
 116 #define BMC150_ACCEL_SLEEP_50_MS                0x0C
 117 #define BMC150_ACCEL_SLEEP_100_MS               0x0D
 118 #define BMC150_ACCEL_SLEEP_500_MS               0x0E
 119 #define BMC150_ACCEL_SLEEP_1_SEC                0x0F
 120
 121 #define BMC150_ACCEL_REG_TEMP                   0x08
 122 #define BMC150_ACCEL_TEMP_CENTER_VAL            23
 123
 124 #define BMC150_ACCEL_AXIS_TO_REG(axis)  (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
 125 #define BMC150_AUTO_SUSPEND_DELAY_MS            2000
 126
 127 #define BMC150_ACCEL_REG_FIFO_STATUS            0x0E
 128 #define BMC150_ACCEL_REG_FIFO_CONFIG0           0x30
 129 #define BMC150_ACCEL_REG_FIFO_CONFIG1           0x3E
 130 #define BMC150_ACCEL_REG_FIFO_DATA              0x3F
 131 #define BMC150_ACCEL_FIFO_LENGTH                32
 132
 133 enum bmc150_accel_axis {
 134         AXIS_X,
 135         AXIS_Y,
 136         AXIS_Z,
 137         AXIS_MAX,
 138 };
 139
 140 enum bmc150_power_modes {
 141         BMC150_ACCEL_SLEEP_MODE_NORMAL,
 142         BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
 143         BMC150_ACCEL_SLEEP_MODE_LPM,
 144         BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
 145 };
 146
 147 struct bmc150_scale_info {
 148         int scale;
 149         u8 reg_range;
 150 };
 151
 152 struct bmc150_accel_chip_info {
 153         const char *name;
 154         u8 chip_id;
 155         const struct iio_chan_spec *channels;
 156         int num_channels;
 157         const struct bmc150_scale_info scale_table[4];
 158 };
 159
 160 struct bmc150_accel_interrupt {
 161         const struct bmc150_accel_interrupt_info *info;
 162         atomic_t users;
 163 };
 164
 165 struct bmc150_accel_trigger {
 166         struct bmc150_accel_data *data;
 167         struct iio_trigger *indio_trig;
 168         int (*setup)(struct bmc150_accel_trigger *t, bool state);
 169         int intr;
 170         bool enabled;
 171 };
 172
 173 enum bmc150_accel_interrupt_id {
 174         BMC150_ACCEL_INT_DATA_READY,
 175         BMC150_ACCEL_INT_ANY_MOTION,
 176         BMC150_ACCEL_INT_WATERMARK,
 177         BMC150_ACCEL_INTERRUPTS,
 178 };
 179
 180 enum bmc150_accel_trigger_id {
 181         BMC150_ACCEL_TRIGGER_DATA_READY,
 182         BMC150_ACCEL_TRIGGER_ANY_MOTION,
 183         BMC150_ACCEL_TRIGGERS,
 184 };
 185
 186 struct bmc150_accel_data {
 187         struct regmap *regmap;
 188         struct regulator_bulk_data regulators[2];
 189         int irq;
 190         struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
 191         struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
 192         struct mutex mutex;
 193         u8 fifo_mode, watermark;
 194         s16 buffer[8];
 195         /*
 196          * Ensure there is sufficient space and correct alignment for
 197          * the timestamp if enabled
 198          */
 199         struct {
 200                 __le16 channels[3];
 201                 s64 ts __aligned(8);
 202         } scan;
 203         u8 bw_bits;
 204         u32 slope_dur;
 205         u32 slope_thres;
 206         u32 range;
 207         int ev_enable_state;
 208         int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
 209         const struct bmc150_accel_chip_info *chip_info;
 210         struct iio_mount_matrix orientation;
 211 };
 212
 213 static const struct {
 214         int val;
 215         int val2;
 216         u8 bw_bits;
 217 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
 218                                      {31, 260000, 0x09},
 219                                      {62, 500000, 0x0A},
 220                                      {125, 0, 0x0B},
 221                                      {250, 0, 0x0C},
 222                                      {500, 0, 0x0D},
 223                                      {1000, 0, 0x0E},
 224                                      {2000, 0, 0x0F} };
 225
 226 static const struct {
 227         int bw_bits;
 228         int msec;
 229 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
 230                                      {0x09, 32},
 231                                      {0x0A, 16},
 232                                      {0x0B, 8},
 233                                      {0x0C, 4},
 234                                      {0x0D, 2},
 235                                      {0x0E, 1},
 236                                      {0x0F, 1} };
 237
 238 static const struct {
 239         int sleep_dur;
 240         u8 reg_value;
 241 } bmc150_accel_sleep_value_table[] = { {0, 0},
 242                                        {500, BMC150_ACCEL_SLEEP_500_MICRO},
 243                                        {1000, BMC150_ACCEL_SLEEP_1_MS},
 244                                        {2000, BMC150_ACCEL_SLEEP_2_MS},
 245                                        {4000, BMC150_ACCEL_SLEEP_4_MS},
 246                                        {6000, BMC150_ACCEL_SLEEP_6_MS},
 247                                        {10000, BMC150_ACCEL_SLEEP_10_MS},
 248                                        {25000, BMC150_ACCEL_SLEEP_25_MS},
 249                                        {50000, BMC150_ACCEL_SLEEP_50_MS},
 250                                        {100000, BMC150_ACCEL_SLEEP_100_MS},
 251                                        {500000, BMC150_ACCEL_SLEEP_500_MS},
 252                                        {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
 253
 254 const struct regmap_config bmc150_regmap_conf = {
 255         .reg_bits = 8,
 256         .val_bits = 8,
 257         .max_register = 0x3f,
 258 };
 259 EXPORT_SYMBOL_GPL(bmc150_regmap_conf);
 260
 261 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
 262                                  enum bmc150_power_modes mode,
 263                                  int dur_us)
 264 {
 265         struct device *dev = regmap_get_device(data->regmap);
 266         int i;
 267         int ret;
 268         u8 lpw_bits;
 269         int dur_val = -1;
 270
 271         if (dur_us > 0) {
 272                 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
 273                                                                          ++i) {
 274                         if (bmc150_accel_sleep_value_table[i].sleep_dur ==
 275                                                                         dur_us)
 276                                 dur_val =
 277                                 bmc150_accel_sleep_value_table[i].reg_value;
 278                 }
 279         } else {
 280                 dur_val = 0;
 281         }
 282
 283         if (dur_val < 0)
 284                 return -EINVAL;
 285
 286         lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
 287         lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
 288
 289         dev_dbg(dev, "Set Mode bits %x\n", lpw_bits);
 290
 291         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
 292         if (ret < 0) {
 293                 dev_err(dev, "Error writing reg_pmu_lpw\n");
 294                 return ret;
 295         }
 296
 297         return 0;
 298 }
 299
 300 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
 301                                int val2)
 302 {
 303         int i;
 304         int ret;
 305
 306         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 307                 if (bmc150_accel_samp_freq_table[i].val == val &&
 308                     bmc150_accel_samp_freq_table[i].val2 == val2) {
 309                         ret = regmap_write(data->regmap,
 310                                 BMC150_ACCEL_REG_PMU_BW,
 311                                 bmc150_accel_samp_freq_table[i].bw_bits);
 312                         if (ret < 0)
 313                                 return ret;
 314
 315                         data->bw_bits =
 316                                 bmc150_accel_samp_freq_table[i].bw_bits;
 317                         return 0;
 318                 }
 319         }
 320
 321         return -EINVAL;
 322 }
 323
 324 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
 325 {
 326         struct device *dev = regmap_get_device(data->regmap);
 327         int ret;
 328
 329         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
 330                                         data->slope_thres);
 331         if (ret < 0) {
 332                 dev_err(dev, "Error writing reg_int_6\n");
 333                 return ret;
 334         }
 335
 336         ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
 337                                  BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
 338         if (ret < 0) {
 339                 dev_err(dev, "Error updating reg_int_5\n");
 340                 return ret;
 341         }
 342
 343         dev_dbg(dev, "%x %x\n", data->slope_thres, data->slope_dur);
 344
 345         return ret;
 346 }
 347
 348 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
 349                                          bool state)
 350 {
 351         if (state)
 352                 return bmc150_accel_update_slope(t->data);
 353
 354         return 0;
 355 }
 356
 357 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
 358                                int *val2)
 359 {
 360         int i;
 361
 362         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 363                 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
 364                         *val = bmc150_accel_samp_freq_table[i].val;
 365                         *val2 = bmc150_accel_samp_freq_table[i].val2;
 366                         return IIO_VAL_INT_PLUS_MICRO;
 367                 }
 368         }
 369
 370         return -EINVAL;
 371 }
 372
 373 #ifdef CONFIG_PM
 374 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
 375 {
 376         int i;
 377
 378         for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
 379                 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
 380                         return bmc150_accel_sample_upd_time[i].msec;
 381         }
 382
 383         return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
 384 }
 385
 386 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 387 {
 388         struct device *dev = regmap_get_device(data->regmap);
 389         int ret;
 390
 391         if (on) {
 392                 ret = pm_runtime_get_sync(dev);
 393         } else {
 394                 pm_runtime_mark_last_busy(dev);
 395                 ret = pm_runtime_put_autosuspend(dev);
 396         }
 397
 398         if (ret < 0) {
 399                 dev_err(dev,
 400                         "Failed: %s for %d\n", __func__, on);
 401                 if (on)
 402                         pm_runtime_put_noidle(dev);
 403
 404                 return ret;
 405         }
 406
 407         return 0;
 408 }
 409 #else
 410 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 411 {
 412         return 0;
 413 }
 414 #endif
 415
 416 static const struct bmc150_accel_interrupt_info {
 417         u8 map_reg;
 418         u8 map_bitmask;
 419         u8 en_reg;
 420         u8 en_bitmask;
 421 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
 422         { /* data ready interrupt */
 423                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 424                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
 425                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 426                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
 427         },
 428         {  /* motion interrupt */
 429                 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
 430                 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
 431                 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
 432                 .en_bitmask =  BMC150_ACCEL_INT_EN_BIT_SLP_X |
 433                         BMC150_ACCEL_INT_EN_BIT_SLP_Y |
 434                         BMC150_ACCEL_INT_EN_BIT_SLP_Z
 435         },
 436         { /* fifo watermark interrupt */
 437                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 438                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
 439                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 440                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
 441         },
 442 };
 443
 444 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
 445                                           struct bmc150_accel_data *data)
 446 {
 447         int i;
 448
 449         for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
 450                 data->interrupts[i].info = &bmc150_accel_interrupts[i];
 451 }
 452
 453 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
 454                                       bool state)
 455 {
 456         struct device *dev = regmap_get_device(data->regmap);
 457         struct bmc150_accel_interrupt *intr = &data->interrupts[i];
 458         const struct bmc150_accel_interrupt_info *info = intr->info;
 459         int ret;
 460
 461         if (state) {
 462                 if (atomic_inc_return(&intr->users) > 1)
 463                         return 0;
 464         } else {
 465                 if (atomic_dec_return(&intr->users) > 0)
 466                         return 0;
 467         }
 468
 469         /*
 470          * We will expect the enable and disable to do operation in reverse
 471          * order. This will happen here anyway, as our resume operation uses
 472          * sync mode runtime pm calls. The suspend operation will be delayed
 473          * by autosuspend delay.
 474          * So the disable operation will still happen in reverse order of
 475          * enable operation. When runtime pm is disabled the mode is always on,
 476          * so sequence doesn't matter.
 477          */
 478         ret = bmc150_accel_set_power_state(data, state);
 479         if (ret < 0)
 480                 return ret;
 481
 482         /* map the interrupt to the appropriate pins */
 483         ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
 484                                  (state ? info->map_bitmask : 0));
 485         if (ret < 0) {
 486                 dev_err(dev, "Error updating reg_int_map\n");
 487                 goto out_fix_power_state;
 488         }
 489
 490         /* enable/disable the interrupt */
 491         ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
 492                                  (state ? info->en_bitmask : 0));
 493         if (ret < 0) {
 494                 dev_err(dev, "Error updating reg_int_en\n");
 495                 goto out_fix_power_state;
 496         }
 497
 498         return 0;
 499
 500 out_fix_power_state:
 501         bmc150_accel_set_power_state(data, false);
 502         return ret;
 503 }
 504
 505 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
 506 {
 507         struct device *dev = regmap_get_device(data->regmap);
 508         int ret, i;
 509
 510         for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
 511                 if (data->chip_info->scale_table[i].scale == val) {
 512                         ret = regmap_write(data->regmap,
 513                                      BMC150_ACCEL_REG_PMU_RANGE,
 514                                      data->chip_info->scale_table[i].reg_range);
 515                         if (ret < 0) {
 516                                 dev_err(dev, "Error writing pmu_range\n");
 517                                 return ret;
 518                         }
 519
 520                         data->range = data->chip_info->scale_table[i].reg_range;
 521                         return 0;
 522                 }
 523         }
 524
 525         return -EINVAL;
 526 }
 527
 528 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
 529 {
 530         struct device *dev = regmap_get_device(data->regmap);
 531         int ret;
 532         unsigned int value;
 533
 534         mutex_lock(&data->mutex);
 535
 536         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
 537         if (ret < 0) {
 538                 dev_err(dev, "Error reading reg_temp\n");
 539                 mutex_unlock(&data->mutex);
 540                 return ret;
 541         }
 542         *val = sign_extend32(value, 7);
 543
 544         mutex_unlock(&data->mutex);
 545
 546         return IIO_VAL_INT;
 547 }
 548
 549 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
 550                                  struct iio_chan_spec const *chan,
 551                                  int *val)
 552 {
 553         struct device *dev = regmap_get_device(data->regmap);
 554         int ret;
 555         int axis = chan->scan_index;
 556         __le16 raw_val;
 557
 558         mutex_lock(&data->mutex);
 559         ret = bmc150_accel_set_power_state(data, true);
 560         if (ret < 0) {
 561                 mutex_unlock(&data->mutex);
 562                 return ret;
 563         }
 564
 565         ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
 566                                &raw_val, sizeof(raw_val));
 567         if (ret < 0) {
 568                 dev_err(dev, "Error reading axis %d\n", axis);
 569                 bmc150_accel_set_power_state(data, false);
 570                 mutex_unlock(&data->mutex);
 571                 return ret;
 572         }
 573         *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
 574                              chan->scan_type.realbits - 1);
 575         ret = bmc150_accel_set_power_state(data, false);
 576         mutex_unlock(&data->mutex);
 577         if (ret < 0)
 578                 return ret;
 579
 580         return IIO_VAL_INT;
 581 }
 582
 583 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
 584                                  struct iio_chan_spec const *chan,
 585                                  int *val, int *val2, long mask)
 586 {
 587         struct bmc150_accel_data *data = iio_priv(indio_dev);
 588         int ret;
 589
 590         switch (mask) {
 591         case IIO_CHAN_INFO_RAW:
 592                 switch (chan->type) {
 593                 case IIO_TEMP:
 594                         return bmc150_accel_get_temp(data, val);
 595                 case IIO_ACCEL:
 596                         if (iio_buffer_enabled(indio_dev))
 597                                 return -EBUSY;
 598                         else
 599                                 return bmc150_accel_get_axis(data, chan, val);
 600                 default:
 601                         return -EINVAL;
 602                 }
 603         case IIO_CHAN_INFO_OFFSET:
 604                 if (chan->type == IIO_TEMP) {
 605                         *val = BMC150_ACCEL_TEMP_CENTER_VAL;
 606                         return IIO_VAL_INT;
 607                 } else {
 608                         return -EINVAL;
 609                 }
 610         case IIO_CHAN_INFO_SCALE:
 611                 *val = 0;
 612                 switch (chan->type) {
 613                 case IIO_TEMP:
 614                         *val2 = 500000;
 615                         return IIO_VAL_INT_PLUS_MICRO;
 616                 case IIO_ACCEL:
 617                 {
 618                         int i;
 619                         const struct bmc150_scale_info *si;
 620                         int st_size = ARRAY_SIZE(data->chip_info->scale_table);
 621
 622                         for (i = 0; i < st_size; ++i) {
 623                                 si = &data->chip_info->scale_table[i];
 624                                 if (si->reg_range == data->range) {
 625                                         *val2 = si->scale;
 626                                         return IIO_VAL_INT_PLUS_MICRO;
 627                                 }
 628                         }
 629                         return -EINVAL;
 630                 }
 631                 default:
 632                         return -EINVAL;
 633                 }
 634         case IIO_CHAN_INFO_SAMP_FREQ:
 635                 mutex_lock(&data->mutex);
 636                 ret = bmc150_accel_get_bw(data, val, val2);
 637                 mutex_unlock(&data->mutex);
 638                 return ret;
 639         default:
 640                 return -EINVAL;
 641         }
 642 }
 643
 644 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
 645                                   struct iio_chan_spec const *chan,
 646                                   int val, int val2, long mask)
 647 {
 648         struct bmc150_accel_data *data = iio_priv(indio_dev);
 649         int ret;
 650
 651         switch (mask) {
 652         case IIO_CHAN_INFO_SAMP_FREQ:
 653                 mutex_lock(&data->mutex);
 654                 ret = bmc150_accel_set_bw(data, val, val2);
 655                 mutex_unlock(&data->mutex);
 656                 break;
 657         case IIO_CHAN_INFO_SCALE:
 658                 if (val)
 659                         return -EINVAL;
 660
 661                 mutex_lock(&data->mutex);
 662                 ret = bmc150_accel_set_scale(data, val2);
 663                 mutex_unlock(&data->mutex);
 664                 return ret;
 665         default:
 666                 ret = -EINVAL;
 667         }
 668
 669         return ret;
 670 }
 671
 672 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
 673                                    const struct iio_chan_spec *chan,
 674                                    enum iio_event_type type,
 675                                    enum iio_event_direction dir,
 676                                    enum iio_event_info info,
 677                                    int *val, int *val2)
 678 {
 679         struct bmc150_accel_data *data = iio_priv(indio_dev);
 680
 681         *val2 = 0;
 682         switch (info) {
 683         case IIO_EV_INFO_VALUE:
 684                 *val = data->slope_thres;
 685                 break;
 686         case IIO_EV_INFO_PERIOD:
 687                 *val = data->slope_dur;
 688                 break;
 689         default:
 690                 return -EINVAL;
 691         }
 692
 693         return IIO_VAL_INT;
 694 }
 695
 696 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
 697                                     const struct iio_chan_spec *chan,
 698                                     enum iio_event_type type,
 699                                     enum iio_event_direction dir,
 700                                     enum iio_event_info info,
 701                                     int val, int val2)
 702 {
 703         struct bmc150_accel_data *data = iio_priv(indio_dev);
 704
 705         if (data->ev_enable_state)
 706                 return -EBUSY;
 707
 708         switch (info) {
 709         case IIO_EV_INFO_VALUE:
 710                 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
 711                 break;
 712         case IIO_EV_INFO_PERIOD:
 713                 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
 714                 break;
 715         default:
 716                 return -EINVAL;
 717         }
 718
 719         return 0;
 720 }
 721
 722 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
 723                                           const struct iio_chan_spec *chan,
 724                                           enum iio_event_type type,
 725                                           enum iio_event_direction dir)
 726 {
 727         struct bmc150_accel_data *data = iio_priv(indio_dev);
 728
 729         return data->ev_enable_state;
 730 }
 731
 732 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
 733                                            const struct iio_chan_spec *chan,
 734                                            enum iio_event_type type,
 735                                            enum iio_event_direction dir,
 736                                            int state)
 737 {
 738         struct bmc150_accel_data *data = iio_priv(indio_dev);
 739         int ret;
 740
 741         if (state == data->ev_enable_state)
 742                 return 0;
 743
 744         mutex_lock(&data->mutex);
 745
 746         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
 747                                          state);
 748         if (ret < 0) {
 749                 mutex_unlock(&data->mutex);
 750                 return ret;
 751         }
 752
 753         data->ev_enable_state = state;
 754         mutex_unlock(&data->mutex);
 755
 756         return 0;
 757 }
 758
 759 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
 760                                          struct iio_trigger *trig)
 761 {
 762         struct bmc150_accel_data *data = iio_priv(indio_dev);
 763         int i;
 764
 765         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
 766                 if (data->triggers[i].indio_trig == trig)
 767                         return 0;
 768         }
 769
 770         return -EINVAL;
 771 }
 772
 773 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
 774                                                struct device_attribute *attr,
 775                                                char *buf)
 776 {
 777         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 778         struct bmc150_accel_data *data = iio_priv(indio_dev);
 779         int wm;
 780
 781         mutex_lock(&data->mutex);
 782         wm = data->watermark;
 783         mutex_unlock(&data->mutex);
 784
 785         return sprintf(buf, "%d\n", wm);
 786 }
 787
 788 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
 789                                            struct device_attribute *attr,
 790                                            char *buf)
 791 {
 792         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 793         struct bmc150_accel_data *data = iio_priv(indio_dev);
 794         bool state;
 795
 796         mutex_lock(&data->mutex);
 797         state = data->fifo_mode;
 798         mutex_unlock(&data->mutex);
 799
 800         return sprintf(buf, "%d\n", state);
 801 }
 802
 803 static const struct iio_mount_matrix *
 804 bmc150_accel_get_mount_matrix(const struct iio_dev *indio_dev,
 805                                 const struct iio_chan_spec *chan)
 806 {
 807         struct bmc150_accel_data *data = iio_priv(indio_dev);
 808
 809         return &data->orientation;
 810 }
 811
 812 static const struct iio_chan_spec_ext_info bmc150_accel_ext_info[] = {
 813         IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmc150_accel_get_mount_matrix),
 814         { }
 815 };
 816
 817 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
 818 static IIO_CONST_ATTR(hwfifo_watermark_max,
 819                       __stringify(BMC150_ACCEL_FIFO_LENGTH));
 820 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
 821                        bmc150_accel_get_fifo_state, NULL, 0);
 822 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
 823                        bmc150_accel_get_fifo_watermark, NULL, 0);
 824
 825 static const struct attribute *bmc150_accel_fifo_attributes[] = {
 826         &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
 827         &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
 828         &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
 829         &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
 830         NULL,
 831 };
 832
 833 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
 834 {
 835         struct bmc150_accel_data *data = iio_priv(indio_dev);
 836
 837         if (val > BMC150_ACCEL_FIFO_LENGTH)
 838                 val = BMC150_ACCEL_FIFO_LENGTH;
 839
 840         mutex_lock(&data->mutex);
 841         data->watermark = val;
 842         mutex_unlock(&data->mutex);
 843
 844         return 0;
 845 }
 846
 847 /*
 848  * We must read at least one full frame in one burst, otherwise the rest of the
 849  * frame data is discarded.
 850  */
 851 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
 852                                       char *buffer, int samples)
 853 {
 854         struct device *dev = regmap_get_device(data->regmap);
 855         int sample_length = 3 * 2;
 856         int ret;
 857         int total_length = samples * sample_length;
 858
 859         ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
 860                               buffer, total_length);
 861         if (ret)
 862                 dev_err(dev,
 863                         "Error transferring data from fifo: %d\n", ret);
 864
 865         return ret;
 866 }
 867
 868 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
 869                                      unsigned samples, bool irq)
 870 {
 871         struct bmc150_accel_data *data = iio_priv(indio_dev);
 872         struct device *dev = regmap_get_device(data->regmap);
 873         int ret, i;
 874         u8 count;
 875         u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
 876         int64_t tstamp;
 877         uint64_t sample_period;
 878         unsigned int val;
 879
 880         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
 881         if (ret < 0) {
 882                 dev_err(dev, "Error reading reg_fifo_status\n");
 883                 return ret;
 884         }
 885
 886         count = val & 0x7F;
 887
 888         if (!count)
 889                 return 0;
 890
 891         /*
 892          * If we getting called from IRQ handler we know the stored timestamp is
 893          * fairly accurate for the last stored sample. Otherwise, if we are
 894          * called as a result of a read operation from userspace and hence
 895          * before the watermark interrupt was triggered, take a timestamp
 896          * now. We can fall anywhere in between two samples so the error in this
 897          * case is at most one sample period.
 898          */
 899         if (!irq) {
 900                 data->old_timestamp = data->timestamp;
 901                 data->timestamp = iio_get_time_ns(indio_dev);
 902         }
 903
 904         /*
 905          * Approximate timestamps for each of the sample based on the sampling
 906          * frequency, timestamp for last sample and number of samples.
 907          *
 908          * Note that we can't use the current bandwidth settings to compute the
 909          * sample period because the sample rate varies with the device
 910          * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
 911          * small variation adds when we store a large number of samples and
 912          * creates significant jitter between the last and first samples in
 913          * different batches (e.g. 32ms vs 21ms).
 914          *
 915          * To avoid this issue we compute the actual sample period ourselves
 916          * based on the timestamp delta between the last two flush operations.
 917          */
 918         sample_period = (data->timestamp - data->old_timestamp);
 919         do_div(sample_period, count);
 920         tstamp = data->timestamp - (count - 1) * sample_period;
 921
 922         if (samples && count > samples)
 923                 count = samples;
 924
 925         ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
 926         if (ret)
 927                 return ret;
 928
 929         /*
 930          * Ideally we want the IIO core to handle the demux when running in fifo
 931          * mode but not when running in triggered buffer mode. Unfortunately
 932          * this does not seem to be possible, so stick with driver demux for
 933          * now.
 934          */
 935         for (i = 0; i < count; i++) {
 936                 int j, bit;
 937
 938                 j = 0;
 939                 for_each_set_bit(bit, indio_dev->active_scan_mask,
 940                                  indio_dev->masklength)
 941                         memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit],
 942                                sizeof(data->scan.channels[0]));
 943
 944                 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
 945                                                    tstamp);
 946
 947                 tstamp += sample_period;
 948         }
 949
 950         return count;
 951 }
 952
 953 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
 954 {
 955         struct bmc150_accel_data *data = iio_priv(indio_dev);
 956         int ret;
 957
 958         mutex_lock(&data->mutex);
 959         ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
 960         mutex_unlock(&data->mutex);
 961
 962         return ret;
 963 }
 964
 965 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
 966                 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
 967
 968 static struct attribute *bmc150_accel_attributes[] = {
 969         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 970         NULL,
 971 };
 972
 973 static const struct attribute_group bmc150_accel_attrs_group = {
 974         .attrs = bmc150_accel_attributes,
 975 };
 976
 977 static const struct iio_event_spec bmc150_accel_event = {
 978                 .type = IIO_EV_TYPE_ROC,
 979                 .dir = IIO_EV_DIR_EITHER,
 980                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
 981                                  BIT(IIO_EV_INFO_ENABLE) |
 982                                  BIT(IIO_EV_INFO_PERIOD)
 983 };
 984
 985 #define BMC150_ACCEL_CHANNEL(_axis, bits) {                             \
 986         .type = IIO_ACCEL,                                              \
 987         .modified = 1,                                                  \
 988         .channel2 = IIO_MOD_##_axis,                                    \
 989         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),                   \
 990         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |          \
 991                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),           \
 992         .scan_index = AXIS_##_axis,                                     \
 993         .scan_type = {                                                  \
 994                 .sign = 's',                                            \
 995                 .realbits = (bits),                                     \
 996                 .storagebits = 16,                                      \
 997                 .shift = 16 - (bits),                                   \
 998                 .endianness = IIO_LE,                                   \
 999         },                                                              \
1000         .ext_info = bmc150_accel_ext_info,                              \
1001         .event_spec = &bmc150_accel_event,                              \
1002         .num_event_specs = 1                                            \
1003 }
1004
1005 #define BMC150_ACCEL_CHANNELS(bits) {                                   \
1006         {                                                               \
1007                 .type = IIO_TEMP,                                       \
1008                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
1009                                       BIT(IIO_CHAN_INFO_SCALE) |        \
1010                                       BIT(IIO_CHAN_INFO_OFFSET),        \
1011                 .scan_index = -1,                                       \
1012         },                                                              \
1013         BMC150_ACCEL_CHANNEL(X, bits),                                  \
1014         BMC150_ACCEL_CHANNEL(Y, bits),                                  \
1015         BMC150_ACCEL_CHANNEL(Z, bits),                                  \
1016         IIO_CHAN_SOFT_TIMESTAMP(3),                                     \
1017 }
1018
1019 static const struct iio_chan_spec bma222e_accel_channels[] =
1020         BMC150_ACCEL_CHANNELS(8);
1021 static const struct iio_chan_spec bma250e_accel_channels[] =
1022         BMC150_ACCEL_CHANNELS(10);
1023 static const struct iio_chan_spec bmc150_accel_channels[] =
1024         BMC150_ACCEL_CHANNELS(12);
1025 static const struct iio_chan_spec bma280_accel_channels[] =
1026         BMC150_ACCEL_CHANNELS(14);
1027
1028 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1029         [bmc150] = {
1030                 .name = "BMC150A",
1031                 .chip_id = 0xFA,
1032                 .channels = bmc150_accel_channels,
1033                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1034                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1035                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1036                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1037                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1038         },
1039         [bmi055] = {
1040                 .name = "BMI055A",
1041                 .chip_id = 0xFA,
1042                 .channels = bmc150_accel_channels,
1043                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1044                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1045                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1046                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1047                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1048         },
1049         [bma255] = {
1050                 .name = "BMA0255",
1051                 .chip_id = 0xFA,
1052                 .channels = bmc150_accel_channels,
1053                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1054                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1055                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1056                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1057                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1058         },
1059         [bma250e] = {
1060                 .name = "BMA250E",
1061                 .chip_id = 0xF9,
1062                 .channels = bma250e_accel_channels,
1063                 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1064                 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1065                                  {76590, BMC150_ACCEL_DEF_RANGE_4G},
1066                                  {153277, BMC150_ACCEL_DEF_RANGE_8G},
1067                                  {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1068         },
1069         [bma222] = {
1070                 .name = "BMA222",
1071                 .chip_id = 0x03,
1072                 .channels = bma222e_accel_channels,
1073                 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1074                 /*
1075                  * The datasheet page 17 says:
1076                  * 15.6, 31.3, 62.5 and 125 mg per LSB.
1077                  */
1078                 .scale_table = { {156000, BMC150_ACCEL_DEF_RANGE_2G},
1079                                  {313000, BMC150_ACCEL_DEF_RANGE_4G},
1080                                  {625000, BMC150_ACCEL_DEF_RANGE_8G},
1081                                  {1250000, BMC150_ACCEL_DEF_RANGE_16G} },
1082         },
1083         [bma222e] = {
1084                 .name = "BMA222E",
1085                 .chip_id = 0xF8,
1086                 .channels = bma222e_accel_channels,
1087                 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1088                 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1089                                  {306457, BMC150_ACCEL_DEF_RANGE_4G},
1090                                  {612915, BMC150_ACCEL_DEF_RANGE_8G},
1091                                  {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1092         },
1093         [bma280] = {
1094                 .name = "BMA0280",
1095                 .chip_id = 0xFB,
1096                 .channels = bma280_accel_channels,
1097                 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1098                 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1099                                  {4785, BMC150_ACCEL_DEF_RANGE_4G},
1100                                  {9581, BMC150_ACCEL_DEF_RANGE_8G},
1101                                  {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1102         },
1103 };
1104
1105 static const struct iio_info bmc150_accel_info = {
1106         .attrs                  = &bmc150_accel_attrs_group,
1107         .read_raw               = bmc150_accel_read_raw,
1108         .write_raw              = bmc150_accel_write_raw,
1109         .read_event_value       = bmc150_accel_read_event,
1110         .write_event_value      = bmc150_accel_write_event,
1111         .write_event_config     = bmc150_accel_write_event_config,
1112         .read_event_config      = bmc150_accel_read_event_config,
1113 };
1114
1115 static const struct iio_info bmc150_accel_info_fifo = {
1116         .attrs                  = &bmc150_accel_attrs_group,
1117         .read_raw               = bmc150_accel_read_raw,
1118         .write_raw              = bmc150_accel_write_raw,
1119         .read_event_value       = bmc150_accel_read_event,
1120         .write_event_value      = bmc150_accel_write_event,
1121         .write_event_config     = bmc150_accel_write_event_config,
1122         .read_event_config      = bmc150_accel_read_event_config,
1123         .validate_trigger       = bmc150_accel_validate_trigger,
1124         .hwfifo_set_watermark   = bmc150_accel_set_watermark,
1125         .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1126 };
1127
1128 static const unsigned long bmc150_accel_scan_masks[] = {
1129                                         BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
1130                                         0};
1131
1132 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1133 {
1134         struct iio_poll_func *pf = p;
1135         struct iio_dev *indio_dev = pf->indio_dev;
1136         struct bmc150_accel_data *data = iio_priv(indio_dev);
1137         int ret;
1138
1139         mutex_lock(&data->mutex);
1140         ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L,
1141                                data->buffer, AXIS_MAX * 2);
1142         mutex_unlock(&data->mutex);
1143         if (ret < 0)
1144                 goto err_read;
1145
1146         iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1147                                            pf->timestamp);
1148 err_read:
1149         iio_trigger_notify_done(indio_dev->trig);
1150
1151         return IRQ_HANDLED;
1152 }
1153
1154 static void bmc150_accel_trig_reen(struct iio_trigger *trig)
1155 {
1156         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1157         struct bmc150_accel_data *data = t->data;
1158         struct device *dev = regmap_get_device(data->regmap);
1159         int ret;
1160
1161         /* new data interrupts don't need ack */
1162         if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1163                 return;
1164
1165         mutex_lock(&data->mutex);
1166         /* clear any latched interrupt */
1167         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1168                            BMC150_ACCEL_INT_MODE_LATCH_INT |
1169                            BMC150_ACCEL_INT_MODE_LATCH_RESET);
1170         mutex_unlock(&data->mutex);
1171         if (ret < 0)
1172                 dev_err(dev, "Error writing reg_int_rst_latch\n");
1173 }
1174
1175 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1176                                           bool state)
1177 {
1178         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1179         struct bmc150_accel_data *data = t->data;
1180         int ret;
1181
1182         mutex_lock(&data->mutex);
1183
1184         if (t->enabled == state) {
1185                 mutex_unlock(&data->mutex);
1186                 return 0;
1187         }
1188
1189         if (t->setup) {
1190                 ret = t->setup(t, state);
1191                 if (ret < 0) {
1192                         mutex_unlock(&data->mutex);
1193                         return ret;
1194                 }
1195         }
1196
1197         ret = bmc150_accel_set_interrupt(data, t->intr, state);
1198         if (ret < 0) {
1199                 mutex_unlock(&data->mutex);
1200                 return ret;
1201         }
1202
1203         t->enabled = state;
1204
1205         mutex_unlock(&data->mutex);
1206
1207         return ret;
1208 }
1209
1210 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1211         .set_trigger_state = bmc150_accel_trigger_set_state,
1212         .reenable = bmc150_accel_trig_reen,
1213 };
1214
1215 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1216 {
1217         struct bmc150_accel_data *data = iio_priv(indio_dev);
1218         struct device *dev = regmap_get_device(data->regmap);
1219         int dir;
1220         int ret;
1221         unsigned int val;
1222
1223         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1224         if (ret < 0) {
1225                 dev_err(dev, "Error reading reg_int_status_2\n");
1226                 return ret;
1227         }
1228
1229         if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1230                 dir = IIO_EV_DIR_FALLING;
1231         else
1232                 dir = IIO_EV_DIR_RISING;
1233
1234         if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1235                 iio_push_event(indio_dev,
1236                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1237                                                   0,
1238                                                   IIO_MOD_X,
1239                                                   IIO_EV_TYPE_ROC,
1240                                                   dir),
1241                                data->timestamp);
1242
1243         if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1244                 iio_push_event(indio_dev,
1245                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1246                                                   0,
1247                                                   IIO_MOD_Y,
1248                                                   IIO_EV_TYPE_ROC,
1249                                                   dir),
1250                                data->timestamp);
1251
1252         if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1253                 iio_push_event(indio_dev,
1254                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1255                                                   0,
1256                                                   IIO_MOD_Z,
1257                                                   IIO_EV_TYPE_ROC,
1258                                                   dir),
1259                                data->timestamp);
1260
1261         return ret;
1262 }
1263
1264 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1265 {
1266         struct iio_dev *indio_dev = private;
1267         struct bmc150_accel_data *data = iio_priv(indio_dev);
1268         struct device *dev = regmap_get_device(data->regmap);
1269         bool ack = false;
1270         int ret;
1271
1272         mutex_lock(&data->mutex);
1273
1274         if (data->fifo_mode) {
1275                 ret = __bmc150_accel_fifo_flush(indio_dev,
1276                                                 BMC150_ACCEL_FIFO_LENGTH, true);
1277                 if (ret > 0)
1278                         ack = true;
1279         }
1280
1281         if (data->ev_enable_state) {
1282                 ret = bmc150_accel_handle_roc_event(indio_dev);
1283                 if (ret > 0)
1284                         ack = true;
1285         }
1286
1287         if (ack) {
1288                 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1289                                    BMC150_ACCEL_INT_MODE_LATCH_INT |
1290                                    BMC150_ACCEL_INT_MODE_LATCH_RESET);
1291                 if (ret)
1292                         dev_err(dev, "Error writing reg_int_rst_latch\n");
1293
1294                 ret = IRQ_HANDLED;
1295         } else {
1296                 ret = IRQ_NONE;
1297         }
1298
1299         mutex_unlock(&data->mutex);
1300
1301         return ret;
1302 }
1303
1304 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1305 {
1306         struct iio_dev *indio_dev = private;
1307         struct bmc150_accel_data *data = iio_priv(indio_dev);
1308         bool ack = false;
1309         int i;
1310
1311         data->old_timestamp = data->timestamp;
1312         data->timestamp = iio_get_time_ns(indio_dev);
1313
1314         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1315                 if (data->triggers[i].enabled) {
1316                         iio_trigger_poll(data->triggers[i].indio_trig);
1317                         ack = true;
1318                         break;
1319                 }
1320         }
1321
1322         if (data->ev_enable_state || data->fifo_mode)
1323                 return IRQ_WAKE_THREAD;
1324
1325         if (ack)
1326                 return IRQ_HANDLED;
1327
1328         return IRQ_NONE;
1329 }
1330
1331 static const struct {
1332         int intr;
1333         const char *name;
1334         int (*setup)(struct bmc150_accel_trigger *t, bool state);
1335 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1336         {
1337                 .intr = 0,
1338                 .name = "%s-dev%d",
1339         },
1340         {
1341                 .intr = 1,
1342                 .name = "%s-any-motion-dev%d",
1343                 .setup = bmc150_accel_any_motion_setup,
1344         },
1345 };
1346
1347 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1348                                              int from)
1349 {
1350         int i;
1351
1352         for (i = from; i >= 0; i--) {
1353                 if (data->triggers[i].indio_trig) {
1354                         iio_trigger_unregister(data->triggers[i].indio_trig);
1355                         data->triggers[i].indio_trig = NULL;
1356                 }
1357         }
1358 }
1359
1360 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1361                                        struct bmc150_accel_data *data)
1362 {
1363         struct device *dev = regmap_get_device(data->regmap);
1364         int i, ret;
1365
1366         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1367                 struct bmc150_accel_trigger *t = &data->triggers[i];
1368
1369                 t->indio_trig = devm_iio_trigger_alloc(dev,
1370                                         bmc150_accel_triggers[i].name,
1371                                                        indio_dev->name,
1372                                                        indio_dev->id);
1373                 if (!t->indio_trig) {
1374                         ret = -ENOMEM;
1375                         break;
1376                 }
1377
1378                 t->indio_trig->dev.parent = dev;
1379                 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1380                 t->intr = bmc150_accel_triggers[i].intr;
1381                 t->data = data;
1382                 t->setup = bmc150_accel_triggers[i].setup;
1383                 iio_trigger_set_drvdata(t->indio_trig, t);
1384
1385                 ret = iio_trigger_register(t->indio_trig);
1386                 if (ret)
1387                         break;
1388         }
1389
1390         if (ret)
1391                 bmc150_accel_unregister_triggers(data, i - 1);
1392
1393         return ret;
1394 }
1395
1396 #define BMC150_ACCEL_FIFO_MODE_STREAM          0x80
1397 #define BMC150_ACCEL_FIFO_MODE_FIFO            0x40
1398 #define BMC150_ACCEL_FIFO_MODE_BYPASS          0x00
1399
1400 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1401 {
1402         struct device *dev = regmap_get_device(data->regmap);
1403         u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1404         int ret;
1405
1406         ret = regmap_write(data->regmap, reg, data->fifo_mode);
1407         if (ret < 0) {
1408                 dev_err(dev, "Error writing reg_fifo_config1\n");
1409                 return ret;
1410         }
1411
1412         if (!data->fifo_mode)
1413                 return 0;
1414
1415         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1416                            data->watermark);
1417         if (ret < 0)
1418                 dev_err(dev, "Error writing reg_fifo_config0\n");
1419
1420         return ret;
1421 }
1422
1423 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1424 {
1425         struct bmc150_accel_data *data = iio_priv(indio_dev);
1426
1427         return bmc150_accel_set_power_state(data, true);
1428 }
1429
1430 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1431 {
1432         struct bmc150_accel_data *data = iio_priv(indio_dev);
1433         int ret = 0;
1434
1435         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1436                 return 0;
1437
1438         mutex_lock(&data->mutex);
1439
1440         if (!data->watermark)
1441                 goto out;
1442
1443         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1444                                          true);
1445         if (ret)
1446                 goto out;
1447
1448         data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1449
1450         ret = bmc150_accel_fifo_set_mode(data);
1451         if (ret) {
1452                 data->fifo_mode = 0;
1453                 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1454                                            false);
1455         }
1456
1457 out:
1458         mutex_unlock(&data->mutex);
1459
1460         return ret;
1461 }
1462
1463 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1464 {
1465         struct bmc150_accel_data *data = iio_priv(indio_dev);
1466
1467         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1468                 return 0;
1469
1470         mutex_lock(&data->mutex);
1471
1472         if (!data->fifo_mode)
1473                 goto out;
1474
1475         bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1476         __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1477         data->fifo_mode = 0;
1478         bmc150_accel_fifo_set_mode(data);
1479
1480 out:
1481         mutex_unlock(&data->mutex);
1482
1483         return 0;
1484 }
1485
1486 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1487 {
1488         struct bmc150_accel_data *data = iio_priv(indio_dev);
1489
1490         return bmc150_accel_set_power_state(data, false);
1491 }
1492
1493 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1494         .preenable = bmc150_accel_buffer_preenable,
1495         .postenable = bmc150_accel_buffer_postenable,
1496         .predisable = bmc150_accel_buffer_predisable,
1497         .postdisable = bmc150_accel_buffer_postdisable,
1498 };
1499
1500 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1501 {
1502         struct device *dev = regmap_get_device(data->regmap);
1503         int ret, i;
1504         unsigned int val;
1505
1506         /*
1507          * Reset chip to get it in a known good state. A delay of 1.8ms after
1508          * reset is required according to the data sheets of supported chips.
1509          */
1510         regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1511                      BMC150_ACCEL_RESET_VAL);
1512         usleep_range(1800, 2500);
1513
1514         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1515         if (ret < 0) {
1516                 dev_err(dev, "Error: Reading chip id\n");
1517                 return ret;
1518         }
1519
1520         dev_dbg(dev, "Chip Id %x\n", val);
1521         for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1522                 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1523                         data->chip_info = &bmc150_accel_chip_info_tbl[i];
1524                         break;
1525                 }
1526         }
1527
1528         if (!data->chip_info) {
1529                 dev_err(dev, "Invalid chip %x\n", val);
1530                 return -ENODEV;
1531         }
1532
1533         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1534         if (ret < 0)
1535                 return ret;
1536
1537         /* Set Bandwidth */
1538         ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1539         if (ret < 0)
1540                 return ret;
1541
1542         /* Set Default Range */
1543         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1544                            BMC150_ACCEL_DEF_RANGE_4G);
1545         if (ret < 0) {
1546                 dev_err(dev, "Error writing reg_pmu_range\n");
1547                 return ret;
1548         }
1549
1550         data->range = BMC150_ACCEL_DEF_RANGE_4G;
1551
1552         /* Set default slope duration and thresholds */
1553         data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1554         data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1555         ret = bmc150_accel_update_slope(data);
1556         if (ret < 0)
1557                 return ret;
1558
1559         /* Set default as latched interrupts */
1560         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1561                            BMC150_ACCEL_INT_MODE_LATCH_INT |
1562                            BMC150_ACCEL_INT_MODE_LATCH_RESET);
1563         if (ret < 0) {
1564                 dev_err(dev, "Error writing reg_int_rst_latch\n");
1565                 return ret;
1566         }
1567
1568         return 0;
1569 }
1570
1571 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1572                             const char *name, bool block_supported)
1573 {
1574         const struct attribute **fifo_attrs;
1575         struct bmc150_accel_data *data;
1576         struct iio_dev *indio_dev;
1577         int ret;
1578
1579         indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1580         if (!indio_dev)
1581                 return -ENOMEM;
1582
1583         data = iio_priv(indio_dev);
1584         dev_set_drvdata(dev, indio_dev);
1585         data->irq = irq;
1586
1587         data->regmap = regmap;
1588
1589         ret = iio_read_mount_matrix(dev, "mount-matrix",
1590                                      &data->orientation);
1591         if (ret)
1592                 return ret;
1593         /*
1594          * VDD   is the analog and digital domain voltage supply
1595          * VDDIO is the digital I/O voltage supply
1596          */
1597         data->regulators[0].supply = "vdd";
1598         data->regulators[1].supply = "vddio";
1599         ret = devm_regulator_bulk_get(dev,
1600                                       ARRAY_SIZE(data->regulators),
1601                                       data->regulators);
1602         if (ret)
1603                 return dev_err_probe(dev, ret, "failed to get regulators\n");
1604
1605         ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators),
1606                                     data->regulators);
1607         if (ret) {
1608                 dev_err(dev, "failed to enable regulators: %d\n", ret);
1609                 return ret;
1610         }
1611         /*
1612          * 2ms or 3ms power-on time according to datasheets, let's better
1613          * be safe than sorry and set this delay to 5ms.
1614          */
1615         msleep(5);
1616
1617         ret = bmc150_accel_chip_init(data);
1618         if (ret < 0)
1619                 goto err_disable_regulators;
1620
1621         mutex_init(&data->mutex);
1622
1623         indio_dev->channels = data->chip_info->channels;
1624         indio_dev->num_channels = data->chip_info->num_channels;
1625         indio_dev->name = name ? name : data->chip_info->name;
1626         indio_dev->available_scan_masks = bmc150_accel_scan_masks;
1627         indio_dev->modes = INDIO_DIRECT_MODE;
1628         indio_dev->info = &bmc150_accel_info;
1629
1630         if (block_supported) {
1631                 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1632                 indio_dev->info = &bmc150_accel_info_fifo;
1633                 fifo_attrs = bmc150_accel_fifo_attributes;
1634         } else {
1635                 fifo_attrs = NULL;
1636         }
1637
1638         ret = iio_triggered_buffer_setup_ext(indio_dev,
1639                                              &iio_pollfunc_store_time,
1640                                              bmc150_accel_trigger_handler,
1641                                              &bmc150_accel_buffer_ops,
1642                                              fifo_attrs);
1643         if (ret < 0) {
1644                 dev_err(dev, "Failed: iio triggered buffer setup\n");
1645                 goto err_disable_regulators;
1646         }
1647
1648         if (data->irq > 0) {
1649                 ret = devm_request_threaded_irq(
1650                                                 dev, data->irq,
1651                                                 bmc150_accel_irq_handler,
1652                                                 bmc150_accel_irq_thread_handler,
1653                                                 IRQF_TRIGGER_RISING,
1654                                                 BMC150_ACCEL_IRQ_NAME,
1655                                                 indio_dev);
1656                 if (ret)
1657                         goto err_buffer_cleanup;
1658
1659                 /*
1660                  * Set latched mode interrupt. While certain interrupts are
1661                  * non-latched regardless of this settings (e.g. new data) we
1662                  * want to use latch mode when we can to prevent interrupt
1663                  * flooding.
1664                  */
1665                 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1666                                    BMC150_ACCEL_INT_MODE_LATCH_RESET);
1667                 if (ret < 0) {
1668                         dev_err(dev, "Error writing reg_int_rst_latch\n");
1669                         goto err_buffer_cleanup;
1670                 }
1671
1672                 bmc150_accel_interrupts_setup(indio_dev, data);
1673
1674                 ret = bmc150_accel_triggers_setup(indio_dev, data);
1675                 if (ret)
1676                         goto err_buffer_cleanup;
1677         }
1678
1679         ret = pm_runtime_set_active(dev);
1680         if (ret)
1681                 goto err_trigger_unregister;
1682
1683         pm_runtime_enable(dev);
1684         pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1685         pm_runtime_use_autosuspend(dev);
1686
1687         ret = iio_device_register(indio_dev);
1688         if (ret < 0) {
1689                 dev_err(dev, "Unable to register iio device\n");
1690                 goto err_trigger_unregister;
1691         }
1692
1693         return 0;
1694
1695 err_trigger_unregister:
1696         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1697 err_buffer_cleanup:
1698         iio_triggered_buffer_cleanup(indio_dev);
1699 err_disable_regulators:
1700         regulator_bulk_disable(ARRAY_SIZE(data->regulators),
1701                                data->regulators);
1702
1703         return ret;
1704 }
1705 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1706
1707 int bmc150_accel_core_remove(struct device *dev)
1708 {
1709         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1710         struct bmc150_accel_data *data = iio_priv(indio_dev);
1711
1712         iio_device_unregister(indio_dev);
1713
1714         pm_runtime_disable(dev);
1715         pm_runtime_set_suspended(dev);
1716         pm_runtime_put_noidle(dev);
1717
1718         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1719
1720         iio_triggered_buffer_cleanup(indio_dev);
1721
1722         mutex_lock(&data->mutex);
1723         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1724         mutex_unlock(&data->mutex);
1725
1726         regulator_bulk_disable(ARRAY_SIZE(data->regulators),
1727                                data->regulators);
1728
1729         return 0;
1730 }
1731 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1732
1733 #ifdef CONFIG_PM_SLEEP
1734 static int bmc150_accel_suspend(struct device *dev)
1735 {
1736         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1737         struct bmc150_accel_data *data = iio_priv(indio_dev);
1738
1739         mutex_lock(&data->mutex);
1740         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1741         mutex_unlock(&data->mutex);
1742
1743         return 0;
1744 }
1745
1746 static int bmc150_accel_resume(struct device *dev)
1747 {
1748         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1749         struct bmc150_accel_data *data = iio_priv(indio_dev);
1750
1751         mutex_lock(&data->mutex);
1752         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1753         bmc150_accel_fifo_set_mode(data);
1754         mutex_unlock(&data->mutex);
1755
1756         return 0;
1757 }
1758 #endif
1759
1760 #ifdef CONFIG_PM
1761 static int bmc150_accel_runtime_suspend(struct device *dev)
1762 {
1763         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1764         struct bmc150_accel_data *data = iio_priv(indio_dev);
1765         int ret;
1766
1767         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1768         if (ret < 0)
1769                 return -EAGAIN;
1770
1771         return 0;
1772 }
1773
1774 static int bmc150_accel_runtime_resume(struct device *dev)
1775 {
1776         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1777         struct bmc150_accel_data *data = iio_priv(indio_dev);
1778         int ret;
1779         int sleep_val;
1780
1781         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1782         if (ret < 0)
1783                 return ret;
1784         ret = bmc150_accel_fifo_set_mode(data);
1785         if (ret < 0)
1786                 return ret;
1787
1788         sleep_val = bmc150_accel_get_startup_times(data);
1789         if (sleep_val < 20)
1790                 usleep_range(sleep_val * 1000, 20000);
1791         else
1792                 msleep_interruptible(sleep_val);
1793
1794         return 0;
1795 }
1796 #endif
1797
1798 const struct dev_pm_ops bmc150_accel_pm_ops = {
1799         SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1800         SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1801                            bmc150_accel_runtime_resume, NULL)
1802 };
1803 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1804
1805 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1806 MODULE_LICENSE("GPL v2");
1807 MODULE_DESCRIPTION("BMC150 accelerometer driver");