1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_idle.c - native hardware idle loop for modern Intel processors
5 * Copyright (c) 2013 - 2020, Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
11 * intel_idle is a cpuidle driver that loads on specific Intel processors
12 * in lieu of the legacy ACPI processor_idle driver. The intent is to
13 * make Linux more efficient on these processors, as intel_idle knows
14 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
20 * All CPUs have same idle states as boot CPU
22 * Chipset BM_STS (bus master status) bit is a NOP
23 * for preventing entry into deep C-stats
29 * ACPI has a .suspend hack to turn off deep c-statees during suspend
30 * to avoid complications with the lapic timer workaround.
31 * Have not seen issues with suspend, but may need same workaround here.
35 /* un-comment DEBUG to enable pr_debug() statements */
38 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
40 #include <linux/acpi.h>
41 #include <linux/kernel.h>
42 #include <linux/cpuidle.h>
43 #include <linux/tick.h>
44 #include <trace/events/power.h>
45 #include <linux/sched.h>
46 #include <linux/notifier.h>
47 #include <linux/cpu.h>
48 #include <linux/moduleparam.h>
49 #include <asm/cpu_device_id.h>
50 #include <asm/intel-family.h>
51 #include <asm/mwait.h>
54 #define INTEL_IDLE_VERSION "0.5.1"
56 static struct cpuidle_driver intel_idle_driver = {
60 /* intel_idle.max_cstate=0 disables driver */
61 static int max_cstate = CPUIDLE_STATE_MAX - 1;
62 static unsigned int disabled_states_mask;
64 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
66 static unsigned long auto_demotion_disable_flags;
67 static bool disable_promotion_to_c1e;
70 struct cpuidle_state *state_table;
73 * Hardware C-state auto-demotion may not always be optimal.
74 * Indicate which enable bits to clear here.
76 unsigned long auto_demotion_disable_flags;
77 bool byt_auto_demotion_disable_flag;
78 bool disable_promotion_to_c1e;
82 static const struct idle_cpu *icpu __initdata;
83 static struct cpuidle_state *cpuidle_state_table __initdata;
85 static unsigned int mwait_substates __initdata;
88 * Enable this state by default even if the ACPI _CST does not list it.
90 #define CPUIDLE_FLAG_ALWAYS_ENABLE BIT(15)
93 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
94 * the C-state (top nibble) and sub-state (bottom nibble)
95 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
97 * We store the hint at the top of our "flags" for each state.
99 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
100 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
103 * intel_idle - Ask the processor to enter the given idle state.
104 * @dev: cpuidle device of the target CPU.
105 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
106 * @index: Target idle state index.
108 * Use the MWAIT instruction to notify the processor that the CPU represented by
109 * @dev is idle and it can try to enter the idle state corresponding to @index.
111 * If the local APIC timer is not known to be reliable in the target idle state,
112 * enable one-shot tick broadcasting for the target CPU before executing MWAIT.
114 * Optionally call leave_mm() for the target CPU upfront to avoid wakeups due to
115 * flushing user TLBs.
117 * Must be called under local_irq_disable().
119 static __cpuidle int intel_idle(struct cpuidle_device *dev,
120 struct cpuidle_driver *drv, int index)
122 struct cpuidle_state *state = &drv->states[index];
123 unsigned long eax = flg2MWAIT(state->flags);
124 unsigned long ecx = 1; /* break on interrupt flag */
127 if (!static_cpu_has(X86_FEATURE_ARAT)) {
129 * Switch over to one-shot tick broadcast if the target C-state
132 if ((eax >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) {
134 tick_broadcast_enter();
140 mwait_idle_with_hints(eax, ecx);
142 if (!static_cpu_has(X86_FEATURE_ARAT) && tick)
143 tick_broadcast_exit();
149 * intel_idle_s2idle - Ask the processor to enter the given idle state.
150 * @dev: cpuidle device of the target CPU.
151 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
152 * @index: Target idle state index.
154 * Use the MWAIT instruction to notify the processor that the CPU represented by
155 * @dev is idle and it can try to enter the idle state corresponding to @index.
157 * Invoked as a suspend-to-idle callback routine with frozen user space, frozen
158 * scheduler tick and suspended scheduler clock on the target CPU.
160 static __cpuidle int intel_idle_s2idle(struct cpuidle_device *dev,
161 struct cpuidle_driver *drv, int index)
163 unsigned long eax = flg2MWAIT(drv->states[index].flags);
164 unsigned long ecx = 1; /* break on interrupt flag */
166 mwait_idle_with_hints(eax, ecx);
172 * States are indexed by the cstate number,
173 * which is also the index into the MWAIT hint array.
174 * Thus C0 is a dummy.
176 static struct cpuidle_state nehalem_cstates[] __initdata = {
179 .desc = "MWAIT 0x00",
180 .flags = MWAIT2flg(0x00),
182 .target_residency = 6,
183 .enter = &intel_idle,
184 .enter_s2idle = intel_idle_s2idle, },
187 .desc = "MWAIT 0x01",
188 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
190 .target_residency = 20,
191 .enter = &intel_idle,
192 .enter_s2idle = intel_idle_s2idle, },
195 .desc = "MWAIT 0x10",
196 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
198 .target_residency = 80,
199 .enter = &intel_idle,
200 .enter_s2idle = intel_idle_s2idle, },
203 .desc = "MWAIT 0x20",
204 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
206 .target_residency = 800,
207 .enter = &intel_idle,
208 .enter_s2idle = intel_idle_s2idle, },
213 static struct cpuidle_state snb_cstates[] __initdata = {
216 .desc = "MWAIT 0x00",
217 .flags = MWAIT2flg(0x00),
219 .target_residency = 2,
220 .enter = &intel_idle,
221 .enter_s2idle = intel_idle_s2idle, },
224 .desc = "MWAIT 0x01",
225 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
227 .target_residency = 20,
228 .enter = &intel_idle,
229 .enter_s2idle = intel_idle_s2idle, },
232 .desc = "MWAIT 0x10",
233 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
235 .target_residency = 211,
236 .enter = &intel_idle,
237 .enter_s2idle = intel_idle_s2idle, },
240 .desc = "MWAIT 0x20",
241 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
243 .target_residency = 345,
244 .enter = &intel_idle,
245 .enter_s2idle = intel_idle_s2idle, },
248 .desc = "MWAIT 0x30",
249 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
251 .target_residency = 345,
252 .enter = &intel_idle,
253 .enter_s2idle = intel_idle_s2idle, },
258 static struct cpuidle_state byt_cstates[] __initdata = {
261 .desc = "MWAIT 0x00",
262 .flags = MWAIT2flg(0x00),
264 .target_residency = 1,
265 .enter = &intel_idle,
266 .enter_s2idle = intel_idle_s2idle, },
269 .desc = "MWAIT 0x58",
270 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
272 .target_residency = 275,
273 .enter = &intel_idle,
274 .enter_s2idle = intel_idle_s2idle, },
277 .desc = "MWAIT 0x52",
278 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
280 .target_residency = 560,
281 .enter = &intel_idle,
282 .enter_s2idle = intel_idle_s2idle, },
285 .desc = "MWAIT 0x60",
286 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
287 .exit_latency = 1200,
288 .target_residency = 4000,
289 .enter = &intel_idle,
290 .enter_s2idle = intel_idle_s2idle, },
293 .desc = "MWAIT 0x64",
294 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
295 .exit_latency = 10000,
296 .target_residency = 20000,
297 .enter = &intel_idle,
298 .enter_s2idle = intel_idle_s2idle, },
303 static struct cpuidle_state cht_cstates[] __initdata = {
306 .desc = "MWAIT 0x00",
307 .flags = MWAIT2flg(0x00),
309 .target_residency = 1,
310 .enter = &intel_idle,
311 .enter_s2idle = intel_idle_s2idle, },
314 .desc = "MWAIT 0x58",
315 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
317 .target_residency = 275,
318 .enter = &intel_idle,
319 .enter_s2idle = intel_idle_s2idle, },
322 .desc = "MWAIT 0x52",
323 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
325 .target_residency = 560,
326 .enter = &intel_idle,
327 .enter_s2idle = intel_idle_s2idle, },
330 .desc = "MWAIT 0x60",
331 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
332 .exit_latency = 1200,
333 .target_residency = 4000,
334 .enter = &intel_idle,
335 .enter_s2idle = intel_idle_s2idle, },
338 .desc = "MWAIT 0x64",
339 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
340 .exit_latency = 10000,
341 .target_residency = 20000,
342 .enter = &intel_idle,
343 .enter_s2idle = intel_idle_s2idle, },
348 static struct cpuidle_state ivb_cstates[] __initdata = {
351 .desc = "MWAIT 0x00",
352 .flags = MWAIT2flg(0x00),
354 .target_residency = 1,
355 .enter = &intel_idle,
356 .enter_s2idle = intel_idle_s2idle, },
359 .desc = "MWAIT 0x01",
360 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
362 .target_residency = 20,
363 .enter = &intel_idle,
364 .enter_s2idle = intel_idle_s2idle, },
367 .desc = "MWAIT 0x10",
368 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
370 .target_residency = 156,
371 .enter = &intel_idle,
372 .enter_s2idle = intel_idle_s2idle, },
375 .desc = "MWAIT 0x20",
376 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
378 .target_residency = 300,
379 .enter = &intel_idle,
380 .enter_s2idle = intel_idle_s2idle, },
383 .desc = "MWAIT 0x30",
384 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
386 .target_residency = 300,
387 .enter = &intel_idle,
388 .enter_s2idle = intel_idle_s2idle, },
393 static struct cpuidle_state ivt_cstates[] __initdata = {
396 .desc = "MWAIT 0x00",
397 .flags = MWAIT2flg(0x00),
399 .target_residency = 1,
400 .enter = &intel_idle,
401 .enter_s2idle = intel_idle_s2idle, },
404 .desc = "MWAIT 0x01",
405 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
407 .target_residency = 80,
408 .enter = &intel_idle,
409 .enter_s2idle = intel_idle_s2idle, },
412 .desc = "MWAIT 0x10",
413 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
415 .target_residency = 156,
416 .enter = &intel_idle,
417 .enter_s2idle = intel_idle_s2idle, },
420 .desc = "MWAIT 0x20",
421 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
423 .target_residency = 300,
424 .enter = &intel_idle,
425 .enter_s2idle = intel_idle_s2idle, },
430 static struct cpuidle_state ivt_cstates_4s[] __initdata = {
433 .desc = "MWAIT 0x00",
434 .flags = MWAIT2flg(0x00),
436 .target_residency = 1,
437 .enter = &intel_idle,
438 .enter_s2idle = intel_idle_s2idle, },
441 .desc = "MWAIT 0x01",
442 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
444 .target_residency = 250,
445 .enter = &intel_idle,
446 .enter_s2idle = intel_idle_s2idle, },
449 .desc = "MWAIT 0x10",
450 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
452 .target_residency = 300,
453 .enter = &intel_idle,
454 .enter_s2idle = intel_idle_s2idle, },
457 .desc = "MWAIT 0x20",
458 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
460 .target_residency = 400,
461 .enter = &intel_idle,
462 .enter_s2idle = intel_idle_s2idle, },
467 static struct cpuidle_state ivt_cstates_8s[] __initdata = {
470 .desc = "MWAIT 0x00",
471 .flags = MWAIT2flg(0x00),
473 .target_residency = 1,
474 .enter = &intel_idle,
475 .enter_s2idle = intel_idle_s2idle, },
478 .desc = "MWAIT 0x01",
479 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
481 .target_residency = 500,
482 .enter = &intel_idle,
483 .enter_s2idle = intel_idle_s2idle, },
486 .desc = "MWAIT 0x10",
487 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
489 .target_residency = 600,
490 .enter = &intel_idle,
491 .enter_s2idle = intel_idle_s2idle, },
494 .desc = "MWAIT 0x20",
495 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
497 .target_residency = 700,
498 .enter = &intel_idle,
499 .enter_s2idle = intel_idle_s2idle, },
504 static struct cpuidle_state hsw_cstates[] __initdata = {
507 .desc = "MWAIT 0x00",
508 .flags = MWAIT2flg(0x00),
510 .target_residency = 2,
511 .enter = &intel_idle,
512 .enter_s2idle = intel_idle_s2idle, },
515 .desc = "MWAIT 0x01",
516 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
518 .target_residency = 20,
519 .enter = &intel_idle,
520 .enter_s2idle = intel_idle_s2idle, },
523 .desc = "MWAIT 0x10",
524 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
526 .target_residency = 100,
527 .enter = &intel_idle,
528 .enter_s2idle = intel_idle_s2idle, },
531 .desc = "MWAIT 0x20",
532 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
534 .target_residency = 400,
535 .enter = &intel_idle,
536 .enter_s2idle = intel_idle_s2idle, },
539 .desc = "MWAIT 0x32",
540 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
542 .target_residency = 500,
543 .enter = &intel_idle,
544 .enter_s2idle = intel_idle_s2idle, },
547 .desc = "MWAIT 0x40",
548 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
550 .target_residency = 900,
551 .enter = &intel_idle,
552 .enter_s2idle = intel_idle_s2idle, },
555 .desc = "MWAIT 0x50",
556 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
558 .target_residency = 1800,
559 .enter = &intel_idle,
560 .enter_s2idle = intel_idle_s2idle, },
563 .desc = "MWAIT 0x60",
564 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
565 .exit_latency = 2600,
566 .target_residency = 7700,
567 .enter = &intel_idle,
568 .enter_s2idle = intel_idle_s2idle, },
572 static struct cpuidle_state bdw_cstates[] __initdata = {
575 .desc = "MWAIT 0x00",
576 .flags = MWAIT2flg(0x00),
578 .target_residency = 2,
579 .enter = &intel_idle,
580 .enter_s2idle = intel_idle_s2idle, },
583 .desc = "MWAIT 0x01",
584 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
586 .target_residency = 20,
587 .enter = &intel_idle,
588 .enter_s2idle = intel_idle_s2idle, },
591 .desc = "MWAIT 0x10",
592 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
594 .target_residency = 100,
595 .enter = &intel_idle,
596 .enter_s2idle = intel_idle_s2idle, },
599 .desc = "MWAIT 0x20",
600 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
602 .target_residency = 400,
603 .enter = &intel_idle,
604 .enter_s2idle = intel_idle_s2idle, },
607 .desc = "MWAIT 0x32",
608 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
610 .target_residency = 500,
611 .enter = &intel_idle,
612 .enter_s2idle = intel_idle_s2idle, },
615 .desc = "MWAIT 0x40",
616 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
618 .target_residency = 900,
619 .enter = &intel_idle,
620 .enter_s2idle = intel_idle_s2idle, },
623 .desc = "MWAIT 0x50",
624 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
626 .target_residency = 1800,
627 .enter = &intel_idle,
628 .enter_s2idle = intel_idle_s2idle, },
631 .desc = "MWAIT 0x60",
632 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
633 .exit_latency = 2600,
634 .target_residency = 7700,
635 .enter = &intel_idle,
636 .enter_s2idle = intel_idle_s2idle, },
641 static struct cpuidle_state skl_cstates[] __initdata = {
644 .desc = "MWAIT 0x00",
645 .flags = MWAIT2flg(0x00),
647 .target_residency = 2,
648 .enter = &intel_idle,
649 .enter_s2idle = intel_idle_s2idle, },
652 .desc = "MWAIT 0x01",
653 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
655 .target_residency = 20,
656 .enter = &intel_idle,
657 .enter_s2idle = intel_idle_s2idle, },
660 .desc = "MWAIT 0x10",
661 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
663 .target_residency = 100,
664 .enter = &intel_idle,
665 .enter_s2idle = intel_idle_s2idle, },
668 .desc = "MWAIT 0x20",
669 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
671 .target_residency = 200,
672 .enter = &intel_idle,
673 .enter_s2idle = intel_idle_s2idle, },
676 .desc = "MWAIT 0x33",
677 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
679 .target_residency = 800,
680 .enter = &intel_idle,
681 .enter_s2idle = intel_idle_s2idle, },
684 .desc = "MWAIT 0x40",
685 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
687 .target_residency = 800,
688 .enter = &intel_idle,
689 .enter_s2idle = intel_idle_s2idle, },
692 .desc = "MWAIT 0x50",
693 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
695 .target_residency = 5000,
696 .enter = &intel_idle,
697 .enter_s2idle = intel_idle_s2idle, },
700 .desc = "MWAIT 0x60",
701 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
703 .target_residency = 5000,
704 .enter = &intel_idle,
705 .enter_s2idle = intel_idle_s2idle, },
710 static struct cpuidle_state skx_cstates[] __initdata = {
713 .desc = "MWAIT 0x00",
714 .flags = MWAIT2flg(0x00),
716 .target_residency = 2,
717 .enter = &intel_idle,
718 .enter_s2idle = intel_idle_s2idle, },
721 .desc = "MWAIT 0x01",
722 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
724 .target_residency = 20,
725 .enter = &intel_idle,
726 .enter_s2idle = intel_idle_s2idle, },
729 .desc = "MWAIT 0x20",
730 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
732 .target_residency = 600,
733 .enter = &intel_idle,
734 .enter_s2idle = intel_idle_s2idle, },
739 static struct cpuidle_state icx_cstates[] __initdata = {
742 .desc = "MWAIT 0x00",
743 .flags = MWAIT2flg(0x00),
745 .target_residency = 1,
746 .enter = &intel_idle,
747 .enter_s2idle = intel_idle_s2idle, },
750 .desc = "MWAIT 0x01",
751 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
753 .target_residency = 4,
754 .enter = &intel_idle,
755 .enter_s2idle = intel_idle_s2idle, },
758 .desc = "MWAIT 0x20",
759 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
761 .target_residency = 384,
762 .enter = &intel_idle,
763 .enter_s2idle = intel_idle_s2idle, },
768 static struct cpuidle_state atom_cstates[] __initdata = {
771 .desc = "MWAIT 0x00",
772 .flags = MWAIT2flg(0x00),
774 .target_residency = 20,
775 .enter = &intel_idle,
776 .enter_s2idle = intel_idle_s2idle, },
779 .desc = "MWAIT 0x10",
780 .flags = MWAIT2flg(0x10),
782 .target_residency = 80,
783 .enter = &intel_idle,
784 .enter_s2idle = intel_idle_s2idle, },
787 .desc = "MWAIT 0x30",
788 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
790 .target_residency = 400,
791 .enter = &intel_idle,
792 .enter_s2idle = intel_idle_s2idle, },
795 .desc = "MWAIT 0x52",
796 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
798 .target_residency = 560,
799 .enter = &intel_idle,
800 .enter_s2idle = intel_idle_s2idle, },
804 static struct cpuidle_state tangier_cstates[] __initdata = {
807 .desc = "MWAIT 0x00",
808 .flags = MWAIT2flg(0x00),
810 .target_residency = 4,
811 .enter = &intel_idle,
812 .enter_s2idle = intel_idle_s2idle, },
815 .desc = "MWAIT 0x30",
816 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
818 .target_residency = 400,
819 .enter = &intel_idle,
820 .enter_s2idle = intel_idle_s2idle, },
823 .desc = "MWAIT 0x52",
824 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
826 .target_residency = 560,
827 .enter = &intel_idle,
828 .enter_s2idle = intel_idle_s2idle, },
831 .desc = "MWAIT 0x60",
832 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
833 .exit_latency = 1200,
834 .target_residency = 4000,
835 .enter = &intel_idle,
836 .enter_s2idle = intel_idle_s2idle, },
839 .desc = "MWAIT 0x64",
840 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
841 .exit_latency = 10000,
842 .target_residency = 20000,
843 .enter = &intel_idle,
844 .enter_s2idle = intel_idle_s2idle, },
848 static struct cpuidle_state avn_cstates[] __initdata = {
851 .desc = "MWAIT 0x00",
852 .flags = MWAIT2flg(0x00),
854 .target_residency = 2,
855 .enter = &intel_idle,
856 .enter_s2idle = intel_idle_s2idle, },
859 .desc = "MWAIT 0x51",
860 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
862 .target_residency = 45,
863 .enter = &intel_idle,
864 .enter_s2idle = intel_idle_s2idle, },
868 static struct cpuidle_state knl_cstates[] __initdata = {
871 .desc = "MWAIT 0x00",
872 .flags = MWAIT2flg(0x00),
874 .target_residency = 2,
875 .enter = &intel_idle,
876 .enter_s2idle = intel_idle_s2idle },
879 .desc = "MWAIT 0x10",
880 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
882 .target_residency = 500,
883 .enter = &intel_idle,
884 .enter_s2idle = intel_idle_s2idle },
889 static struct cpuidle_state bxt_cstates[] __initdata = {
892 .desc = "MWAIT 0x00",
893 .flags = MWAIT2flg(0x00),
895 .target_residency = 2,
896 .enter = &intel_idle,
897 .enter_s2idle = intel_idle_s2idle, },
900 .desc = "MWAIT 0x01",
901 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
903 .target_residency = 20,
904 .enter = &intel_idle,
905 .enter_s2idle = intel_idle_s2idle, },
908 .desc = "MWAIT 0x20",
909 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
911 .target_residency = 133,
912 .enter = &intel_idle,
913 .enter_s2idle = intel_idle_s2idle, },
916 .desc = "MWAIT 0x31",
917 .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
919 .target_residency = 155,
920 .enter = &intel_idle,
921 .enter_s2idle = intel_idle_s2idle, },
924 .desc = "MWAIT 0x40",
925 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
926 .exit_latency = 1000,
927 .target_residency = 1000,
928 .enter = &intel_idle,
929 .enter_s2idle = intel_idle_s2idle, },
932 .desc = "MWAIT 0x50",
933 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
934 .exit_latency = 2000,
935 .target_residency = 2000,
936 .enter = &intel_idle,
937 .enter_s2idle = intel_idle_s2idle, },
940 .desc = "MWAIT 0x60",
941 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
942 .exit_latency = 10000,
943 .target_residency = 10000,
944 .enter = &intel_idle,
945 .enter_s2idle = intel_idle_s2idle, },
950 static struct cpuidle_state dnv_cstates[] __initdata = {
953 .desc = "MWAIT 0x00",
954 .flags = MWAIT2flg(0x00),
956 .target_residency = 2,
957 .enter = &intel_idle,
958 .enter_s2idle = intel_idle_s2idle, },
961 .desc = "MWAIT 0x01",
962 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
964 .target_residency = 20,
965 .enter = &intel_idle,
966 .enter_s2idle = intel_idle_s2idle, },
969 .desc = "MWAIT 0x20",
970 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
972 .target_residency = 500,
973 .enter = &intel_idle,
974 .enter_s2idle = intel_idle_s2idle, },
979 static const struct idle_cpu idle_cpu_nehalem __initconst = {
980 .state_table = nehalem_cstates,
981 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
982 .disable_promotion_to_c1e = true,
985 static const struct idle_cpu idle_cpu_nhx __initconst = {
986 .state_table = nehalem_cstates,
987 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
988 .disable_promotion_to_c1e = true,
992 static const struct idle_cpu idle_cpu_atom __initconst = {
993 .state_table = atom_cstates,
996 static const struct idle_cpu idle_cpu_tangier __initconst = {
997 .state_table = tangier_cstates,
1000 static const struct idle_cpu idle_cpu_lincroft __initconst = {
1001 .state_table = atom_cstates,
1002 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
1005 static const struct idle_cpu idle_cpu_snb __initconst = {
1006 .state_table = snb_cstates,
1007 .disable_promotion_to_c1e = true,
1010 static const struct idle_cpu idle_cpu_snx __initconst = {
1011 .state_table = snb_cstates,
1012 .disable_promotion_to_c1e = true,
1016 static const struct idle_cpu idle_cpu_byt __initconst = {
1017 .state_table = byt_cstates,
1018 .disable_promotion_to_c1e = true,
1019 .byt_auto_demotion_disable_flag = true,
1022 static const struct idle_cpu idle_cpu_cht __initconst = {
1023 .state_table = cht_cstates,
1024 .disable_promotion_to_c1e = true,
1025 .byt_auto_demotion_disable_flag = true,
1028 static const struct idle_cpu idle_cpu_ivb __initconst = {
1029 .state_table = ivb_cstates,
1030 .disable_promotion_to_c1e = true,
1033 static const struct idle_cpu idle_cpu_ivt __initconst = {
1034 .state_table = ivt_cstates,
1035 .disable_promotion_to_c1e = true,
1039 static const struct idle_cpu idle_cpu_hsw __initconst = {
1040 .state_table = hsw_cstates,
1041 .disable_promotion_to_c1e = true,
1044 static const struct idle_cpu idle_cpu_hsx __initconst = {
1045 .state_table = hsw_cstates,
1046 .disable_promotion_to_c1e = true,
1050 static const struct idle_cpu idle_cpu_bdw __initconst = {
1051 .state_table = bdw_cstates,
1052 .disable_promotion_to_c1e = true,
1055 static const struct idle_cpu idle_cpu_bdx __initconst = {
1056 .state_table = bdw_cstates,
1057 .disable_promotion_to_c1e = true,
1061 static const struct idle_cpu idle_cpu_skl __initconst = {
1062 .state_table = skl_cstates,
1063 .disable_promotion_to_c1e = true,
1066 static const struct idle_cpu idle_cpu_skx __initconst = {
1067 .state_table = skx_cstates,
1068 .disable_promotion_to_c1e = true,
1072 static const struct idle_cpu idle_cpu_icx __initconst = {
1073 .state_table = icx_cstates,
1074 .disable_promotion_to_c1e = true,
1078 static const struct idle_cpu idle_cpu_avn __initconst = {
1079 .state_table = avn_cstates,
1080 .disable_promotion_to_c1e = true,
1084 static const struct idle_cpu idle_cpu_knl __initconst = {
1085 .state_table = knl_cstates,
1089 static const struct idle_cpu idle_cpu_bxt __initconst = {
1090 .state_table = bxt_cstates,
1091 .disable_promotion_to_c1e = true,
1094 static const struct idle_cpu idle_cpu_dnv __initconst = {
1095 .state_table = dnv_cstates,
1096 .disable_promotion_to_c1e = true,
1100 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
1101 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &idle_cpu_nhx),
1102 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &idle_cpu_nehalem),
1103 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_G, &idle_cpu_nehalem),
1104 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE, &idle_cpu_nehalem),
1105 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP, &idle_cpu_nhx),
1106 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX, &idle_cpu_nhx),
1107 X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL, &idle_cpu_atom),
1108 X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL_MID, &idle_cpu_lincroft),
1109 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX, &idle_cpu_nhx),
1110 X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &idle_cpu_snb),
1111 X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &idle_cpu_snx),
1112 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL, &idle_cpu_atom),
1113 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &idle_cpu_byt),
1114 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &idle_cpu_tangier),
1115 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &idle_cpu_cht),
1116 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &idle_cpu_ivb),
1117 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &idle_cpu_ivt),
1118 X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &idle_cpu_hsw),
1119 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &idle_cpu_hsx),
1120 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &idle_cpu_hsw),
1121 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &idle_cpu_hsw),
1122 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, &idle_cpu_avn),
1123 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &idle_cpu_bdw),
1124 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &idle_cpu_bdw),
1125 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &idle_cpu_bdx),
1126 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &idle_cpu_bdx),
1127 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &idle_cpu_skl),
1128 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &idle_cpu_skl),
1129 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &idle_cpu_skl),
1130 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &idle_cpu_skl),
1131 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &idle_cpu_skx),
1132 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &idle_cpu_icx),
1133 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl),
1134 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl),
1135 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &idle_cpu_bxt),
1136 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &idle_cpu_bxt),
1137 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &idle_cpu_dnv),
1138 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &idle_cpu_dnv),
1142 static const struct x86_cpu_id intel_mwait_ids[] __initconst = {
1143 X86_MATCH_VENDOR_FAM_FEATURE(INTEL, 6, X86_FEATURE_MWAIT, NULL),
1147 static bool __init intel_idle_max_cstate_reached(int cstate)
1149 if (cstate + 1 > max_cstate) {
1150 pr_info("max_cstate %d reached\n", max_cstate);
1156 #ifdef CONFIG_ACPI_PROCESSOR_CSTATE
1157 #include <acpi/processor.h>
1159 static bool no_acpi __read_mostly;
1160 module_param(no_acpi, bool, 0444);
1161 MODULE_PARM_DESC(no_acpi, "Do not use ACPI _CST for building the idle states list");
1163 static bool force_use_acpi __read_mostly; /* No effect if no_acpi is set. */
1164 module_param_named(use_acpi, force_use_acpi, bool, 0444);
1165 MODULE_PARM_DESC(use_acpi, "Use ACPI _CST for building the idle states list");
1167 static struct acpi_processor_power acpi_state_table __initdata;
1170 * intel_idle_cst_usable - Check if the _CST information can be used.
1172 * Check if all of the C-states listed by _CST in the max_cstate range are
1173 * ACPI_CSTATE_FFH, which means that they should be entered via MWAIT.
1175 static bool __init intel_idle_cst_usable(void)
1179 limit = min_t(int, min_t(int, CPUIDLE_STATE_MAX, max_cstate + 1),
1180 acpi_state_table.count);
1182 for (cstate = 1; cstate < limit; cstate++) {
1183 struct acpi_processor_cx *cx = &acpi_state_table.states[cstate];
1185 if (cx->entry_method != ACPI_CSTATE_FFH)
1192 static bool __init intel_idle_acpi_cst_extract(void)
1197 pr_debug("Not allowed to use ACPI _CST\n");
1201 for_each_possible_cpu(cpu) {
1202 struct acpi_processor *pr = per_cpu(processors, cpu);
1207 if (acpi_processor_evaluate_cst(pr->handle, cpu, &acpi_state_table))
1210 acpi_state_table.count++;
1212 if (!intel_idle_cst_usable())
1215 if (!acpi_processor_claim_cst_control()) {
1216 acpi_state_table.count = 0;
1223 pr_debug("ACPI _CST not found or not usable\n");
1227 static void __init intel_idle_init_cstates_acpi(struct cpuidle_driver *drv)
1229 int cstate, limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1232 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1233 * the interesting states are ACPI_CSTATE_FFH.
1235 for (cstate = 1; cstate < limit; cstate++) {
1236 struct acpi_processor_cx *cx;
1237 struct cpuidle_state *state;
1239 if (intel_idle_max_cstate_reached(cstate))
1242 cx = &acpi_state_table.states[cstate];
1244 state = &drv->states[drv->state_count++];
1246 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d_ACPI", cstate);
1247 strlcpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1248 state->exit_latency = cx->latency;
1250 * For C1-type C-states use the same number for both the exit
1251 * latency and target residency, because that is the case for
1252 * C1 in the majority of the static C-states tables above.
1253 * For the other types of C-states, however, set the target
1254 * residency to 3 times the exit latency which should lead to
1255 * a reasonable balance between energy-efficiency and
1256 * performance in the majority of interesting cases.
1258 state->target_residency = cx->latency;
1259 if (cx->type > ACPI_STATE_C1)
1260 state->target_residency *= 3;
1262 state->flags = MWAIT2flg(cx->address);
1263 if (cx->type > ACPI_STATE_C2)
1264 state->flags |= CPUIDLE_FLAG_TLB_FLUSHED;
1266 if (disabled_states_mask & BIT(cstate))
1267 state->flags |= CPUIDLE_FLAG_OFF;
1269 state->enter = intel_idle;
1270 state->enter_s2idle = intel_idle_s2idle;
1274 static bool __init intel_idle_off_by_default(u32 mwait_hint)
1279 * If there are no _CST C-states, do not disable any C-states by
1282 if (!acpi_state_table.count)
1285 limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1287 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1288 * the interesting states are ACPI_CSTATE_FFH.
1290 for (cstate = 1; cstate < limit; cstate++) {
1291 if (acpi_state_table.states[cstate].address == mwait_hint)
1296 #else /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1297 #define force_use_acpi (false)
1299 static inline bool intel_idle_acpi_cst_extract(void) { return false; }
1300 static inline void intel_idle_init_cstates_acpi(struct cpuidle_driver *drv) { }
1301 static inline bool intel_idle_off_by_default(u32 mwait_hint) { return false; }
1302 #endif /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1305 * ivt_idle_state_table_update - Tune the idle states table for Ivy Town.
1307 * Tune IVT multi-socket targets.
1308 * Assumption: num_sockets == (max_package_num + 1).
1310 static void __init ivt_idle_state_table_update(void)
1312 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
1313 int cpu, package_num, num_sockets = 1;
1315 for_each_online_cpu(cpu) {
1316 package_num = topology_physical_package_id(cpu);
1317 if (package_num + 1 > num_sockets) {
1318 num_sockets = package_num + 1;
1320 if (num_sockets > 4) {
1321 cpuidle_state_table = ivt_cstates_8s;
1327 if (num_sockets > 2)
1328 cpuidle_state_table = ivt_cstates_4s;
1330 /* else, 1 and 2 socket systems use default ivt_cstates */
1334 * irtl_2_usec - IRTL to microseconds conversion.
1335 * @irtl: IRTL MSR value.
1337 * Translate the IRTL (Interrupt Response Time Limit) MSR value to microseconds.
1339 static unsigned long long __init irtl_2_usec(unsigned long long irtl)
1341 static const unsigned int irtl_ns_units[] __initconst = {
1342 1, 32, 1024, 32768, 1048576, 33554432, 0, 0
1344 unsigned long long ns;
1349 ns = irtl_ns_units[(irtl >> 10) & 0x7];
1351 return div_u64((irtl & 0x3FF) * ns, NSEC_PER_USEC);
1355 * bxt_idle_state_table_update - Fix up the Broxton idle states table.
1357 * On BXT, trust the IRTL (Interrupt Response Time Limit) MSR to show the
1358 * definitive maximum latency and use the same value for target_residency.
1360 static void __init bxt_idle_state_table_update(void)
1362 unsigned long long msr;
1365 rdmsrl(MSR_PKGC6_IRTL, msr);
1366 usec = irtl_2_usec(msr);
1368 bxt_cstates[2].exit_latency = usec;
1369 bxt_cstates[2].target_residency = usec;
1372 rdmsrl(MSR_PKGC7_IRTL, msr);
1373 usec = irtl_2_usec(msr);
1375 bxt_cstates[3].exit_latency = usec;
1376 bxt_cstates[3].target_residency = usec;
1379 rdmsrl(MSR_PKGC8_IRTL, msr);
1380 usec = irtl_2_usec(msr);
1382 bxt_cstates[4].exit_latency = usec;
1383 bxt_cstates[4].target_residency = usec;
1386 rdmsrl(MSR_PKGC9_IRTL, msr);
1387 usec = irtl_2_usec(msr);
1389 bxt_cstates[5].exit_latency = usec;
1390 bxt_cstates[5].target_residency = usec;
1393 rdmsrl(MSR_PKGC10_IRTL, msr);
1394 usec = irtl_2_usec(msr);
1396 bxt_cstates[6].exit_latency = usec;
1397 bxt_cstates[6].target_residency = usec;
1403 * sklh_idle_state_table_update - Fix up the Sky Lake idle states table.
1405 * On SKL-H (model 0x5e) skip C8 and C9 if C10 is enabled and SGX disabled.
1407 static void __init sklh_idle_state_table_update(void)
1409 unsigned long long msr;
1410 unsigned int eax, ebx, ecx, edx;
1413 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1414 if (max_cstate <= 7)
1417 /* if PC10 not present in CPUID.MWAIT.EDX */
1418 if ((mwait_substates & (0xF << 28)) == 0)
1421 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1423 /* PC10 is not enabled in PKG C-state limit */
1424 if ((msr & 0xF) != 8)
1428 cpuid(7, &eax, &ebx, &ecx, &edx);
1430 /* if SGX is present */
1431 if (ebx & (1 << 2)) {
1433 rdmsrl(MSR_IA32_FEAT_CTL, msr);
1435 /* if SGX is enabled */
1436 if (msr & (1 << 18))
1440 skl_cstates[5].flags |= CPUIDLE_FLAG_UNUSABLE; /* C8-SKL */
1441 skl_cstates[6].flags |= CPUIDLE_FLAG_UNUSABLE; /* C9-SKL */
1444 static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)
1446 unsigned int mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint) + 1;
1447 unsigned int num_substates = (mwait_substates >> mwait_cstate * 4) &
1448 MWAIT_SUBSTATE_MASK;
1450 /* Ignore the C-state if there are NO sub-states in CPUID for it. */
1451 if (num_substates == 0)
1454 if (mwait_cstate > 2 && !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1455 mark_tsc_unstable("TSC halts in idle states deeper than C2");
1460 static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
1464 switch (boot_cpu_data.x86_model) {
1465 case INTEL_FAM6_IVYBRIDGE_X:
1466 ivt_idle_state_table_update();
1468 case INTEL_FAM6_ATOM_GOLDMONT:
1469 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
1470 bxt_idle_state_table_update();
1472 case INTEL_FAM6_SKYLAKE:
1473 sklh_idle_state_table_update();
1477 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
1478 unsigned int mwait_hint;
1480 if (intel_idle_max_cstate_reached(cstate))
1483 if (!cpuidle_state_table[cstate].enter &&
1484 !cpuidle_state_table[cstate].enter_s2idle)
1487 /* If marked as unusable, skip this state. */
1488 if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_UNUSABLE) {
1489 pr_debug("state %s is disabled\n",
1490 cpuidle_state_table[cstate].name);
1494 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
1495 if (!intel_idle_verify_cstate(mwait_hint))
1498 /* Structure copy. */
1499 drv->states[drv->state_count] = cpuidle_state_table[cstate];
1501 if ((disabled_states_mask & BIT(drv->state_count)) ||
1502 ((icpu->use_acpi || force_use_acpi) &&
1503 intel_idle_off_by_default(mwait_hint) &&
1504 !(cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_ALWAYS_ENABLE)))
1505 drv->states[drv->state_count].flags |= CPUIDLE_FLAG_OFF;
1510 if (icpu->byt_auto_demotion_disable_flag) {
1511 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1512 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1517 * intel_idle_cpuidle_driver_init - Create the list of available idle states.
1518 * @drv: cpuidle driver structure to initialize.
1520 static void __init intel_idle_cpuidle_driver_init(struct cpuidle_driver *drv)
1522 cpuidle_poll_state_init(drv);
1524 if (disabled_states_mask & BIT(0))
1525 drv->states[0].flags |= CPUIDLE_FLAG_OFF;
1527 drv->state_count = 1;
1530 intel_idle_init_cstates_icpu(drv);
1532 intel_idle_init_cstates_acpi(drv);
1535 static void auto_demotion_disable(void)
1537 unsigned long long msr_bits;
1539 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1540 msr_bits &= ~auto_demotion_disable_flags;
1541 wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1544 static void c1e_promotion_disable(void)
1546 unsigned long long msr_bits;
1548 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
1550 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
1554 * intel_idle_cpu_init - Register the target CPU with the cpuidle core.
1555 * @cpu: CPU to initialize.
1557 * Register a cpuidle device object for @cpu and update its MSRs in accordance
1558 * with the processor model flags.
1560 static int intel_idle_cpu_init(unsigned int cpu)
1562 struct cpuidle_device *dev;
1564 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1567 if (cpuidle_register_device(dev)) {
1568 pr_debug("cpuidle_register_device %d failed!\n", cpu);
1572 if (auto_demotion_disable_flags)
1573 auto_demotion_disable();
1575 if (disable_promotion_to_c1e)
1576 c1e_promotion_disable();
1581 static int intel_idle_cpu_online(unsigned int cpu)
1583 struct cpuidle_device *dev;
1585 if (!boot_cpu_has(X86_FEATURE_ARAT))
1586 tick_broadcast_enable();
1589 * Some systems can hotplug a cpu at runtime after
1590 * the kernel has booted, we have to initialize the
1591 * driver in this case
1593 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1594 if (!dev->registered)
1595 return intel_idle_cpu_init(cpu);
1601 * intel_idle_cpuidle_devices_uninit - Unregister all cpuidle devices.
1603 static void __init intel_idle_cpuidle_devices_uninit(void)
1607 for_each_online_cpu(i)
1608 cpuidle_unregister_device(per_cpu_ptr(intel_idle_cpuidle_devices, i));
1611 static int __init intel_idle_init(void)
1613 const struct x86_cpu_id *id;
1614 unsigned int eax, ebx, ecx;
1617 /* Do not load intel_idle at all for now if idle= is passed */
1618 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1621 if (max_cstate == 0) {
1622 pr_debug("disabled\n");
1626 id = x86_match_cpu(intel_idle_ids);
1628 if (!boot_cpu_has(X86_FEATURE_MWAIT)) {
1629 pr_debug("Please enable MWAIT in BIOS SETUP\n");
1633 id = x86_match_cpu(intel_mwait_ids);
1638 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1641 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
1643 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
1644 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
1648 pr_debug("MWAIT substates: 0x%x\n", mwait_substates);
1650 icpu = (const struct idle_cpu *)id->driver_data;
1652 cpuidle_state_table = icpu->state_table;
1653 auto_demotion_disable_flags = icpu->auto_demotion_disable_flags;
1654 disable_promotion_to_c1e = icpu->disable_promotion_to_c1e;
1655 if (icpu->use_acpi || force_use_acpi)
1656 intel_idle_acpi_cst_extract();
1657 } else if (!intel_idle_acpi_cst_extract()) {
1661 pr_debug("v" INTEL_IDLE_VERSION " model 0x%X\n",
1662 boot_cpu_data.x86_model);
1664 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1665 if (!intel_idle_cpuidle_devices)
1668 intel_idle_cpuidle_driver_init(&intel_idle_driver);
1670 retval = cpuidle_register_driver(&intel_idle_driver);
1672 struct cpuidle_driver *drv = cpuidle_get_driver();
1673 printk(KERN_DEBUG pr_fmt("intel_idle yielding to %s\n"),
1674 drv ? drv->name : "none");
1675 goto init_driver_fail;
1678 retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online",
1679 intel_idle_cpu_online, NULL);
1683 pr_debug("Local APIC timer is reliable in %s\n",
1684 boot_cpu_has(X86_FEATURE_ARAT) ? "all C-states" : "C1");
1689 intel_idle_cpuidle_devices_uninit();
1690 cpuidle_unregister_driver(&intel_idle_driver);
1692 free_percpu(intel_idle_cpuidle_devices);
1696 device_initcall(intel_idle_init);
1699 * We are not really modular, but we used to support that. Meaning we also
1700 * support "intel_idle.max_cstate=..." at boot and also a read-only export of
1701 * it at /sys/module/intel_idle/parameters/max_cstate -- so using module_param
1702 * is the easiest way (currently) to continue doing that.
1704 module_param(max_cstate, int, 0444);
1706 * The positions of the bits that are set in this number are the indices of the
1707 * idle states to be disabled by default (as reflected by the names of the
1708 * corresponding idle state directories in sysfs, "state0", "state1" ...
1709 * "state<i>" ..., where <i> is the index of the given state).
1711 module_param_named(states_off, disabled_states_mask, uint, 0444);
1712 MODULE_PARM_DESC(states_off, "Mask of disabled idle states");