1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_idle.c - native hardware idle loop for modern Intel processors
5 * Copyright (c) 2013 - 2020, Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
11 * intel_idle is a cpuidle driver that loads on all Intel CPUs with MWAIT
12 * in lieu of the legacy ACPI processor_idle driver. The intent is to
13 * make Linux more efficient on these processors, as intel_idle knows
14 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
20 * All CPUs have same idle states as boot CPU
22 * Chipset BM_STS (bus master status) bit is a NOP
23 * for preventing entry into deep C-states
25 * CPU will flush caches as needed when entering a C-state via MWAIT
26 * (in contrast to entering ACPI C3, in which case the WBINVD
27 * instruction needs to be executed to flush the caches)
33 * ACPI has a .suspend hack to turn off deep c-statees during suspend
34 * to avoid complications with the lapic timer workaround.
35 * Have not seen issues with suspend, but may need same workaround here.
39 /* un-comment DEBUG to enable pr_debug() statements */
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/acpi.h>
45 #include <linux/kernel.h>
46 #include <linux/cpuidle.h>
47 #include <linux/tick.h>
48 #include <trace/events/power.h>
49 #include <linux/sched.h>
50 #include <linux/notifier.h>
51 #include <linux/cpu.h>
52 #include <linux/moduleparam.h>
53 #include <asm/cpu_device_id.h>
54 #include <asm/intel-family.h>
55 #include <asm/mwait.h>
58 #define INTEL_IDLE_VERSION "0.5.1"
60 static struct cpuidle_driver intel_idle_driver = {
64 /* intel_idle.max_cstate=0 disables driver */
65 static int max_cstate = CPUIDLE_STATE_MAX - 1;
66 static unsigned int disabled_states_mask;
67 static unsigned int preferred_states_mask;
69 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
71 static unsigned long auto_demotion_disable_flags;
74 C1E_PROMOTION_PRESERVE,
77 } c1e_promotion = C1E_PROMOTION_PRESERVE;
80 struct cpuidle_state *state_table;
83 * Hardware C-state auto-demotion may not always be optimal.
84 * Indicate which enable bits to clear here.
86 unsigned long auto_demotion_disable_flags;
87 bool byt_auto_demotion_disable_flag;
88 bool disable_promotion_to_c1e;
92 static const struct idle_cpu *icpu __initdata;
93 static struct cpuidle_state *cpuidle_state_table __initdata;
95 static unsigned int mwait_substates __initdata;
98 * Enable interrupts before entering the C-state. On some platforms and for
99 * some C-states, this may measurably decrease interrupt latency.
101 #define CPUIDLE_FLAG_IRQ_ENABLE BIT(14)
104 * Enable this state by default even if the ACPI _CST does not list it.
106 #define CPUIDLE_FLAG_ALWAYS_ENABLE BIT(15)
109 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
110 * the C-state (top nibble) and sub-state (bottom nibble)
111 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
113 * We store the hint at the top of our "flags" for each state.
115 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
116 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
119 * intel_idle - Ask the processor to enter the given idle state.
120 * @dev: cpuidle device of the target CPU.
121 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
122 * @index: Target idle state index.
124 * Use the MWAIT instruction to notify the processor that the CPU represented by
125 * @dev is idle and it can try to enter the idle state corresponding to @index.
127 * If the local APIC timer is not known to be reliable in the target idle state,
128 * enable one-shot tick broadcasting for the target CPU before executing MWAIT.
130 * Must be called under local_irq_disable().
132 static __cpuidle int intel_idle(struct cpuidle_device *dev,
133 struct cpuidle_driver *drv, int index)
135 struct cpuidle_state *state = &drv->states[index];
136 unsigned long eax = flg2MWAIT(state->flags);
137 unsigned long ecx = 1; /* break on interrupt flag */
139 if (state->flags & CPUIDLE_FLAG_IRQ_ENABLE)
142 mwait_idle_with_hints(eax, ecx);
148 * intel_idle_s2idle - Ask the processor to enter the given idle state.
149 * @dev: cpuidle device of the target CPU.
150 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
151 * @index: Target idle state index.
153 * Use the MWAIT instruction to notify the processor that the CPU represented by
154 * @dev is idle and it can try to enter the idle state corresponding to @index.
156 * Invoked as a suspend-to-idle callback routine with frozen user space, frozen
157 * scheduler tick and suspended scheduler clock on the target CPU.
159 static __cpuidle int intel_idle_s2idle(struct cpuidle_device *dev,
160 struct cpuidle_driver *drv, int index)
162 unsigned long eax = flg2MWAIT(drv->states[index].flags);
163 unsigned long ecx = 1; /* break on interrupt flag */
165 mwait_idle_with_hints(eax, ecx);
171 * States are indexed by the cstate number,
172 * which is also the index into the MWAIT hint array.
173 * Thus C0 is a dummy.
175 static struct cpuidle_state nehalem_cstates[] __initdata = {
178 .desc = "MWAIT 0x00",
179 .flags = MWAIT2flg(0x00),
181 .target_residency = 6,
182 .enter = &intel_idle,
183 .enter_s2idle = intel_idle_s2idle, },
186 .desc = "MWAIT 0x01",
187 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
189 .target_residency = 20,
190 .enter = &intel_idle,
191 .enter_s2idle = intel_idle_s2idle, },
194 .desc = "MWAIT 0x10",
195 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
197 .target_residency = 80,
198 .enter = &intel_idle,
199 .enter_s2idle = intel_idle_s2idle, },
202 .desc = "MWAIT 0x20",
203 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
205 .target_residency = 800,
206 .enter = &intel_idle,
207 .enter_s2idle = intel_idle_s2idle, },
212 static struct cpuidle_state snb_cstates[] __initdata = {
215 .desc = "MWAIT 0x00",
216 .flags = MWAIT2flg(0x00),
218 .target_residency = 2,
219 .enter = &intel_idle,
220 .enter_s2idle = intel_idle_s2idle, },
223 .desc = "MWAIT 0x01",
224 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
226 .target_residency = 20,
227 .enter = &intel_idle,
228 .enter_s2idle = intel_idle_s2idle, },
231 .desc = "MWAIT 0x10",
232 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
234 .target_residency = 211,
235 .enter = &intel_idle,
236 .enter_s2idle = intel_idle_s2idle, },
239 .desc = "MWAIT 0x20",
240 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
242 .target_residency = 345,
243 .enter = &intel_idle,
244 .enter_s2idle = intel_idle_s2idle, },
247 .desc = "MWAIT 0x30",
248 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
250 .target_residency = 345,
251 .enter = &intel_idle,
252 .enter_s2idle = intel_idle_s2idle, },
257 static struct cpuidle_state byt_cstates[] __initdata = {
260 .desc = "MWAIT 0x00",
261 .flags = MWAIT2flg(0x00),
263 .target_residency = 1,
264 .enter = &intel_idle,
265 .enter_s2idle = intel_idle_s2idle, },
268 .desc = "MWAIT 0x58",
269 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
271 .target_residency = 275,
272 .enter = &intel_idle,
273 .enter_s2idle = intel_idle_s2idle, },
276 .desc = "MWAIT 0x52",
277 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
279 .target_residency = 560,
280 .enter = &intel_idle,
281 .enter_s2idle = intel_idle_s2idle, },
284 .desc = "MWAIT 0x60",
285 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
286 .exit_latency = 1200,
287 .target_residency = 4000,
288 .enter = &intel_idle,
289 .enter_s2idle = intel_idle_s2idle, },
292 .desc = "MWAIT 0x64",
293 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
294 .exit_latency = 10000,
295 .target_residency = 20000,
296 .enter = &intel_idle,
297 .enter_s2idle = intel_idle_s2idle, },
302 static struct cpuidle_state cht_cstates[] __initdata = {
305 .desc = "MWAIT 0x00",
306 .flags = MWAIT2flg(0x00),
308 .target_residency = 1,
309 .enter = &intel_idle,
310 .enter_s2idle = intel_idle_s2idle, },
313 .desc = "MWAIT 0x58",
314 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
316 .target_residency = 275,
317 .enter = &intel_idle,
318 .enter_s2idle = intel_idle_s2idle, },
321 .desc = "MWAIT 0x52",
322 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
324 .target_residency = 560,
325 .enter = &intel_idle,
326 .enter_s2idle = intel_idle_s2idle, },
329 .desc = "MWAIT 0x60",
330 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
331 .exit_latency = 1200,
332 .target_residency = 4000,
333 .enter = &intel_idle,
334 .enter_s2idle = intel_idle_s2idle, },
337 .desc = "MWAIT 0x64",
338 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
339 .exit_latency = 10000,
340 .target_residency = 20000,
341 .enter = &intel_idle,
342 .enter_s2idle = intel_idle_s2idle, },
347 static struct cpuidle_state ivb_cstates[] __initdata = {
350 .desc = "MWAIT 0x00",
351 .flags = MWAIT2flg(0x00),
353 .target_residency = 1,
354 .enter = &intel_idle,
355 .enter_s2idle = intel_idle_s2idle, },
358 .desc = "MWAIT 0x01",
359 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
361 .target_residency = 20,
362 .enter = &intel_idle,
363 .enter_s2idle = intel_idle_s2idle, },
366 .desc = "MWAIT 0x10",
367 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
369 .target_residency = 156,
370 .enter = &intel_idle,
371 .enter_s2idle = intel_idle_s2idle, },
374 .desc = "MWAIT 0x20",
375 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
377 .target_residency = 300,
378 .enter = &intel_idle,
379 .enter_s2idle = intel_idle_s2idle, },
382 .desc = "MWAIT 0x30",
383 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
385 .target_residency = 300,
386 .enter = &intel_idle,
387 .enter_s2idle = intel_idle_s2idle, },
392 static struct cpuidle_state ivt_cstates[] __initdata = {
395 .desc = "MWAIT 0x00",
396 .flags = MWAIT2flg(0x00),
398 .target_residency = 1,
399 .enter = &intel_idle,
400 .enter_s2idle = intel_idle_s2idle, },
403 .desc = "MWAIT 0x01",
404 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
406 .target_residency = 80,
407 .enter = &intel_idle,
408 .enter_s2idle = intel_idle_s2idle, },
411 .desc = "MWAIT 0x10",
412 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
414 .target_residency = 156,
415 .enter = &intel_idle,
416 .enter_s2idle = intel_idle_s2idle, },
419 .desc = "MWAIT 0x20",
420 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
422 .target_residency = 300,
423 .enter = &intel_idle,
424 .enter_s2idle = intel_idle_s2idle, },
429 static struct cpuidle_state ivt_cstates_4s[] __initdata = {
432 .desc = "MWAIT 0x00",
433 .flags = MWAIT2flg(0x00),
435 .target_residency = 1,
436 .enter = &intel_idle,
437 .enter_s2idle = intel_idle_s2idle, },
440 .desc = "MWAIT 0x01",
441 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
443 .target_residency = 250,
444 .enter = &intel_idle,
445 .enter_s2idle = intel_idle_s2idle, },
448 .desc = "MWAIT 0x10",
449 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
451 .target_residency = 300,
452 .enter = &intel_idle,
453 .enter_s2idle = intel_idle_s2idle, },
456 .desc = "MWAIT 0x20",
457 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
459 .target_residency = 400,
460 .enter = &intel_idle,
461 .enter_s2idle = intel_idle_s2idle, },
466 static struct cpuidle_state ivt_cstates_8s[] __initdata = {
469 .desc = "MWAIT 0x00",
470 .flags = MWAIT2flg(0x00),
472 .target_residency = 1,
473 .enter = &intel_idle,
474 .enter_s2idle = intel_idle_s2idle, },
477 .desc = "MWAIT 0x01",
478 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
480 .target_residency = 500,
481 .enter = &intel_idle,
482 .enter_s2idle = intel_idle_s2idle, },
485 .desc = "MWAIT 0x10",
486 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
488 .target_residency = 600,
489 .enter = &intel_idle,
490 .enter_s2idle = intel_idle_s2idle, },
493 .desc = "MWAIT 0x20",
494 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
496 .target_residency = 700,
497 .enter = &intel_idle,
498 .enter_s2idle = intel_idle_s2idle, },
503 static struct cpuidle_state hsw_cstates[] __initdata = {
506 .desc = "MWAIT 0x00",
507 .flags = MWAIT2flg(0x00),
509 .target_residency = 2,
510 .enter = &intel_idle,
511 .enter_s2idle = intel_idle_s2idle, },
514 .desc = "MWAIT 0x01",
515 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
517 .target_residency = 20,
518 .enter = &intel_idle,
519 .enter_s2idle = intel_idle_s2idle, },
522 .desc = "MWAIT 0x10",
523 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
525 .target_residency = 100,
526 .enter = &intel_idle,
527 .enter_s2idle = intel_idle_s2idle, },
530 .desc = "MWAIT 0x20",
531 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
533 .target_residency = 400,
534 .enter = &intel_idle,
535 .enter_s2idle = intel_idle_s2idle, },
538 .desc = "MWAIT 0x32",
539 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
541 .target_residency = 500,
542 .enter = &intel_idle,
543 .enter_s2idle = intel_idle_s2idle, },
546 .desc = "MWAIT 0x40",
547 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
549 .target_residency = 900,
550 .enter = &intel_idle,
551 .enter_s2idle = intel_idle_s2idle, },
554 .desc = "MWAIT 0x50",
555 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
557 .target_residency = 1800,
558 .enter = &intel_idle,
559 .enter_s2idle = intel_idle_s2idle, },
562 .desc = "MWAIT 0x60",
563 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
564 .exit_latency = 2600,
565 .target_residency = 7700,
566 .enter = &intel_idle,
567 .enter_s2idle = intel_idle_s2idle, },
571 static struct cpuidle_state bdw_cstates[] __initdata = {
574 .desc = "MWAIT 0x00",
575 .flags = MWAIT2flg(0x00),
577 .target_residency = 2,
578 .enter = &intel_idle,
579 .enter_s2idle = intel_idle_s2idle, },
582 .desc = "MWAIT 0x01",
583 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
585 .target_residency = 20,
586 .enter = &intel_idle,
587 .enter_s2idle = intel_idle_s2idle, },
590 .desc = "MWAIT 0x10",
591 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
593 .target_residency = 100,
594 .enter = &intel_idle,
595 .enter_s2idle = intel_idle_s2idle, },
598 .desc = "MWAIT 0x20",
599 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
601 .target_residency = 400,
602 .enter = &intel_idle,
603 .enter_s2idle = intel_idle_s2idle, },
606 .desc = "MWAIT 0x32",
607 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
609 .target_residency = 500,
610 .enter = &intel_idle,
611 .enter_s2idle = intel_idle_s2idle, },
614 .desc = "MWAIT 0x40",
615 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
617 .target_residency = 900,
618 .enter = &intel_idle,
619 .enter_s2idle = intel_idle_s2idle, },
622 .desc = "MWAIT 0x50",
623 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
625 .target_residency = 1800,
626 .enter = &intel_idle,
627 .enter_s2idle = intel_idle_s2idle, },
630 .desc = "MWAIT 0x60",
631 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
632 .exit_latency = 2600,
633 .target_residency = 7700,
634 .enter = &intel_idle,
635 .enter_s2idle = intel_idle_s2idle, },
640 static struct cpuidle_state skl_cstates[] __initdata = {
643 .desc = "MWAIT 0x00",
644 .flags = MWAIT2flg(0x00),
646 .target_residency = 2,
647 .enter = &intel_idle,
648 .enter_s2idle = intel_idle_s2idle, },
651 .desc = "MWAIT 0x01",
652 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
654 .target_residency = 20,
655 .enter = &intel_idle,
656 .enter_s2idle = intel_idle_s2idle, },
659 .desc = "MWAIT 0x10",
660 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
662 .target_residency = 100,
663 .enter = &intel_idle,
664 .enter_s2idle = intel_idle_s2idle, },
667 .desc = "MWAIT 0x20",
668 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
670 .target_residency = 200,
671 .enter = &intel_idle,
672 .enter_s2idle = intel_idle_s2idle, },
675 .desc = "MWAIT 0x33",
676 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
678 .target_residency = 800,
679 .enter = &intel_idle,
680 .enter_s2idle = intel_idle_s2idle, },
683 .desc = "MWAIT 0x40",
684 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
686 .target_residency = 800,
687 .enter = &intel_idle,
688 .enter_s2idle = intel_idle_s2idle, },
691 .desc = "MWAIT 0x50",
692 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
694 .target_residency = 5000,
695 .enter = &intel_idle,
696 .enter_s2idle = intel_idle_s2idle, },
699 .desc = "MWAIT 0x60",
700 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
702 .target_residency = 5000,
703 .enter = &intel_idle,
704 .enter_s2idle = intel_idle_s2idle, },
709 static struct cpuidle_state skx_cstates[] __initdata = {
712 .desc = "MWAIT 0x00",
713 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE,
715 .target_residency = 2,
716 .enter = &intel_idle,
717 .enter_s2idle = intel_idle_s2idle, },
720 .desc = "MWAIT 0x01",
721 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
723 .target_residency = 20,
724 .enter = &intel_idle,
725 .enter_s2idle = intel_idle_s2idle, },
728 .desc = "MWAIT 0x20",
729 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
731 .target_residency = 600,
732 .enter = &intel_idle,
733 .enter_s2idle = intel_idle_s2idle, },
738 static struct cpuidle_state icx_cstates[] __initdata = {
741 .desc = "MWAIT 0x00",
742 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_IRQ_ENABLE,
744 .target_residency = 1,
745 .enter = &intel_idle,
746 .enter_s2idle = intel_idle_s2idle, },
749 .desc = "MWAIT 0x01",
750 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
752 .target_residency = 4,
753 .enter = &intel_idle,
754 .enter_s2idle = intel_idle_s2idle, },
757 .desc = "MWAIT 0x20",
758 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
760 .target_residency = 600,
761 .enter = &intel_idle,
762 .enter_s2idle = intel_idle_s2idle, },
768 * On Sapphire Rapids Xeon C1 has to be disabled if C1E is enabled, and vice
769 * versa. On SPR C1E is enabled only if "C1E promotion" bit is set in
770 * MSR_IA32_POWER_CTL. But in this case there effectively no C1, because C1
771 * requests are promoted to C1E. If the "C1E promotion" bit is cleared, then
772 * both C1 and C1E requests end up with C1, so there is effectively no C1E.
774 * By default we enable C1 and disable C1E by marking it with
775 * 'CPUIDLE_FLAG_UNUSABLE'.
777 static struct cpuidle_state spr_cstates[] __initdata = {
780 .desc = "MWAIT 0x00",
781 .flags = MWAIT2flg(0x00),
783 .target_residency = 1,
784 .enter = &intel_idle,
785 .enter_s2idle = intel_idle_s2idle, },
788 .desc = "MWAIT 0x01",
789 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE |
790 CPUIDLE_FLAG_UNUSABLE,
792 .target_residency = 4,
793 .enter = &intel_idle,
794 .enter_s2idle = intel_idle_s2idle, },
797 .desc = "MWAIT 0x20",
798 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
800 .target_residency = 800,
801 .enter = &intel_idle,
802 .enter_s2idle = intel_idle_s2idle, },
807 static struct cpuidle_state atom_cstates[] __initdata = {
810 .desc = "MWAIT 0x00",
811 .flags = MWAIT2flg(0x00),
813 .target_residency = 20,
814 .enter = &intel_idle,
815 .enter_s2idle = intel_idle_s2idle, },
818 .desc = "MWAIT 0x10",
819 .flags = MWAIT2flg(0x10),
821 .target_residency = 80,
822 .enter = &intel_idle,
823 .enter_s2idle = intel_idle_s2idle, },
826 .desc = "MWAIT 0x30",
827 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
829 .target_residency = 400,
830 .enter = &intel_idle,
831 .enter_s2idle = intel_idle_s2idle, },
834 .desc = "MWAIT 0x52",
835 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
837 .target_residency = 560,
838 .enter = &intel_idle,
839 .enter_s2idle = intel_idle_s2idle, },
843 static struct cpuidle_state tangier_cstates[] __initdata = {
846 .desc = "MWAIT 0x00",
847 .flags = MWAIT2flg(0x00),
849 .target_residency = 4,
850 .enter = &intel_idle,
851 .enter_s2idle = intel_idle_s2idle, },
854 .desc = "MWAIT 0x30",
855 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
857 .target_residency = 400,
858 .enter = &intel_idle,
859 .enter_s2idle = intel_idle_s2idle, },
862 .desc = "MWAIT 0x52",
863 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
865 .target_residency = 560,
866 .enter = &intel_idle,
867 .enter_s2idle = intel_idle_s2idle, },
870 .desc = "MWAIT 0x60",
871 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
872 .exit_latency = 1200,
873 .target_residency = 4000,
874 .enter = &intel_idle,
875 .enter_s2idle = intel_idle_s2idle, },
878 .desc = "MWAIT 0x64",
879 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
880 .exit_latency = 10000,
881 .target_residency = 20000,
882 .enter = &intel_idle,
883 .enter_s2idle = intel_idle_s2idle, },
887 static struct cpuidle_state avn_cstates[] __initdata = {
890 .desc = "MWAIT 0x00",
891 .flags = MWAIT2flg(0x00),
893 .target_residency = 2,
894 .enter = &intel_idle,
895 .enter_s2idle = intel_idle_s2idle, },
898 .desc = "MWAIT 0x51",
899 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
901 .target_residency = 45,
902 .enter = &intel_idle,
903 .enter_s2idle = intel_idle_s2idle, },
907 static struct cpuidle_state knl_cstates[] __initdata = {
910 .desc = "MWAIT 0x00",
911 .flags = MWAIT2flg(0x00),
913 .target_residency = 2,
914 .enter = &intel_idle,
915 .enter_s2idle = intel_idle_s2idle },
918 .desc = "MWAIT 0x10",
919 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
921 .target_residency = 500,
922 .enter = &intel_idle,
923 .enter_s2idle = intel_idle_s2idle },
928 static struct cpuidle_state bxt_cstates[] __initdata = {
931 .desc = "MWAIT 0x00",
932 .flags = MWAIT2flg(0x00),
934 .target_residency = 2,
935 .enter = &intel_idle,
936 .enter_s2idle = intel_idle_s2idle, },
939 .desc = "MWAIT 0x01",
940 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
942 .target_residency = 20,
943 .enter = &intel_idle,
944 .enter_s2idle = intel_idle_s2idle, },
947 .desc = "MWAIT 0x20",
948 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
950 .target_residency = 133,
951 .enter = &intel_idle,
952 .enter_s2idle = intel_idle_s2idle, },
955 .desc = "MWAIT 0x31",
956 .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
958 .target_residency = 155,
959 .enter = &intel_idle,
960 .enter_s2idle = intel_idle_s2idle, },
963 .desc = "MWAIT 0x40",
964 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
965 .exit_latency = 1000,
966 .target_residency = 1000,
967 .enter = &intel_idle,
968 .enter_s2idle = intel_idle_s2idle, },
971 .desc = "MWAIT 0x50",
972 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
973 .exit_latency = 2000,
974 .target_residency = 2000,
975 .enter = &intel_idle,
976 .enter_s2idle = intel_idle_s2idle, },
979 .desc = "MWAIT 0x60",
980 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
981 .exit_latency = 10000,
982 .target_residency = 10000,
983 .enter = &intel_idle,
984 .enter_s2idle = intel_idle_s2idle, },
989 static struct cpuidle_state dnv_cstates[] __initdata = {
992 .desc = "MWAIT 0x00",
993 .flags = MWAIT2flg(0x00),
995 .target_residency = 2,
996 .enter = &intel_idle,
997 .enter_s2idle = intel_idle_s2idle, },
1000 .desc = "MWAIT 0x01",
1001 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
1003 .target_residency = 20,
1004 .enter = &intel_idle,
1005 .enter_s2idle = intel_idle_s2idle, },
1008 .desc = "MWAIT 0x20",
1009 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
1011 .target_residency = 500,
1012 .enter = &intel_idle,
1013 .enter_s2idle = intel_idle_s2idle, },
1019 * Note, depending on HW and FW revision, SnowRidge SoC may or may not support
1020 * C6, and this is indicated in the CPUID mwait leaf.
1022 static struct cpuidle_state snr_cstates[] __initdata = {
1025 .desc = "MWAIT 0x00",
1026 .flags = MWAIT2flg(0x00),
1028 .target_residency = 2,
1029 .enter = &intel_idle,
1030 .enter_s2idle = intel_idle_s2idle, },
1033 .desc = "MWAIT 0x01",
1034 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
1036 .target_residency = 25,
1037 .enter = &intel_idle,
1038 .enter_s2idle = intel_idle_s2idle, },
1041 .desc = "MWAIT 0x20",
1042 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
1043 .exit_latency = 130,
1044 .target_residency = 500,
1045 .enter = &intel_idle,
1046 .enter_s2idle = intel_idle_s2idle, },
1051 static const struct idle_cpu idle_cpu_nehalem __initconst = {
1052 .state_table = nehalem_cstates,
1053 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
1054 .disable_promotion_to_c1e = true,
1057 static const struct idle_cpu idle_cpu_nhx __initconst = {
1058 .state_table = nehalem_cstates,
1059 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
1060 .disable_promotion_to_c1e = true,
1064 static const struct idle_cpu idle_cpu_atom __initconst = {
1065 .state_table = atom_cstates,
1068 static const struct idle_cpu idle_cpu_tangier __initconst = {
1069 .state_table = tangier_cstates,
1072 static const struct idle_cpu idle_cpu_lincroft __initconst = {
1073 .state_table = atom_cstates,
1074 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
1077 static const struct idle_cpu idle_cpu_snb __initconst = {
1078 .state_table = snb_cstates,
1079 .disable_promotion_to_c1e = true,
1082 static const struct idle_cpu idle_cpu_snx __initconst = {
1083 .state_table = snb_cstates,
1084 .disable_promotion_to_c1e = true,
1088 static const struct idle_cpu idle_cpu_byt __initconst = {
1089 .state_table = byt_cstates,
1090 .disable_promotion_to_c1e = true,
1091 .byt_auto_demotion_disable_flag = true,
1094 static const struct idle_cpu idle_cpu_cht __initconst = {
1095 .state_table = cht_cstates,
1096 .disable_promotion_to_c1e = true,
1097 .byt_auto_demotion_disable_flag = true,
1100 static const struct idle_cpu idle_cpu_ivb __initconst = {
1101 .state_table = ivb_cstates,
1102 .disable_promotion_to_c1e = true,
1105 static const struct idle_cpu idle_cpu_ivt __initconst = {
1106 .state_table = ivt_cstates,
1107 .disable_promotion_to_c1e = true,
1111 static const struct idle_cpu idle_cpu_hsw __initconst = {
1112 .state_table = hsw_cstates,
1113 .disable_promotion_to_c1e = true,
1116 static const struct idle_cpu idle_cpu_hsx __initconst = {
1117 .state_table = hsw_cstates,
1118 .disable_promotion_to_c1e = true,
1122 static const struct idle_cpu idle_cpu_bdw __initconst = {
1123 .state_table = bdw_cstates,
1124 .disable_promotion_to_c1e = true,
1127 static const struct idle_cpu idle_cpu_bdx __initconst = {
1128 .state_table = bdw_cstates,
1129 .disable_promotion_to_c1e = true,
1133 static const struct idle_cpu idle_cpu_skl __initconst = {
1134 .state_table = skl_cstates,
1135 .disable_promotion_to_c1e = true,
1138 static const struct idle_cpu idle_cpu_skx __initconst = {
1139 .state_table = skx_cstates,
1140 .disable_promotion_to_c1e = true,
1144 static const struct idle_cpu idle_cpu_icx __initconst = {
1145 .state_table = icx_cstates,
1146 .disable_promotion_to_c1e = true,
1150 static const struct idle_cpu idle_cpu_spr __initconst = {
1151 .state_table = spr_cstates,
1152 .disable_promotion_to_c1e = true,
1156 static const struct idle_cpu idle_cpu_avn __initconst = {
1157 .state_table = avn_cstates,
1158 .disable_promotion_to_c1e = true,
1162 static const struct idle_cpu idle_cpu_knl __initconst = {
1163 .state_table = knl_cstates,
1167 static const struct idle_cpu idle_cpu_bxt __initconst = {
1168 .state_table = bxt_cstates,
1169 .disable_promotion_to_c1e = true,
1172 static const struct idle_cpu idle_cpu_dnv __initconst = {
1173 .state_table = dnv_cstates,
1174 .disable_promotion_to_c1e = true,
1178 static const struct idle_cpu idle_cpu_snr __initconst = {
1179 .state_table = snr_cstates,
1180 .disable_promotion_to_c1e = true,
1184 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
1185 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &idle_cpu_nhx),
1186 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &idle_cpu_nehalem),
1187 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_G, &idle_cpu_nehalem),
1188 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE, &idle_cpu_nehalem),
1189 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP, &idle_cpu_nhx),
1190 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX, &idle_cpu_nhx),
1191 X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL, &idle_cpu_atom),
1192 X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL_MID, &idle_cpu_lincroft),
1193 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX, &idle_cpu_nhx),
1194 X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &idle_cpu_snb),
1195 X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &idle_cpu_snx),
1196 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL, &idle_cpu_atom),
1197 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &idle_cpu_byt),
1198 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &idle_cpu_tangier),
1199 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &idle_cpu_cht),
1200 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &idle_cpu_ivb),
1201 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &idle_cpu_ivt),
1202 X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &idle_cpu_hsw),
1203 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &idle_cpu_hsx),
1204 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &idle_cpu_hsw),
1205 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &idle_cpu_hsw),
1206 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, &idle_cpu_avn),
1207 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &idle_cpu_bdw),
1208 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &idle_cpu_bdw),
1209 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &idle_cpu_bdx),
1210 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &idle_cpu_bdx),
1211 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &idle_cpu_skl),
1212 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &idle_cpu_skl),
1213 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &idle_cpu_skl),
1214 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &idle_cpu_skl),
1215 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &idle_cpu_skx),
1216 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &idle_cpu_icx),
1217 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &idle_cpu_icx),
1218 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &idle_cpu_spr),
1219 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl),
1220 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl),
1221 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &idle_cpu_bxt),
1222 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &idle_cpu_bxt),
1223 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &idle_cpu_dnv),
1224 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &idle_cpu_snr),
1228 static const struct x86_cpu_id intel_mwait_ids[] __initconst = {
1229 X86_MATCH_VENDOR_FAM_FEATURE(INTEL, 6, X86_FEATURE_MWAIT, NULL),
1233 static bool __init intel_idle_max_cstate_reached(int cstate)
1235 if (cstate + 1 > max_cstate) {
1236 pr_info("max_cstate %d reached\n", max_cstate);
1242 static bool __init intel_idle_state_needs_timer_stop(struct cpuidle_state *state)
1244 unsigned long eax = flg2MWAIT(state->flags);
1246 if (boot_cpu_has(X86_FEATURE_ARAT))
1250 * Switch over to one-shot tick broadcast if the target C-state
1251 * is deeper than C1.
1253 return !!((eax >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK);
1256 #ifdef CONFIG_ACPI_PROCESSOR_CSTATE
1257 #include <acpi/processor.h>
1259 static bool no_acpi __read_mostly;
1260 module_param(no_acpi, bool, 0444);
1261 MODULE_PARM_DESC(no_acpi, "Do not use ACPI _CST for building the idle states list");
1263 static bool force_use_acpi __read_mostly; /* No effect if no_acpi is set. */
1264 module_param_named(use_acpi, force_use_acpi, bool, 0444);
1265 MODULE_PARM_DESC(use_acpi, "Use ACPI _CST for building the idle states list");
1267 static struct acpi_processor_power acpi_state_table __initdata;
1270 * intel_idle_cst_usable - Check if the _CST information can be used.
1272 * Check if all of the C-states listed by _CST in the max_cstate range are
1273 * ACPI_CSTATE_FFH, which means that they should be entered via MWAIT.
1275 static bool __init intel_idle_cst_usable(void)
1279 limit = min_t(int, min_t(int, CPUIDLE_STATE_MAX, max_cstate + 1),
1280 acpi_state_table.count);
1282 for (cstate = 1; cstate < limit; cstate++) {
1283 struct acpi_processor_cx *cx = &acpi_state_table.states[cstate];
1285 if (cx->entry_method != ACPI_CSTATE_FFH)
1292 static bool __init intel_idle_acpi_cst_extract(void)
1297 pr_debug("Not allowed to use ACPI _CST\n");
1301 for_each_possible_cpu(cpu) {
1302 struct acpi_processor *pr = per_cpu(processors, cpu);
1307 if (acpi_processor_evaluate_cst(pr->handle, cpu, &acpi_state_table))
1310 acpi_state_table.count++;
1312 if (!intel_idle_cst_usable())
1315 if (!acpi_processor_claim_cst_control())
1321 acpi_state_table.count = 0;
1322 pr_debug("ACPI _CST not found or not usable\n");
1326 static void __init intel_idle_init_cstates_acpi(struct cpuidle_driver *drv)
1328 int cstate, limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1331 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1332 * the interesting states are ACPI_CSTATE_FFH.
1334 for (cstate = 1; cstate < limit; cstate++) {
1335 struct acpi_processor_cx *cx;
1336 struct cpuidle_state *state;
1338 if (intel_idle_max_cstate_reached(cstate - 1))
1341 cx = &acpi_state_table.states[cstate];
1343 state = &drv->states[drv->state_count++];
1345 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d_ACPI", cstate);
1346 strlcpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1347 state->exit_latency = cx->latency;
1349 * For C1-type C-states use the same number for both the exit
1350 * latency and target residency, because that is the case for
1351 * C1 in the majority of the static C-states tables above.
1352 * For the other types of C-states, however, set the target
1353 * residency to 3 times the exit latency which should lead to
1354 * a reasonable balance between energy-efficiency and
1355 * performance in the majority of interesting cases.
1357 state->target_residency = cx->latency;
1358 if (cx->type > ACPI_STATE_C1)
1359 state->target_residency *= 3;
1361 state->flags = MWAIT2flg(cx->address);
1362 if (cx->type > ACPI_STATE_C2)
1363 state->flags |= CPUIDLE_FLAG_TLB_FLUSHED;
1365 if (disabled_states_mask & BIT(cstate))
1366 state->flags |= CPUIDLE_FLAG_OFF;
1368 if (intel_idle_state_needs_timer_stop(state))
1369 state->flags |= CPUIDLE_FLAG_TIMER_STOP;
1371 state->enter = intel_idle;
1372 state->enter_s2idle = intel_idle_s2idle;
1376 static bool __init intel_idle_off_by_default(u32 mwait_hint)
1381 * If there are no _CST C-states, do not disable any C-states by
1384 if (!acpi_state_table.count)
1387 limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1389 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1390 * the interesting states are ACPI_CSTATE_FFH.
1392 for (cstate = 1; cstate < limit; cstate++) {
1393 if (acpi_state_table.states[cstate].address == mwait_hint)
1398 #else /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1399 #define force_use_acpi (false)
1401 static inline bool intel_idle_acpi_cst_extract(void) { return false; }
1402 static inline void intel_idle_init_cstates_acpi(struct cpuidle_driver *drv) { }
1403 static inline bool intel_idle_off_by_default(u32 mwait_hint) { return false; }
1404 #endif /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1407 * ivt_idle_state_table_update - Tune the idle states table for Ivy Town.
1409 * Tune IVT multi-socket targets.
1410 * Assumption: num_sockets == (max_package_num + 1).
1412 static void __init ivt_idle_state_table_update(void)
1414 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
1415 int cpu, package_num, num_sockets = 1;
1417 for_each_online_cpu(cpu) {
1418 package_num = topology_physical_package_id(cpu);
1419 if (package_num + 1 > num_sockets) {
1420 num_sockets = package_num + 1;
1422 if (num_sockets > 4) {
1423 cpuidle_state_table = ivt_cstates_8s;
1429 if (num_sockets > 2)
1430 cpuidle_state_table = ivt_cstates_4s;
1432 /* else, 1 and 2 socket systems use default ivt_cstates */
1436 * irtl_2_usec - IRTL to microseconds conversion.
1437 * @irtl: IRTL MSR value.
1439 * Translate the IRTL (Interrupt Response Time Limit) MSR value to microseconds.
1441 static unsigned long long __init irtl_2_usec(unsigned long long irtl)
1443 static const unsigned int irtl_ns_units[] __initconst = {
1444 1, 32, 1024, 32768, 1048576, 33554432, 0, 0
1446 unsigned long long ns;
1451 ns = irtl_ns_units[(irtl >> 10) & 0x7];
1453 return div_u64((irtl & 0x3FF) * ns, NSEC_PER_USEC);
1457 * bxt_idle_state_table_update - Fix up the Broxton idle states table.
1459 * On BXT, trust the IRTL (Interrupt Response Time Limit) MSR to show the
1460 * definitive maximum latency and use the same value for target_residency.
1462 static void __init bxt_idle_state_table_update(void)
1464 unsigned long long msr;
1467 rdmsrl(MSR_PKGC6_IRTL, msr);
1468 usec = irtl_2_usec(msr);
1470 bxt_cstates[2].exit_latency = usec;
1471 bxt_cstates[2].target_residency = usec;
1474 rdmsrl(MSR_PKGC7_IRTL, msr);
1475 usec = irtl_2_usec(msr);
1477 bxt_cstates[3].exit_latency = usec;
1478 bxt_cstates[3].target_residency = usec;
1481 rdmsrl(MSR_PKGC8_IRTL, msr);
1482 usec = irtl_2_usec(msr);
1484 bxt_cstates[4].exit_latency = usec;
1485 bxt_cstates[4].target_residency = usec;
1488 rdmsrl(MSR_PKGC9_IRTL, msr);
1489 usec = irtl_2_usec(msr);
1491 bxt_cstates[5].exit_latency = usec;
1492 bxt_cstates[5].target_residency = usec;
1495 rdmsrl(MSR_PKGC10_IRTL, msr);
1496 usec = irtl_2_usec(msr);
1498 bxt_cstates[6].exit_latency = usec;
1499 bxt_cstates[6].target_residency = usec;
1505 * sklh_idle_state_table_update - Fix up the Sky Lake idle states table.
1507 * On SKL-H (model 0x5e) skip C8 and C9 if C10 is enabled and SGX disabled.
1509 static void __init sklh_idle_state_table_update(void)
1511 unsigned long long msr;
1512 unsigned int eax, ebx, ecx, edx;
1515 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1516 if (max_cstate <= 7)
1519 /* if PC10 not present in CPUID.MWAIT.EDX */
1520 if ((mwait_substates & (0xF << 28)) == 0)
1523 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1525 /* PC10 is not enabled in PKG C-state limit */
1526 if ((msr & 0xF) != 8)
1530 cpuid(7, &eax, &ebx, &ecx, &edx);
1532 /* if SGX is present */
1533 if (ebx & (1 << 2)) {
1535 rdmsrl(MSR_IA32_FEAT_CTL, msr);
1537 /* if SGX is enabled */
1538 if (msr & (1 << 18))
1542 skl_cstates[5].flags |= CPUIDLE_FLAG_UNUSABLE; /* C8-SKL */
1543 skl_cstates[6].flags |= CPUIDLE_FLAG_UNUSABLE; /* C9-SKL */
1547 * skx_idle_state_table_update - Adjust the Sky Lake/Cascade Lake
1548 * idle states table.
1550 static void __init skx_idle_state_table_update(void)
1552 unsigned long long msr;
1554 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1557 * 000b: C0/C1 (no package C-state support)
1559 * 010b: C6 (non-retention)
1560 * 011b: C6 (retention)
1561 * 111b: No Package C state limits.
1563 if ((msr & 0x7) < 2) {
1565 * Uses the CC6 + PC0 latency and 3 times of
1566 * latency for target_residency if the PC6
1567 * is disabled in BIOS. This is consistent
1568 * with how intel_idle driver uses _CST
1569 * to set the target_residency.
1571 skx_cstates[2].exit_latency = 92;
1572 skx_cstates[2].target_residency = 276;
1577 * spr_idle_state_table_update - Adjust Sapphire Rapids idle states table.
1579 static void __init spr_idle_state_table_update(void)
1581 unsigned long long msr;
1583 /* Check if user prefers C1E over C1. */
1584 if ((preferred_states_mask & BIT(2)) &&
1585 !(preferred_states_mask & BIT(1))) {
1586 /* Disable C1 and enable C1E. */
1587 spr_cstates[0].flags |= CPUIDLE_FLAG_UNUSABLE;
1588 spr_cstates[1].flags &= ~CPUIDLE_FLAG_UNUSABLE;
1590 /* Enable C1E using the "C1E promotion" bit. */
1591 c1e_promotion = C1E_PROMOTION_ENABLE;
1595 * By default, the C6 state assumes the worst-case scenario of package
1596 * C6. However, if PC6 is disabled, we update the numbers to match
1599 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1601 /* Limit value 2 and above allow for PC6. */
1602 if ((msr & 0x7) < 2) {
1603 spr_cstates[2].exit_latency = 190;
1604 spr_cstates[2].target_residency = 600;
1608 static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)
1610 unsigned int mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint) + 1;
1611 unsigned int num_substates = (mwait_substates >> mwait_cstate * 4) &
1612 MWAIT_SUBSTATE_MASK;
1614 /* Ignore the C-state if there are NO sub-states in CPUID for it. */
1615 if (num_substates == 0)
1618 if (mwait_cstate > 2 && !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1619 mark_tsc_unstable("TSC halts in idle states deeper than C2");
1624 static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
1628 switch (boot_cpu_data.x86_model) {
1629 case INTEL_FAM6_IVYBRIDGE_X:
1630 ivt_idle_state_table_update();
1632 case INTEL_FAM6_ATOM_GOLDMONT:
1633 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
1634 bxt_idle_state_table_update();
1636 case INTEL_FAM6_SKYLAKE:
1637 sklh_idle_state_table_update();
1639 case INTEL_FAM6_SKYLAKE_X:
1640 skx_idle_state_table_update();
1642 case INTEL_FAM6_SAPPHIRERAPIDS_X:
1643 spr_idle_state_table_update();
1647 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
1648 unsigned int mwait_hint;
1650 if (intel_idle_max_cstate_reached(cstate))
1653 if (!cpuidle_state_table[cstate].enter &&
1654 !cpuidle_state_table[cstate].enter_s2idle)
1657 /* If marked as unusable, skip this state. */
1658 if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_UNUSABLE) {
1659 pr_debug("state %s is disabled\n",
1660 cpuidle_state_table[cstate].name);
1664 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
1665 if (!intel_idle_verify_cstate(mwait_hint))
1668 /* Structure copy. */
1669 drv->states[drv->state_count] = cpuidle_state_table[cstate];
1671 if ((disabled_states_mask & BIT(drv->state_count)) ||
1672 ((icpu->use_acpi || force_use_acpi) &&
1673 intel_idle_off_by_default(mwait_hint) &&
1674 !(cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_ALWAYS_ENABLE)))
1675 drv->states[drv->state_count].flags |= CPUIDLE_FLAG_OFF;
1677 if (intel_idle_state_needs_timer_stop(&drv->states[drv->state_count]))
1678 drv->states[drv->state_count].flags |= CPUIDLE_FLAG_TIMER_STOP;
1683 if (icpu->byt_auto_demotion_disable_flag) {
1684 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1685 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1690 * intel_idle_cpuidle_driver_init - Create the list of available idle states.
1691 * @drv: cpuidle driver structure to initialize.
1693 static void __init intel_idle_cpuidle_driver_init(struct cpuidle_driver *drv)
1695 cpuidle_poll_state_init(drv);
1697 if (disabled_states_mask & BIT(0))
1698 drv->states[0].flags |= CPUIDLE_FLAG_OFF;
1700 drv->state_count = 1;
1703 intel_idle_init_cstates_icpu(drv);
1705 intel_idle_init_cstates_acpi(drv);
1708 static void auto_demotion_disable(void)
1710 unsigned long long msr_bits;
1712 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1713 msr_bits &= ~auto_demotion_disable_flags;
1714 wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1717 static void c1e_promotion_enable(void)
1719 unsigned long long msr_bits;
1721 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
1723 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
1726 static void c1e_promotion_disable(void)
1728 unsigned long long msr_bits;
1730 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
1732 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
1736 * intel_idle_cpu_init - Register the target CPU with the cpuidle core.
1737 * @cpu: CPU to initialize.
1739 * Register a cpuidle device object for @cpu and update its MSRs in accordance
1740 * with the processor model flags.
1742 static int intel_idle_cpu_init(unsigned int cpu)
1744 struct cpuidle_device *dev;
1746 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1749 if (cpuidle_register_device(dev)) {
1750 pr_debug("cpuidle_register_device %d failed!\n", cpu);
1754 if (auto_demotion_disable_flags)
1755 auto_demotion_disable();
1757 if (c1e_promotion == C1E_PROMOTION_ENABLE)
1758 c1e_promotion_enable();
1759 else if (c1e_promotion == C1E_PROMOTION_DISABLE)
1760 c1e_promotion_disable();
1765 static int intel_idle_cpu_online(unsigned int cpu)
1767 struct cpuidle_device *dev;
1769 if (!boot_cpu_has(X86_FEATURE_ARAT))
1770 tick_broadcast_enable();
1773 * Some systems can hotplug a cpu at runtime after
1774 * the kernel has booted, we have to initialize the
1775 * driver in this case
1777 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1778 if (!dev->registered)
1779 return intel_idle_cpu_init(cpu);
1785 * intel_idle_cpuidle_devices_uninit - Unregister all cpuidle devices.
1787 static void __init intel_idle_cpuidle_devices_uninit(void)
1791 for_each_online_cpu(i)
1792 cpuidle_unregister_device(per_cpu_ptr(intel_idle_cpuidle_devices, i));
1795 static int __init intel_idle_init(void)
1797 const struct x86_cpu_id *id;
1798 unsigned int eax, ebx, ecx;
1801 /* Do not load intel_idle at all for now if idle= is passed */
1802 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1805 if (max_cstate == 0) {
1806 pr_debug("disabled\n");
1810 id = x86_match_cpu(intel_idle_ids);
1812 if (!boot_cpu_has(X86_FEATURE_MWAIT)) {
1813 pr_debug("Please enable MWAIT in BIOS SETUP\n");
1817 id = x86_match_cpu(intel_mwait_ids);
1822 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1825 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
1827 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
1828 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
1832 pr_debug("MWAIT substates: 0x%x\n", mwait_substates);
1834 icpu = (const struct idle_cpu *)id->driver_data;
1836 cpuidle_state_table = icpu->state_table;
1837 auto_demotion_disable_flags = icpu->auto_demotion_disable_flags;
1838 if (icpu->disable_promotion_to_c1e)
1839 c1e_promotion = C1E_PROMOTION_DISABLE;
1840 if (icpu->use_acpi || force_use_acpi)
1841 intel_idle_acpi_cst_extract();
1842 } else if (!intel_idle_acpi_cst_extract()) {
1846 pr_debug("v" INTEL_IDLE_VERSION " model 0x%X\n",
1847 boot_cpu_data.x86_model);
1849 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1850 if (!intel_idle_cpuidle_devices)
1853 intel_idle_cpuidle_driver_init(&intel_idle_driver);
1855 retval = cpuidle_register_driver(&intel_idle_driver);
1857 struct cpuidle_driver *drv = cpuidle_get_driver();
1858 printk(KERN_DEBUG pr_fmt("intel_idle yielding to %s\n"),
1859 drv ? drv->name : "none");
1860 goto init_driver_fail;
1863 retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online",
1864 intel_idle_cpu_online, NULL);
1868 pr_debug("Local APIC timer is reliable in %s\n",
1869 boot_cpu_has(X86_FEATURE_ARAT) ? "all C-states" : "C1");
1874 intel_idle_cpuidle_devices_uninit();
1875 cpuidle_unregister_driver(&intel_idle_driver);
1877 free_percpu(intel_idle_cpuidle_devices);
1881 device_initcall(intel_idle_init);
1884 * We are not really modular, but we used to support that. Meaning we also
1885 * support "intel_idle.max_cstate=..." at boot and also a read-only export of
1886 * it at /sys/module/intel_idle/parameters/max_cstate -- so using module_param
1887 * is the easiest way (currently) to continue doing that.
1889 module_param(max_cstate, int, 0444);
1891 * The positions of the bits that are set in this number are the indices of the
1892 * idle states to be disabled by default (as reflected by the names of the
1893 * corresponding idle state directories in sysfs, "state0", "state1" ...
1894 * "state<i>" ..., where <i> is the index of the given state).
1896 module_param_named(states_off, disabled_states_mask, uint, 0444);
1897 MODULE_PARM_DESC(states_off, "Mask of disabled idle states");
1899 * Some platforms come with mutually exclusive C-states, so that if one is
1900 * enabled, the other C-states must not be used. Example: C1 and C1E on
1901 * Sapphire Rapids platform. This parameter allows for selecting the
1902 * preferred C-states among the groups of mutually exclusive C-states - the
1903 * selected C-states will be registered, the other C-states from the mutually
1904 * exclusive group won't be registered. If the platform has no mutually
1905 * exclusive C-states, this parameter has no effect.
1907 module_param_named(preferred_cstates, preferred_states_mask, uint, 0444);
1908 MODULE_PARM_DESC(preferred_cstates, "Mask of preferred idle states");