1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Sanechips Technology Co., Ltd.
4 * Copyright 2017 Linaro Ltd.
6 * Author: Baoyou Xie <baoyou.xie@linaro.org>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
17 #define REG_DEVADDR_H 0x0C
18 #define REG_DEVADDR_L 0x10
19 #define REG_CLK_DIV_FS 0x14
20 #define REG_CLK_DIV_HS 0x18
21 #define REG_WRCONF 0x1C
22 #define REG_RDCONF 0x20
27 #define I2C_MASTER BIT(0)
28 #define I2C_ADDR_MODE_TEN BIT(1)
29 #define I2C_IRQ_MSK_ENABLE BIT(3)
30 #define I2C_RW_READ BIT(4)
31 #define I2C_CMB_RW_EN BIT(5)
32 #define I2C_START BIT(6)
34 #define I2C_ADDR_LOW_MASK GENMASK(6, 0)
35 #define I2C_ADDR_LOW_SHIFT 0
36 #define I2C_ADDR_HI_MASK GENMASK(2, 0)
37 #define I2C_ADDR_HI_SHIFT 7
39 #define I2C_WFIFO_RESET BIT(7)
40 #define I2C_RFIFO_RESET BIT(7)
42 #define I2C_IRQ_ACK_CLEAR BIT(7)
43 #define I2C_INT_MASK GENMASK(6, 0)
45 #define I2C_TRANS_DONE BIT(0)
46 #define I2C_SR_EDEVICE BIT(1)
47 #define I2C_SR_EDATA BIT(2)
49 #define I2C_FIFO_MAX 16
51 #define I2C_TIMEOUT msecs_to_jiffies(1000)
53 #define DEV(i2c) ((i2c)->adap.dev.parent)
56 struct i2c_adapter adap;
58 struct completion complete;
60 void __iomem *reg_base;
69 static void zx2967_i2c_writel(struct zx2967_i2c *i2c,
70 u32 val, unsigned long reg)
72 writel_relaxed(val, i2c->reg_base + reg);
75 static u32 zx2967_i2c_readl(struct zx2967_i2c *i2c, unsigned long reg)
77 return readl_relaxed(i2c->reg_base + reg);
80 static void zx2967_i2c_writesb(struct zx2967_i2c *i2c,
81 void *data, unsigned long reg, int len)
83 writesb(i2c->reg_base + reg, data, len);
86 static void zx2967_i2c_readsb(struct zx2967_i2c *i2c,
87 void *data, unsigned long reg, int len)
89 readsb(i2c->reg_base + reg, data, len);
92 static void zx2967_i2c_start_ctrl(struct zx2967_i2c *i2c)
97 status = zx2967_i2c_readl(i2c, REG_STAT);
98 status |= I2C_IRQ_ACK_CLEAR;
99 zx2967_i2c_writel(i2c, status, REG_STAT);
101 ctl = zx2967_i2c_readl(i2c, REG_CMD);
106 ctl &= ~I2C_CMB_RW_EN;
108 zx2967_i2c_writel(i2c, ctl, REG_CMD);
111 static void zx2967_i2c_flush_fifos(struct zx2967_i2c *i2c)
118 val = I2C_RFIFO_RESET;
121 val = I2C_WFIFO_RESET;
124 val |= zx2967_i2c_readl(i2c, offset);
125 zx2967_i2c_writel(i2c, val, offset);
128 static int zx2967_i2c_empty_rx_fifo(struct zx2967_i2c *i2c, u32 size)
130 u8 val[I2C_FIFO_MAX] = {0};
133 if (size > I2C_FIFO_MAX) {
134 dev_err(DEV(i2c), "fifo size %d over the max value %d\n",
139 zx2967_i2c_readsb(i2c, val, REG_DATA, size);
140 for (i = 0; i < size; i++) {
141 *i2c->cur_trans++ = val[i];
150 static int zx2967_i2c_fill_tx_fifo(struct zx2967_i2c *i2c)
152 size_t residue = i2c->residue;
153 u8 *buf = i2c->cur_trans;
156 dev_err(DEV(i2c), "residue is %d\n", (int)residue);
160 if (residue <= I2C_FIFO_MAX) {
161 zx2967_i2c_writesb(i2c, buf, REG_DATA, residue);
163 /* Again update before writing to FIFO to make sure isr sees. */
165 i2c->cur_trans = NULL;
167 zx2967_i2c_writesb(i2c, buf, REG_DATA, I2C_FIFO_MAX);
168 i2c->residue -= I2C_FIFO_MAX;
169 i2c->cur_trans += I2C_FIFO_MAX;
177 static int zx2967_i2c_reset_hardware(struct zx2967_i2c *i2c)
182 val = I2C_MASTER | I2C_IRQ_MSK_ENABLE;
183 zx2967_i2c_writel(i2c, val, REG_CMD);
185 clk_div = clk_get_rate(i2c->clk) / i2c->clk_freq - 1;
186 zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_FS);
187 zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_HS);
189 zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_WRCONF);
190 zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_RDCONF);
191 zx2967_i2c_writel(i2c, 1, REG_RDCONF);
193 zx2967_i2c_flush_fifos(i2c);
198 static void zx2967_i2c_isr_clr(struct zx2967_i2c *i2c)
202 status = zx2967_i2c_readl(i2c, REG_STAT);
203 status |= I2C_IRQ_ACK_CLEAR;
204 zx2967_i2c_writel(i2c, status, REG_STAT);
207 static irqreturn_t zx2967_i2c_isr(int irq, void *dev_id)
210 struct zx2967_i2c *i2c = (struct zx2967_i2c *)dev_id;
212 status = zx2967_i2c_readl(i2c, REG_STAT) & I2C_INT_MASK;
213 zx2967_i2c_isr_clr(i2c);
215 if (status & I2C_SR_EDEVICE)
217 else if (status & I2C_SR_EDATA)
219 else if (status & I2C_TRANS_DONE)
224 complete(&i2c->complete);
229 static void zx2967_set_addr(struct zx2967_i2c *i2c, u16 addr)
233 val = (addr >> I2C_ADDR_LOW_SHIFT) & I2C_ADDR_LOW_MASK;
234 zx2967_i2c_writel(i2c, val, REG_DEVADDR_L);
236 val = (addr >> I2C_ADDR_HI_SHIFT) & I2C_ADDR_HI_MASK;
237 zx2967_i2c_writel(i2c, val, REG_DEVADDR_H);
239 val = zx2967_i2c_readl(i2c, REG_CMD) | I2C_ADDR_MODE_TEN;
241 val = zx2967_i2c_readl(i2c, REG_CMD) & ~I2C_ADDR_MODE_TEN;
242 zx2967_i2c_writel(i2c, val, REG_CMD);
245 static int zx2967_i2c_xfer_bytes(struct zx2967_i2c *i2c, u32 bytes)
247 unsigned long time_left;
248 int rd = i2c->msg_rd;
251 reinit_completion(&i2c->complete);
254 zx2967_i2c_writel(i2c, bytes - 1, REG_RDCONF);
256 ret = zx2967_i2c_fill_tx_fifo(i2c);
261 zx2967_i2c_start_ctrl(i2c);
263 time_left = wait_for_completion_timeout(&i2c->complete,
271 return rd ? zx2967_i2c_empty_rx_fifo(i2c, bytes) : 0;
274 static int zx2967_i2c_xfer_msg(struct zx2967_i2c *i2c,
280 zx2967_i2c_flush_fifos(i2c);
282 i2c->cur_trans = msg->buf;
283 i2c->residue = msg->len;
284 i2c->access_cnt = msg->len / I2C_FIFO_MAX;
285 i2c->msg_rd = msg->flags & I2C_M_RD;
287 for (i = 0; i < i2c->access_cnt; i++) {
288 ret = zx2967_i2c_xfer_bytes(i2c, I2C_FIFO_MAX);
293 if (i2c->residue > 0) {
294 ret = zx2967_i2c_xfer_bytes(i2c, i2c->residue);
305 static int zx2967_i2c_xfer(struct i2c_adapter *adap,
306 struct i2c_msg *msgs, int num)
308 struct zx2967_i2c *i2c = i2c_get_adapdata(adap);
312 zx2967_set_addr(i2c, msgs->addr);
314 for (i = 0; i < num; i++) {
315 ret = zx2967_i2c_xfer_msg(i2c, &msgs[i]);
324 zx2967_smbus_xfer_prepare(struct zx2967_i2c *i2c, u16 addr,
325 char read_write, u8 command, int size,
326 union i2c_smbus_data *data)
330 val = zx2967_i2c_readl(i2c, REG_RDCONF);
331 val |= I2C_RFIFO_RESET;
332 zx2967_i2c_writel(i2c, val, REG_RDCONF);
333 zx2967_set_addr(i2c, addr);
334 val = zx2967_i2c_readl(i2c, REG_CMD);
336 zx2967_i2c_writel(i2c, val, REG_CMD);
340 zx2967_i2c_writel(i2c, command, REG_DATA);
342 case I2C_SMBUS_BYTE_DATA:
343 zx2967_i2c_writel(i2c, command, REG_DATA);
344 if (read_write == I2C_SMBUS_WRITE)
345 zx2967_i2c_writel(i2c, data->byte, REG_DATA);
347 case I2C_SMBUS_WORD_DATA:
348 zx2967_i2c_writel(i2c, command, REG_DATA);
349 if (read_write == I2C_SMBUS_WRITE) {
350 zx2967_i2c_writel(i2c, (data->word >> 8), REG_DATA);
351 zx2967_i2c_writel(i2c, (data->word & 0xff),
358 static int zx2967_smbus_xfer_read(struct zx2967_i2c *i2c, int size,
359 union i2c_smbus_data *data)
361 unsigned long time_left;
365 reinit_completion(&i2c->complete);
367 val = zx2967_i2c_readl(i2c, REG_CMD);
368 val |= I2C_CMB_RW_EN;
369 zx2967_i2c_writel(i2c, val, REG_CMD);
371 val = zx2967_i2c_readl(i2c, REG_CMD);
373 zx2967_i2c_writel(i2c, val, REG_CMD);
375 time_left = wait_for_completion_timeout(&i2c->complete,
385 case I2C_SMBUS_BYTE_DATA:
386 val = zx2967_i2c_readl(i2c, REG_DATA);
389 case I2C_SMBUS_WORD_DATA:
390 case I2C_SMBUS_PROC_CALL:
391 buf[0] = zx2967_i2c_readl(i2c, REG_DATA);
392 buf[1] = zx2967_i2c_readl(i2c, REG_DATA);
393 data->word = (buf[0] << 8) | buf[1];
402 static int zx2967_smbus_xfer_write(struct zx2967_i2c *i2c)
404 unsigned long time_left;
407 reinit_completion(&i2c->complete);
408 val = zx2967_i2c_readl(i2c, REG_CMD);
410 zx2967_i2c_writel(i2c, val, REG_CMD);
412 time_left = wait_for_completion_timeout(&i2c->complete,
423 static int zx2967_smbus_xfer(struct i2c_adapter *adap, u16 addr,
424 unsigned short flags, char read_write,
425 u8 command, int size, union i2c_smbus_data *data)
427 struct zx2967_i2c *i2c = i2c_get_adapdata(adap);
429 if (size == I2C_SMBUS_QUICK)
430 read_write = I2C_SMBUS_WRITE;
433 case I2C_SMBUS_QUICK:
435 case I2C_SMBUS_BYTE_DATA:
436 case I2C_SMBUS_WORD_DATA:
437 zx2967_smbus_xfer_prepare(i2c, addr, read_write,
438 command, size, data);
444 if (read_write == I2C_SMBUS_READ)
445 return zx2967_smbus_xfer_read(i2c, size, data);
447 return zx2967_smbus_xfer_write(i2c);
450 static u32 zx2967_i2c_func(struct i2c_adapter *adap)
452 return I2C_FUNC_I2C |
453 I2C_FUNC_SMBUS_QUICK |
454 I2C_FUNC_SMBUS_BYTE |
455 I2C_FUNC_SMBUS_BYTE_DATA |
456 I2C_FUNC_SMBUS_WORD_DATA |
457 I2C_FUNC_SMBUS_BLOCK_DATA |
458 I2C_FUNC_SMBUS_PROC_CALL |
459 I2C_FUNC_SMBUS_I2C_BLOCK;
462 static int __maybe_unused zx2967_i2c_suspend(struct device *dev)
464 struct zx2967_i2c *i2c = dev_get_drvdata(dev);
466 i2c_mark_adapter_suspended(&i2c->adap);
467 clk_disable_unprepare(i2c->clk);
472 static int __maybe_unused zx2967_i2c_resume(struct device *dev)
474 struct zx2967_i2c *i2c = dev_get_drvdata(dev);
476 clk_prepare_enable(i2c->clk);
477 i2c_mark_adapter_resumed(&i2c->adap);
482 static SIMPLE_DEV_PM_OPS(zx2967_i2c_dev_pm_ops,
483 zx2967_i2c_suspend, zx2967_i2c_resume);
485 static const struct i2c_algorithm zx2967_i2c_algo = {
486 .master_xfer = zx2967_i2c_xfer,
487 .smbus_xfer = zx2967_smbus_xfer,
488 .functionality = zx2967_i2c_func,
491 static const struct i2c_adapter_quirks zx2967_i2c_quirks = {
492 .flags = I2C_AQ_NO_ZERO_LEN,
495 static const struct of_device_id zx2967_i2c_of_match[] = {
496 { .compatible = "zte,zx296718-i2c", },
499 MODULE_DEVICE_TABLE(of, zx2967_i2c_of_match);
501 static int zx2967_i2c_probe(struct platform_device *pdev)
503 struct zx2967_i2c *i2c;
504 void __iomem *reg_base;
508 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
512 reg_base = devm_platform_ioremap_resource(pdev, 0);
513 if (IS_ERR(reg_base))
514 return PTR_ERR(reg_base);
516 clk = devm_clk_get(&pdev->dev, NULL);
518 dev_err(&pdev->dev, "missing controller clock");
522 ret = clk_prepare_enable(clk);
524 dev_err(&pdev->dev, "failed to enable i2c_clk\n");
528 ret = device_property_read_u32(&pdev->dev, "clock-frequency",
531 dev_err(&pdev->dev, "missing clock-frequency");
535 ret = platform_get_irq(pdev, 0);
540 i2c->reg_base = reg_base;
543 init_completion(&i2c->complete);
544 platform_set_drvdata(pdev, i2c);
546 ret = zx2967_i2c_reset_hardware(i2c);
548 dev_err(&pdev->dev, "failed to initialize i2c controller\n");
549 goto err_clk_unprepare;
552 ret = devm_request_irq(&pdev->dev, i2c->irq,
553 zx2967_i2c_isr, 0, dev_name(&pdev->dev), i2c);
555 dev_err(&pdev->dev, "failed to request irq %i\n", i2c->irq);
556 goto err_clk_unprepare;
559 i2c_set_adapdata(&i2c->adap, i2c);
560 strlcpy(i2c->adap.name, "zx2967 i2c adapter",
561 sizeof(i2c->adap.name));
562 i2c->adap.algo = &zx2967_i2c_algo;
563 i2c->adap.quirks = &zx2967_i2c_quirks;
564 i2c->adap.nr = pdev->id;
565 i2c->adap.dev.parent = &pdev->dev;
566 i2c->adap.dev.of_node = pdev->dev.of_node;
568 ret = i2c_add_numbered_adapter(&i2c->adap);
570 goto err_clk_unprepare;
575 clk_disable_unprepare(i2c->clk);
579 static int zx2967_i2c_remove(struct platform_device *pdev)
581 struct zx2967_i2c *i2c = platform_get_drvdata(pdev);
583 i2c_del_adapter(&i2c->adap);
584 clk_disable_unprepare(i2c->clk);
589 static struct platform_driver zx2967_i2c_driver = {
590 .probe = zx2967_i2c_probe,
591 .remove = zx2967_i2c_remove,
593 .name = "zx2967_i2c",
594 .of_match_table = zx2967_i2c_of_match,
595 .pm = &zx2967_i2c_dev_pm_ops,
598 module_platform_driver(zx2967_i2c_driver);
600 MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
601 MODULE_DESCRIPTION("ZTE ZX2967 I2C Bus Controller driver");
602 MODULE_LICENSE("GPL v2");