drivers/i2c/busses/i2c-zx2967.c

   1 /*
   2  * Copyright (C) 2017 Sanechips Technology Co., Ltd.
   3  * Copyright 2017 Linaro Ltd.
   4  *
   5  * Author: Baoyou Xie <baoyou.xie@linaro.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/i2c.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18
  19 #define REG_CMD                         0x04
  20 #define REG_DEVADDR_H                   0x0C
  21 #define REG_DEVADDR_L                   0x10
  22 #define REG_CLK_DIV_FS                  0x14
  23 #define REG_CLK_DIV_HS                  0x18
  24 #define REG_WRCONF                      0x1C
  25 #define REG_RDCONF                      0x20
  26 #define REG_DATA                        0x24
  27 #define REG_STAT                        0x28
  28
  29 #define I2C_STOP                        0
  30 #define I2C_MASTER                      BIT(0)
  31 #define I2C_ADDR_MODE_TEN               BIT(1)
  32 #define I2C_IRQ_MSK_ENABLE              BIT(3)
  33 #define I2C_RW_READ                     BIT(4)
  34 #define I2C_CMB_RW_EN                   BIT(5)
  35 #define I2C_START                       BIT(6)
  36
  37 #define I2C_ADDR_LOW_MASK               GENMASK(6, 0)
  38 #define I2C_ADDR_LOW_SHIFT              0
  39 #define I2C_ADDR_HI_MASK                GENMASK(2, 0)
  40 #define I2C_ADDR_HI_SHIFT               7
  41
  42 #define I2C_WFIFO_RESET                 BIT(7)
  43 #define I2C_RFIFO_RESET                 BIT(7)
  44
  45 #define I2C_IRQ_ACK_CLEAR               BIT(7)
  46 #define I2C_INT_MASK                    GENMASK(6, 0)
  47
  48 #define I2C_TRANS_DONE                  BIT(0)
  49 #define I2C_SR_EDEVICE                  BIT(1)
  50 #define I2C_SR_EDATA                    BIT(2)
  51
  52 #define I2C_FIFO_MAX                    16
  53
  54 #define I2C_TIMEOUT                     msecs_to_jiffies(1000)
  55
  56 #define DEV(i2c)                        ((i2c)->adap.dev.parent)
  57
  58 struct zx2967_i2c {
  59         struct i2c_adapter      adap;
  60         struct clk              *clk;
  61         struct completion       complete;
  62         u32                     clk_freq;
  63         void __iomem            *reg_base;
  64         size_t                  residue;
  65         int                     irq;
  66         int                     msg_rd;
  67         u8                      *cur_trans;
  68         u8                      access_cnt;
  69         int                     error;
  70 };
  71
  72 static void zx2967_i2c_writel(struct zx2967_i2c *i2c,
  73                               u32 val, unsigned long reg)
  74 {
  75         writel_relaxed(val, i2c->reg_base + reg);
  76 }
  77
  78 static u32 zx2967_i2c_readl(struct zx2967_i2c *i2c, unsigned long reg)
  79 {
  80         return readl_relaxed(i2c->reg_base + reg);
  81 }
  82
  83 static void zx2967_i2c_writesb(struct zx2967_i2c *i2c,
  84                                void *data, unsigned long reg, int len)
  85 {
  86         writesb(i2c->reg_base + reg, data, len);
  87 }
  88
  89 static void zx2967_i2c_readsb(struct zx2967_i2c *i2c,
  90                               void *data, unsigned long reg, int len)
  91 {
  92         readsb(i2c->reg_base + reg, data, len);
  93 }
  94
  95 static void zx2967_i2c_start_ctrl(struct zx2967_i2c *i2c)
  96 {
  97         u32 status;
  98         u32 ctl;
  99
 100         status = zx2967_i2c_readl(i2c, REG_STAT);
 101         status |= I2C_IRQ_ACK_CLEAR;
 102         zx2967_i2c_writel(i2c, status, REG_STAT);
 103
 104         ctl = zx2967_i2c_readl(i2c, REG_CMD);
 105         if (i2c->msg_rd)
 106                 ctl |= I2C_RW_READ;
 107         else
 108                 ctl &= ~I2C_RW_READ;
 109         ctl &= ~I2C_CMB_RW_EN;
 110         ctl |= I2C_START;
 111         zx2967_i2c_writel(i2c, ctl, REG_CMD);
 112 }
 113
 114 static void zx2967_i2c_flush_fifos(struct zx2967_i2c *i2c)
 115 {
 116         u32 offset;
 117         u32 val;
 118
 119         if (i2c->msg_rd) {
 120                 offset = REG_RDCONF;
 121                 val = I2C_RFIFO_RESET;
 122         } else {
 123                 offset = REG_WRCONF;
 124                 val = I2C_WFIFO_RESET;
 125         }
 126
 127         val |= zx2967_i2c_readl(i2c, offset);
 128         zx2967_i2c_writel(i2c, val, offset);
 129 }
 130
 131 static int zx2967_i2c_empty_rx_fifo(struct zx2967_i2c *i2c, u32 size)
 132 {
 133         u8 val[I2C_FIFO_MAX] = {0};
 134         int i;
 135
 136         if (size > I2C_FIFO_MAX) {
 137                 dev_err(DEV(i2c), "fifo size %d over the max value %d\n",
 138                         size, I2C_FIFO_MAX);
 139                 return -EINVAL;
 140         }
 141
 142         zx2967_i2c_readsb(i2c, val, REG_DATA, size);
 143         for (i = 0; i < size; i++) {
 144                 *i2c->cur_trans++ = val[i];
 145                 i2c->residue--;
 146         }
 147
 148         barrier();
 149
 150         return 0;
 151 }
 152
 153 static int zx2967_i2c_fill_tx_fifo(struct zx2967_i2c *i2c)
 154 {
 155         size_t residue = i2c->residue;
 156         u8 *buf = i2c->cur_trans;
 157
 158         if (residue == 0) {
 159                 dev_err(DEV(i2c), "residue is %d\n", (int)residue);
 160                 return -EINVAL;
 161         }
 162
 163         if (residue <= I2C_FIFO_MAX) {
 164                 zx2967_i2c_writesb(i2c, buf, REG_DATA, residue);
 165
 166                 /* Again update before writing to FIFO to make sure isr sees. */
 167                 i2c->residue = 0;
 168                 i2c->cur_trans = NULL;
 169         } else {
 170                 zx2967_i2c_writesb(i2c, buf, REG_DATA, I2C_FIFO_MAX);
 171                 i2c->residue -= I2C_FIFO_MAX;
 172                 i2c->cur_trans += I2C_FIFO_MAX;
 173         }
 174
 175         barrier();
 176
 177         return 0;
 178 }
 179
 180 static int zx2967_i2c_reset_hardware(struct zx2967_i2c *i2c)
 181 {
 182         u32 val;
 183         u32 clk_div;
 184
 185         val = I2C_MASTER | I2C_IRQ_MSK_ENABLE;
 186         zx2967_i2c_writel(i2c, val, REG_CMD);
 187
 188         clk_div = clk_get_rate(i2c->clk) / i2c->clk_freq - 1;
 189         zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_FS);
 190         zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_HS);
 191
 192         zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_WRCONF);
 193         zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_RDCONF);
 194         zx2967_i2c_writel(i2c, 1, REG_RDCONF);
 195
 196         zx2967_i2c_flush_fifos(i2c);
 197
 198         return 0;
 199 }
 200
 201 static void zx2967_i2c_isr_clr(struct zx2967_i2c *i2c)
 202 {
 203         u32 status;
 204
 205         status = zx2967_i2c_readl(i2c, REG_STAT);
 206         status |= I2C_IRQ_ACK_CLEAR;
 207         zx2967_i2c_writel(i2c, status, REG_STAT);
 208 }
 209
 210 static irqreturn_t zx2967_i2c_isr(int irq, void *dev_id)
 211 {
 212         u32 status;
 213         struct zx2967_i2c *i2c = (struct zx2967_i2c *)dev_id;
 214
 215         status = zx2967_i2c_readl(i2c, REG_STAT) & I2C_INT_MASK;
 216         zx2967_i2c_isr_clr(i2c);
 217
 218         if (status & I2C_SR_EDEVICE)
 219                 i2c->error = -ENXIO;
 220         else if (status & I2C_SR_EDATA)
 221                 i2c->error = -EIO;
 222         else if (status & I2C_TRANS_DONE)
 223                 i2c->error = 0;
 224         else
 225                 goto done;
 226
 227         complete(&i2c->complete);
 228 done:
 229         return IRQ_HANDLED;
 230 }
 231
 232 static void zx2967_set_addr(struct zx2967_i2c *i2c, u16 addr)
 233 {
 234         u16 val;
 235
 236         val = (addr >> I2C_ADDR_LOW_SHIFT) & I2C_ADDR_LOW_MASK;
 237         zx2967_i2c_writel(i2c, val, REG_DEVADDR_L);
 238
 239         val = (addr >> I2C_ADDR_HI_SHIFT) & I2C_ADDR_HI_MASK;
 240         zx2967_i2c_writel(i2c, val, REG_DEVADDR_H);
 241         if (val)
 242                 val = zx2967_i2c_readl(i2c, REG_CMD) | I2C_ADDR_MODE_TEN;
 243         else
 244                 val = zx2967_i2c_readl(i2c, REG_CMD) & ~I2C_ADDR_MODE_TEN;
 245         zx2967_i2c_writel(i2c, val, REG_CMD);
 246 }
 247
 248 static int zx2967_i2c_xfer_bytes(struct zx2967_i2c *i2c, u32 bytes)
 249 {
 250         unsigned long time_left;
 251         int rd = i2c->msg_rd;
 252         int ret;
 253
 254         reinit_completion(&i2c->complete);
 255
 256         if (rd) {
 257                 zx2967_i2c_writel(i2c, bytes - 1, REG_RDCONF);
 258         } else {
 259                 ret = zx2967_i2c_fill_tx_fifo(i2c);
 260                 if (ret)
 261                         return ret;
 262         }
 263
 264         zx2967_i2c_start_ctrl(i2c);
 265
 266         time_left = wait_for_completion_timeout(&i2c->complete,
 267                                                 I2C_TIMEOUT);
 268         if (time_left == 0)
 269                 return -ETIMEDOUT;
 270
 271         if (i2c->error)
 272                 return i2c->error;
 273
 274         return rd ? zx2967_i2c_empty_rx_fifo(i2c, bytes) : 0;
 275 }
 276
 277 static int zx2967_i2c_xfer_msg(struct zx2967_i2c *i2c,
 278                                struct i2c_msg *msg)
 279 {
 280         int ret;
 281         int i;
 282
 283         zx2967_i2c_flush_fifos(i2c);
 284
 285         i2c->cur_trans = msg->buf;
 286         i2c->residue = msg->len;
 287         i2c->access_cnt = msg->len / I2C_FIFO_MAX;
 288         i2c->msg_rd = msg->flags & I2C_M_RD;
 289
 290         for (i = 0; i < i2c->access_cnt; i++) {
 291                 ret = zx2967_i2c_xfer_bytes(i2c, I2C_FIFO_MAX);
 292                 if (ret)
 293                         return ret;
 294         }
 295
 296         if (i2c->residue > 0) {
 297                 ret = zx2967_i2c_xfer_bytes(i2c, i2c->residue);
 298                 if (ret)
 299                         return ret;
 300         }
 301
 302         i2c->residue = 0;
 303         i2c->access_cnt = 0;
 304
 305         return 0;
 306 }
 307
 308 static int zx2967_i2c_xfer(struct i2c_adapter *adap,
 309                            struct i2c_msg *msgs, int num)
 310 {
 311         struct zx2967_i2c *i2c = i2c_get_adapdata(adap);
 312         int ret;
 313         int i;
 314
 315         zx2967_set_addr(i2c, msgs->addr);
 316
 317         for (i = 0; i < num; i++) {
 318                 ret = zx2967_i2c_xfer_msg(i2c, &msgs[i]);
 319                 if (ret)
 320                         return ret;
 321         }
 322
 323         return num;
 324 }
 325
 326 static void
 327 zx2967_smbus_xfer_prepare(struct zx2967_i2c *i2c, u16 addr,
 328                           char read_write, u8 command, int size,
 329                           union i2c_smbus_data *data)
 330 {
 331         u32 val;
 332
 333         val = zx2967_i2c_readl(i2c, REG_RDCONF);
 334         val |= I2C_RFIFO_RESET;
 335         zx2967_i2c_writel(i2c, val, REG_RDCONF);
 336         zx2967_set_addr(i2c, addr);
 337         val = zx2967_i2c_readl(i2c, REG_CMD);
 338         val &= ~I2C_RW_READ;
 339         zx2967_i2c_writel(i2c, val, REG_CMD);
 340
 341         switch (size) {
 342         case I2C_SMBUS_BYTE:
 343                 zx2967_i2c_writel(i2c, command, REG_DATA);
 344                 break;
 345         case I2C_SMBUS_BYTE_DATA:
 346                 zx2967_i2c_writel(i2c, command, REG_DATA);
 347                 if (read_write == I2C_SMBUS_WRITE)
 348                         zx2967_i2c_writel(i2c, data->byte, REG_DATA);
 349                 break;
 350         case I2C_SMBUS_WORD_DATA:
 351                 zx2967_i2c_writel(i2c, command, REG_DATA);
 352                 if (read_write == I2C_SMBUS_WRITE) {
 353                         zx2967_i2c_writel(i2c, (data->word >> 8), REG_DATA);
 354                         zx2967_i2c_writel(i2c, (data->word & 0xff),
 355                                           REG_DATA);
 356                 }
 357                 break;
 358         }
 359 }
 360
 361 static int zx2967_smbus_xfer_read(struct zx2967_i2c *i2c, int size,
 362                                   union i2c_smbus_data *data)
 363 {
 364         unsigned long time_left;
 365         u8 buf[2];
 366         u32 val;
 367
 368         reinit_completion(&i2c->complete);
 369
 370         val = zx2967_i2c_readl(i2c, REG_CMD);
 371         val |= I2C_CMB_RW_EN;
 372         zx2967_i2c_writel(i2c, val, REG_CMD);
 373
 374         val = zx2967_i2c_readl(i2c, REG_CMD);
 375         val |= I2C_START;
 376         zx2967_i2c_writel(i2c, val, REG_CMD);
 377
 378         time_left = wait_for_completion_timeout(&i2c->complete,
 379                                                 I2C_TIMEOUT);
 380         if (time_left == 0)
 381                 return -ETIMEDOUT;
 382
 383         if (i2c->error)
 384                 return i2c->error;
 385
 386         switch (size) {
 387         case I2C_SMBUS_BYTE:
 388         case I2C_SMBUS_BYTE_DATA:
 389                 val = zx2967_i2c_readl(i2c, REG_DATA);
 390                 data->byte = val;
 391                 break;
 392         case I2C_SMBUS_WORD_DATA:
 393         case I2C_SMBUS_PROC_CALL:
 394                 buf[0] = zx2967_i2c_readl(i2c, REG_DATA);
 395                 buf[1] = zx2967_i2c_readl(i2c, REG_DATA);
 396                 data->word = (buf[0] << 8) | buf[1];
 397                 break;
 398         default:
 399                 return -EOPNOTSUPP;
 400         }
 401
 402         return 0;
 403 }
 404
 405 static int zx2967_smbus_xfer_write(struct zx2967_i2c *i2c)
 406 {
 407         unsigned long time_left;
 408         u32 val;
 409
 410         reinit_completion(&i2c->complete);
 411         val = zx2967_i2c_readl(i2c, REG_CMD);
 412         val |= I2C_START;
 413         zx2967_i2c_writel(i2c, val, REG_CMD);
 414
 415         time_left = wait_for_completion_timeout(&i2c->complete,
 416                                                 I2C_TIMEOUT);
 417         if (time_left == 0)
 418                 return -ETIMEDOUT;
 419
 420         if (i2c->error)
 421                 return i2c->error;
 422
 423         return 0;
 424 }
 425
 426 static int zx2967_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 427                              unsigned short flags, char read_write,
 428                              u8 command, int size, union i2c_smbus_data *data)
 429 {
 430         struct zx2967_i2c *i2c = i2c_get_adapdata(adap);
 431
 432         if (size == I2C_SMBUS_QUICK)
 433                 read_write = I2C_SMBUS_WRITE;
 434
 435         switch (size) {
 436         case I2C_SMBUS_QUICK:
 437         case I2C_SMBUS_BYTE:
 438         case I2C_SMBUS_BYTE_DATA:
 439         case I2C_SMBUS_WORD_DATA:
 440                 zx2967_smbus_xfer_prepare(i2c, addr, read_write,
 441                                           command, size, data);
 442                 break;
 443         default:
 444                 return -EOPNOTSUPP;
 445         }
 446
 447         if (read_write == I2C_SMBUS_READ)
 448                 return zx2967_smbus_xfer_read(i2c, size, data);
 449
 450         return zx2967_smbus_xfer_write(i2c);
 451 }
 452
 453 static u32 zx2967_i2c_func(struct i2c_adapter *adap)
 454 {
 455         return I2C_FUNC_I2C |
 456                I2C_FUNC_SMBUS_QUICK |
 457                I2C_FUNC_SMBUS_BYTE |
 458                I2C_FUNC_SMBUS_BYTE_DATA |
 459                I2C_FUNC_SMBUS_WORD_DATA |
 460                I2C_FUNC_SMBUS_BLOCK_DATA |
 461                I2C_FUNC_SMBUS_PROC_CALL |
 462                I2C_FUNC_SMBUS_I2C_BLOCK;
 463 }
 464
 465 static int __maybe_unused zx2967_i2c_suspend(struct device *dev)
 466 {
 467         struct zx2967_i2c *i2c = dev_get_drvdata(dev);
 468
 469         i2c_mark_adapter_suspended(&i2c->adap);
 470         clk_disable_unprepare(i2c->clk);
 471
 472         return 0;
 473 }
 474
 475 static int __maybe_unused zx2967_i2c_resume(struct device *dev)
 476 {
 477         struct zx2967_i2c *i2c = dev_get_drvdata(dev);
 478
 479         clk_prepare_enable(i2c->clk);
 480         i2c_mark_adapter_resumed(&i2c->adap);
 481
 482         return 0;
 483 }
 484
 485 static SIMPLE_DEV_PM_OPS(zx2967_i2c_dev_pm_ops,
 486                          zx2967_i2c_suspend, zx2967_i2c_resume);
 487
 488 static const struct i2c_algorithm zx2967_i2c_algo = {
 489         .master_xfer = zx2967_i2c_xfer,
 490         .smbus_xfer = zx2967_smbus_xfer,
 491         .functionality = zx2967_i2c_func,
 492 };
 493
 494 static const struct i2c_adapter_quirks zx2967_i2c_quirks = {
 495         .flags = I2C_AQ_NO_ZERO_LEN,
 496 };
 497
 498 static const struct of_device_id zx2967_i2c_of_match[] = {
 499         { .compatible = "zte,zx296718-i2c", },
 500         { },
 501 };
 502 MODULE_DEVICE_TABLE(of, zx2967_i2c_of_match);
 503
 504 static int zx2967_i2c_probe(struct platform_device *pdev)
 505 {
 506         struct zx2967_i2c *i2c;
 507         void __iomem *reg_base;
 508         struct resource *res;
 509         struct clk *clk;
 510         int ret;
 511
 512         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 513         if (!i2c)
 514                 return -ENOMEM;
 515
 516         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 517         reg_base = devm_ioremap_resource(&pdev->dev, res);
 518         if (IS_ERR(reg_base))
 519                 return PTR_ERR(reg_base);
 520
 521         clk = devm_clk_get(&pdev->dev, NULL);
 522         if (IS_ERR(clk)) {
 523                 dev_err(&pdev->dev, "missing controller clock");
 524                 return PTR_ERR(clk);
 525         }
 526
 527         ret = clk_prepare_enable(clk);
 528         if (ret) {
 529                 dev_err(&pdev->dev, "failed to enable i2c_clk\n");
 530                 return ret;
 531         }
 532
 533         ret = device_property_read_u32(&pdev->dev, "clock-frequency",
 534                                        &i2c->clk_freq);
 535         if (ret) {
 536                 dev_err(&pdev->dev, "missing clock-frequency");
 537                 return ret;
 538         }
 539
 540         ret = platform_get_irq(pdev, 0);
 541         if (ret < 0)
 542                 return ret;
 543
 544         i2c->irq = ret;
 545         i2c->reg_base = reg_base;
 546         i2c->clk = clk;
 547
 548         init_completion(&i2c->complete);
 549         platform_set_drvdata(pdev, i2c);
 550
 551         ret = zx2967_i2c_reset_hardware(i2c);
 552         if (ret) {
 553                 dev_err(&pdev->dev, "failed to initialize i2c controller\n");
 554                 goto err_clk_unprepare;
 555         }
 556
 557         ret = devm_request_irq(&pdev->dev, i2c->irq,
 558                         zx2967_i2c_isr, 0, dev_name(&pdev->dev), i2c);
 559         if (ret) {
 560                 dev_err(&pdev->dev, "failed to request irq %i\n", i2c->irq);
 561                 goto err_clk_unprepare;
 562         }
 563
 564         i2c_set_adapdata(&i2c->adap, i2c);
 565         strlcpy(i2c->adap.name, "zx2967 i2c adapter",
 566                 sizeof(i2c->adap.name));
 567         i2c->adap.algo = &zx2967_i2c_algo;
 568         i2c->adap.quirks = &zx2967_i2c_quirks;
 569         i2c->adap.nr = pdev->id;
 570         i2c->adap.dev.parent = &pdev->dev;
 571         i2c->adap.dev.of_node = pdev->dev.of_node;
 572
 573         ret = i2c_add_numbered_adapter(&i2c->adap);
 574         if (ret)
 575                 goto err_clk_unprepare;
 576
 577         return 0;
 578
 579 err_clk_unprepare:
 580         clk_disable_unprepare(i2c->clk);
 581         return ret;
 582 }
 583
 584 static int zx2967_i2c_remove(struct platform_device *pdev)
 585 {
 586         struct zx2967_i2c *i2c = platform_get_drvdata(pdev);
 587
 588         i2c_del_adapter(&i2c->adap);
 589         clk_disable_unprepare(i2c->clk);
 590
 591         return 0;
 592 }
 593
 594 static struct platform_driver zx2967_i2c_driver = {
 595         .probe  = zx2967_i2c_probe,
 596         .remove = zx2967_i2c_remove,
 597         .driver = {
 598                 .name  = "zx2967_i2c",
 599                 .of_match_table = zx2967_i2c_of_match,
 600                 .pm = &zx2967_i2c_dev_pm_ops,
 601         },
 602 };
 603 module_platform_driver(zx2967_i2c_driver);
 604
 605 MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
 606 MODULE_DESCRIPTION("ZTE ZX2967 I2C Bus Controller driver");
 607 MODULE_LICENSE("GPL v2");