1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Wondermedia I2C Master Mode Driver
5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
7 * Derived from GPLv2+ licensed source:
8 * - Copyright (C) 2008 WonderMedia Technologies, Inc.
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/err.h>
14 #include <linux/i2c.h>
15 #include <linux/interrupt.h>
17 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/platform_device.h>
31 #define REG_SLAVE_CR 0x10
32 #define REG_SLAVE_SR 0x12
33 #define REG_SLAVE_ISR 0x14
34 #define REG_SLAVE_IMR 0x16
35 #define REG_SLAVE_DR 0x18
36 #define REG_SLAVE_TR 0x1A
38 /* REG_CR Bit fields */
39 #define CR_TX_NEXT_ACK 0x0000
40 #define CR_ENABLE 0x0001
41 #define CR_TX_NEXT_NO_ACK 0x0002
42 #define CR_TX_END 0x0004
43 #define CR_CPU_RDY 0x0008
44 #define SLAV_MODE_SEL 0x8000
46 /* REG_TCR Bit fields */
47 #define TCR_STANDARD_MODE 0x0000
48 #define TCR_MASTER_WRITE 0x0000
49 #define TCR_HS_MODE 0x2000
50 #define TCR_MASTER_READ 0x4000
51 #define TCR_FAST_MODE 0x8000
52 #define TCR_SLAVE_ADDR_MASK 0x007F
54 /* REG_ISR Bit fields */
55 #define ISR_NACK_ADDR 0x0001
56 #define ISR_BYTE_END 0x0002
57 #define ISR_SCL_TIMEOUT 0x0004
58 #define ISR_WRITE_ALL 0x0007
60 /* REG_IMR Bit fields */
61 #define IMR_ENABLE_ALL 0x0007
63 /* REG_CSR Bit fields */
64 #define CSR_RCV_NOT_ACK 0x0001
65 #define CSR_RCV_ACK_MASK 0x0001
66 #define CSR_READY_MASK 0x0002
69 #define SCL_TIMEOUT(x) (((x) & 0xFF) << 8)
75 #define MCR_APB_166M 12
77 #define I2C_MODE_STANDARD 0
78 #define I2C_MODE_FAST 1
80 #define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000))
83 struct i2c_adapter adapter;
84 struct completion complete;
93 static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
95 unsigned long timeout;
97 timeout = jiffies + WMT_I2C_TIMEOUT;
98 while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) {
99 if (time_after(jiffies, timeout)) {
100 dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n");
109 static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
113 if (i2c_dev->cmd_status & ISR_NACK_ADDR)
116 if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
122 static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
125 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
128 unsigned long wait_result;
131 if (!(pmsg->flags & I2C_M_NOSTART)) {
132 ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
137 if (pmsg->len == 0) {
139 * We still need to run through the while (..) once, so
140 * start at -1 and break out early from the loop
143 writew(0, i2c_dev->base + REG_CDR);
145 writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
148 if (!(pmsg->flags & I2C_M_NOSTART)) {
149 val = readw(i2c_dev->base + REG_CR);
151 writew(val, i2c_dev->base + REG_CR);
153 val = readw(i2c_dev->base + REG_CR);
155 writew(val, i2c_dev->base + REG_CR);
158 reinit_completion(&i2c_dev->complete);
160 if (i2c_dev->mode == I2C_MODE_STANDARD)
161 tcr_val = TCR_STANDARD_MODE;
163 tcr_val = TCR_FAST_MODE;
165 tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
167 writew(tcr_val, i2c_dev->base + REG_TCR);
169 if (pmsg->flags & I2C_M_NOSTART) {
170 val = readw(i2c_dev->base + REG_CR);
172 writew(val, i2c_dev->base + REG_CR);
175 while (xfer_len < pmsg->len) {
176 wait_result = wait_for_completion_timeout(&i2c_dev->complete,
177 msecs_to_jiffies(500));
179 if (wait_result == 0)
182 ret = wmt_check_status(i2c_dev);
188 val = readw(i2c_dev->base + REG_CSR);
189 if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
190 dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
194 if (pmsg->len == 0) {
195 val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
196 writew(val, i2c_dev->base + REG_CR);
200 if (xfer_len == pmsg->len) {
202 writew(CR_ENABLE, i2c_dev->base + REG_CR);
204 writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
206 writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
213 static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
216 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
219 unsigned long wait_result;
222 if (!(pmsg->flags & I2C_M_NOSTART)) {
223 ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
228 val = readw(i2c_dev->base + REG_CR);
230 writew(val, i2c_dev->base + REG_CR);
232 val = readw(i2c_dev->base + REG_CR);
233 val &= ~CR_TX_NEXT_NO_ACK;
234 writew(val, i2c_dev->base + REG_CR);
236 if (!(pmsg->flags & I2C_M_NOSTART)) {
237 val = readw(i2c_dev->base + REG_CR);
239 writew(val, i2c_dev->base + REG_CR);
242 if (pmsg->len == 1) {
243 val = readw(i2c_dev->base + REG_CR);
244 val |= CR_TX_NEXT_NO_ACK;
245 writew(val, i2c_dev->base + REG_CR);
248 reinit_completion(&i2c_dev->complete);
250 if (i2c_dev->mode == I2C_MODE_STANDARD)
251 tcr_val = TCR_STANDARD_MODE;
253 tcr_val = TCR_FAST_MODE;
255 tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
257 writew(tcr_val, i2c_dev->base + REG_TCR);
259 if (pmsg->flags & I2C_M_NOSTART) {
260 val = readw(i2c_dev->base + REG_CR);
262 writew(val, i2c_dev->base + REG_CR);
265 while (xfer_len < pmsg->len) {
266 wait_result = wait_for_completion_timeout(&i2c_dev->complete,
267 msecs_to_jiffies(500));
272 ret = wmt_check_status(i2c_dev);
276 pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
279 if (xfer_len == pmsg->len - 1) {
280 val = readw(i2c_dev->base + REG_CR);
281 val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
282 writew(val, i2c_dev->base + REG_CR);
284 val = readw(i2c_dev->base + REG_CR);
286 writew(val, i2c_dev->base + REG_CR);
293 static int wmt_i2c_xfer(struct i2c_adapter *adap,
294 struct i2c_msg msgs[],
297 struct i2c_msg *pmsg;
301 for (i = 0; ret >= 0 && i < num; i++) {
302 is_last = ((i + 1) == num);
305 if (pmsg->flags & I2C_M_RD)
306 ret = wmt_i2c_read(adap, pmsg, is_last);
308 ret = wmt_i2c_write(adap, pmsg, is_last);
311 return (ret < 0) ? ret : i;
314 static u32 wmt_i2c_func(struct i2c_adapter *adap)
316 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART;
319 static const struct i2c_algorithm wmt_i2c_algo = {
320 .master_xfer = wmt_i2c_xfer,
321 .functionality = wmt_i2c_func,
324 static irqreturn_t wmt_i2c_isr(int irq, void *data)
326 struct wmt_i2c_dev *i2c_dev = data;
328 /* save the status and write-clear it */
329 i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
330 writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
332 complete(&i2c_dev->complete);
337 static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
341 err = clk_prepare_enable(i2c_dev->clk);
343 dev_err(i2c_dev->dev, "failed to enable clock\n");
347 err = clk_set_rate(i2c_dev->clk, 20000000);
349 dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
350 clk_disable_unprepare(i2c_dev->clk);
354 writew(0, i2c_dev->base + REG_CR);
355 writew(MCR_APB_166M, i2c_dev->base + REG_MCR);
356 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
357 writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
358 writew(CR_ENABLE, i2c_dev->base + REG_CR);
359 readw(i2c_dev->base + REG_CSR); /* read clear */
360 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
362 if (i2c_dev->mode == I2C_MODE_STANDARD)
363 writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR);
365 writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR);
370 static int wmt_i2c_probe(struct platform_device *pdev)
372 struct device_node *np = pdev->dev.of_node;
373 struct wmt_i2c_dev *i2c_dev;
374 struct i2c_adapter *adap;
375 struct resource *res;
379 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
383 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
384 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
385 if (IS_ERR(i2c_dev->base))
386 return PTR_ERR(i2c_dev->base);
388 i2c_dev->irq = irq_of_parse_and_map(np, 0);
390 dev_err(&pdev->dev, "irq missing or invalid\n");
394 i2c_dev->clk = of_clk_get(np, 0);
395 if (IS_ERR(i2c_dev->clk)) {
396 dev_err(&pdev->dev, "unable to request clock\n");
397 return PTR_ERR(i2c_dev->clk);
400 i2c_dev->mode = I2C_MODE_STANDARD;
401 err = of_property_read_u32(np, "clock-frequency", &clk_rate);
402 if (!err && (clk_rate == I2C_MAX_FAST_MODE_FREQ))
403 i2c_dev->mode = I2C_MODE_FAST;
405 i2c_dev->dev = &pdev->dev;
407 err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
410 dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
414 adap = &i2c_dev->adapter;
415 i2c_set_adapdata(adap, i2c_dev);
416 strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
417 adap->owner = THIS_MODULE;
418 adap->algo = &wmt_i2c_algo;
419 adap->dev.parent = &pdev->dev;
420 adap->dev.of_node = pdev->dev.of_node;
422 init_completion(&i2c_dev->complete);
424 err = wmt_i2c_reset_hardware(i2c_dev);
426 dev_err(&pdev->dev, "error initializing hardware\n");
430 err = i2c_add_adapter(adap);
434 platform_set_drvdata(pdev, i2c_dev);
439 static int wmt_i2c_remove(struct platform_device *pdev)
441 struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
443 /* Disable interrupts, clock and delete adapter */
444 writew(0, i2c_dev->base + REG_IMR);
445 clk_disable_unprepare(i2c_dev->clk);
446 i2c_del_adapter(&i2c_dev->adapter);
451 static const struct of_device_id wmt_i2c_dt_ids[] = {
452 { .compatible = "wm,wm8505-i2c" },
456 static struct platform_driver wmt_i2c_driver = {
457 .probe = wmt_i2c_probe,
458 .remove = wmt_i2c_remove,
461 .of_match_table = wmt_i2c_dt_ids,
465 module_platform_driver(wmt_i2c_driver);
467 MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
468 MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
469 MODULE_LICENSE("GPL");
470 MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);